JPS6231439A - Instruction reprocessing control system - Google Patents

Abstract

PURPOSE:To improve the instruction reprocessing efficiency when an error is produced by changing a reprocessing instruction to an invalid action instruction after the parallel executing processes are through and when the decoding processing is unfinished. CONSTITUTION:An executing process is over with an execution end signal 23 turned on and the decoding processes to be executed in parallel are unfinished with a decoding end signal 22 turned off respectively. Under such conditions, a switch 20 is changed over by the output of a gate 21. Then an advance instruction for reprocessing which is given from an executing instruction buffer 3 in response to a retry signal 4 is switched to an invalid operation NOP instruction and supplied to a decoding instruction buffer 2. This NOP instruction is processed as a dummy and a processed instruction is not processed again to omit a big change of the control. This reduces the waste processing time. Thus the instruction processing efficiency is improved when an error is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [1] A control method for reprocessing instructions when an error is detected in a processing device of a computer system. In a processing device that executes an instruction and decodes the subsequent instruction in parallel using so-called pipeline control, the instruction being executed is returned to the decoding stage to reprocess the instruction. When an instruction is delayed and a reprocessing factor is detected while only the subsequent instruction is being decoded after the preceding instruction has been executed, the invalid operation instruction is reprocessed instead of the preceding instruction. Avoid wasted reprocessing time.

[Industrial application field]

The present invention relates to a control method for reprocessing instructions when an error is detected in a processing device of a computer system, particularly in a processing device configured using a so-called pipeline control method.

In a processing unit of a computer system, when an error such as an error in information related to the processing is detected during instruction processing, the processing of instructions after the instruction currently being processed is restarted from the beginning of the processing, A reprocessing (or retry) approach is often adopted.

With this method, if the error or the like is caused by an instantaneously existing cause and the cause disappears immediately, subsequent processing can be continued normally by reprocessing. Since this type of error, caused by external noise signals, for example, is not rare, the above reprocessing method is quite effective in improving the availability of the processing device.

[Prior Art and Problems to be Solved by the Invention] FIG. 2 is a block diagram showing a simple configuration example of an instruction buffering section in a pipeline control type processing device.

Each instruction is read from a main storage device (not shown), held in an instruction read buffer 1, and then sent to a decoding instruction buffer 2, where operation codes are decoded, operand addresses are calculated, and the like.

When the decoding process is completed, it is transferred to the execution instruction buffer 3,
At this point, instructions such as operations between operands are executed.

When one instruction moves from the decoding process to the execution process, the next instruction read out to the instruction read buffer 1 during this time is input to the decoding instruction buffer 2, and the execution process in the execution instruction buffer 3 and the decoding instruction buffer 2 are performed. The decoding process of the next instruction proceeds in parallel.

That is, as illustrated in FIG. 3 (al), instructions are read into the instruction read buffer 1 as instructions A, B, and C1-, and instructions A, B, and C1- are read into the decoding instruction buffer 2 after a delay of l stage control time. B- is transferred and decoding processing is performed, and after l stage time, instructions A and B- are transferred to the execution instruction buffer 3 and execution processing is performed.In this way, each part of the processing device is is used with high efficiency.

In this case, the transition between stages of each process is not necessarily at fixed time intervals, but is controlled by, for example, the longest parallel processing time, and usually the execution process takes at least the same amount of time as the decoding process. It is mostly dominated by execution processing time.

While processing is being performed in this way, if an error is detected in the test circuit of the related control circuit, the retry signal 4
is generated, controls buffering of instructions, returns the instruction in the execution instruction buffer 3 to the decoding instruction buffer via pass 5, and starts processing again starting from reprocessing this instruction.

That is, if an error occurrence is detected at time 10 during the execution process of instruction A in FIG. will be started.

As mentioned above, the instructions are read out continuously.
If it is not supplied, for example, there will be a waiting time in accessing the main memory, and the stage time 12 in FIG.
When the instruction B that follows the instruction A is not read out and is read out at the next stage time, as shown in the figure, an idle time occurs as shown by the broken line in the figure, and the previous instruction A is read out as shown in stage time 13. A state occurs in which the execution processing of instruction B is completed and only the decoding processing of the next instruction B is being performed.

If an error that causes reprocessing is detected at, for example, time 14 within this stage time, the above control returns the instruction A in the execution instruction buffer 3 to the decoding instruction buffer 2 and reprocesses it. is started.

However, in this case, since the execution process of instruction A has been completed normally, restarting the process of instruction A from the beginning is a waste of time on the processing device, especially if the execution process time of instruction A is long. big.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of the instruction buffering part of the processing unit,
20 is a switch for changing over a reprocessing command, and 21 is a gate forming a signal for controlling the switch 20.

[For production]

When loading an instruction to be reprocessed into the decoding buffer 2 by the retry signal 4, normally the execution instruction buffer 3
However, if the signal 22 indicating the end of the decoding process is off and the signal 23 indicating the end of the execution process is on, the switch 20 is switched and the invalid operation instruction is loaded.

Therefore, in the state as shown in FIG. without the need to significantly change
Wasted processing time is reduced.

〔Example〕

In FIG. 1, an instruction read buffer 1, a decode instruction buffer 2, and an execution instruction buffer 3 have the same functions as in the conventional example described above.

When an error causing reprocessing is detected, the retry signal 4 is used to load a required instruction into the decoding instruction buffer and reprocessing is started from the instruction.

However, according to the present invention, the instruction to be reprocessed is stored in the decoding buffer 2.
When loading the instruction into the execution instruction buffer 3, the instruction is normally connected via the switch 20, and the switch 20 is connected to load the instruction from the execution instruction buffer 3 via the path 5 as in the conventional case.

When the signal 22 indicating the end of the decoding process is off and the signal 23 indicating the end of the execution process is on (that is, the state at stage time 13 in FIG. 3 (bl)), the output of the gate 21 is turned on and the switch is turned on. 20 and loads the invalid operation instruction from the bus 24 into the decoding instruction buffer 2.

Therefore, in that case, in the state shown in FIG. .

The invalid operation instruction is a well-known so-called NOP instruction, and since it is a dummy instruction without any effective operation, the processing time is short, so there is no need to change the control significantly, and there is no need to waste processing time. reduced.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the efficiency of instruction reprocessing (retry) when an error occurs in a computer system is improved, so it has a significant industrial effect of improving the performance of processing devices, etc. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional configuration, and FIG. 3 is a timing diagram. In the figure, 1 is an instruction read buffer, 2 is a decoding instruction buffer, 3 is an execution instruction buffer, 4 is a retry signal, 20 is a switch, and 21 is a gate. Figure 2

Claims (1)

[Claims] When a computer system executes a preceding instruction and decodes a subsequent instruction in parallel, and a predetermined reprocessing factor is detected during the processing, the instruction being processed is decoded from the decoding process. In the reprocessing processing device, only the decoding process of the subsequent instruction is delayed until after the execution process of the preceding instruction is completed, and if the reprocessing factor is detected while the processing continues, the preceding instruction is invalidated. An instruction reprocessing control method characterized in that the instruction reprocessing control method is configured to convert into an operation instruction and reprocess it.