KR920006612B1 - Information processing apparatus - Google Patents

Abstract

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Description

Information processing device

1 is a diagram showing the main components of an information processing apparatus according to an embodiment of the present invention.

2 is a diagram for explaining the operation of the information processing apparatus shown in FIG.

FIG. 3 is a diagram showing a main structure of a preceding read control of a memory operand in a conventional information processing apparatus. FIG.

4 is a diagram for explaining the operation of the information processing apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

1: Instruction decoder 3,25: Operand buffer

5,7,15,19,27,29: AND gate 9: Hazard detector

13,31 OR gate 17 Bus controller

21: buffer circuit 23: internal bus

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus of a pipeline control method, and more particularly, to an information processing apparatus used for controlling to read out a memory operand prior to executing an instruction.

[Traditional Technology and Problems]

As a technique for speeding up an information processing apparatus, there is a pipeline control method. A pipeline control method refers to a control method that performs parallel processing and concurrent processing of an instruction during an instruction execution process.

In the above pipeline control method, if the operand information of the instruction, for example, the memory operand, is read before the instruction is executed, the processing speed is improved. That is, in an instruction that requires an operand in memory at the time of execution of the instruction, the memory operand can be read at the time when the instruction is decoded prior to executing the instruction so that the memory operand can be used simultaneously with the execution of the instruction. By controlling the memory access to the state, the processing speed of the information processing apparatus is improved.

In accessing such a memory operand, when the preceding instruction includes a write process to the memory, the preceding instruction may rewrite the memory information to be accessed by the next instruction. For this reason, the reading of the memory operand for the next instruction must be started after the writing process of the preceding instruction is completed.

However, since it is difficult to detect the end of the recording process of the preceding instruction, the memory operand related to the next instruction is usually read after the execution of the preceding instruction ends.

Hereinafter, the read operation of the memory operand will be described in detail with reference to FIG.

FIG. 3 is a diagram showing a main part configuration when reading a memory operand of an instruction in a conventional information processing apparatus.

First, the case where the preceding command is a command that does not include a write process to the memory will be described.

In Fig. 3, when an instruction is decoded by the instruction decoder 1, the memory address of the memory operand is set in the AP field of the operand buffer 3 from the instruction decoder 1. In addition, " 1 " is set in the AV bit of the operand buffer 3 to indicate the validity of the memory address of the AP field, and furthermore, the first access request signal is set to " 1 " to immediately access the memory operand. From (1), they are applied to one input terminal of the AND gates 5 and 7, respectively.

Here, the hazard detector 9 detects that the preceding command is a command which does not execute the write processing to the memory when the preceding command is decoded and sets the detection signal to "0". The signal is applied to the other input of the AND gate 5 via the inverter gate 11.

Therefore, while the first access request signal is applied to the AND gate 5, the output of the OR gate 13 which takes both outputs of the AND gates 5 and 7 as an input becomes "1". As a result, the A information indicating the memory access request is " 1 ", which is set in the A bit of the operand buffer 3.

When both the AV information and the A information become "1", the second access request signal, which is the output of the AND gate 15 which inputs the A information as the AV information, becomes "1", which is the second access request signal. Is applied to the bus controller 17, so that the access start signal is applied from the bus controller 17 to the external memory.

As a result, memory access is started so that the read memory operand is set in the DP field of the operand buffer 3. Furthermore, the DV information is " 1 " to indicate the validity of the DP field. Is set to the DV bit.

When " 1 " is set in the DV bit and the read symbol of the memory operand applied to the AND gate 19 becomes " 1 ", the memory operand is read out to the internal bus 23 via the buffer circuit 21. .

On the other hand, when the preceding command includes a write process to the memory, the detection signal of the hazard detector 9 becomes "1" and the output of the AND gate 5 becomes "0". For this reason, even if the first access request signal becomes "1", when the end signal indicating the end of execution of the preceding instruction becomes "1" and is not applied to the AND gate 7, "1" is not set in the A bit. Will not.

As described above, as a result of reading the memory operand, when the preceding instruction is an instruction including writing processing to the memory, access to the memory operand is started after the execution of the preceding instruction is terminated. Therefore, conventionally, the A bit of the operand buffer 3 cannot be set until the execution of the preceding instruction is completed.

Therefore, the instruction decoder 1 stops the decoding operation until the execution of the preceding instruction ends, as shown in FIG. 4, and starts the decoding operation again after the execution is completed to set the operand buffer 3. do. Furthermore, as shown in Fig. 4, the execution stage stops the execution operation until the execution of the next instruction after the completion of the decoding after the completion of the execution of the preceding instruction is started.

As described above, in the prior art, when the preceding command is a command for executing the write processing to the memory, confusion occurs in parallel processing that the next instruction is decoded during execution of the preceding command, resulting in a decrease in execution speed. Was done.

[Purpose of invention]

Accordingly, the present invention has been invented in view of the above-described circumstances, wherein a preceding instruction is a instruction including a write processing to a memory, and when the memory operand of the next instruction is read, parallel execution of the instruction is executed in parallel. It is an object of the present invention to provide an information processing apparatus designed to improve processing speed by reducing processing confusion.

[Configuration of Invention]

In order to achieve the above object, the present invention provides an instruction decode for decoding an instruction, a hazard detector connected to the instruction decoder to detect whether a preceding instruction preceding the instruction is a command for executing a write process to a memory, An information processing apparatus having an operand buffer connected to said instruction decoder for storing said decoded instruction, and a controller for controlling access to said memory based on information stored in said operand buffer, wherein said operand buffer is said preceding instruction. And a bit for receiving a signal indicating whether or not to execute the write processing to this memory from the command decoder and storing the signal, and for storing the signal stored in the bit and a signal indicating the end of execution of the preceding instruction. A logic operation that requires memory access to the controller It is characterized by having a logical operation device for outputting a call.

[Action]

According to the present invention configured as described above, when the next instruction requires a memory operand, the preceding instruction is executed without interrupting the decoding operation of the next instruction regardless of whether or not the preceding instruction includes a write process to the memory. .

EXAMPLE

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing a main configuration of an information processing apparatus according to an embodiment of the present invention. In the embodiment shown in FIG. 1, access to the memory relating to the next instruction is to be performed after completion of execution of the preceding instruction. An AR bit for setting information indicating whether or not the information is set is provided in the operand buffer 25, and memory access may be started in accordance with the information of this AR bit.

In FIG. 1, the same reference numerals as those of FIG. 3 perform the same functions as those of FIG. 3, and a detailed description thereof will be omitted.

In FIG. 1, the operand buffer 25 is provided with an AR bit in addition to the respective storage areas of the operand buffer 3 shown in FIG. 3. In this AR bit, a preceding instruction is written into the memory. Is set by the instruction decoder 1 when the instruction is executed, and "0" is set by the instruction decoder 1 when the preceding instruction is an instruction that does not execute the write processing to the memory. It is.

When the preceding instruction is an instruction for executing a write process to the memory, the first access request signal is " 0 ", and " 0 " is set in the A bit of the operand buffer 25 by the instruction decoder 1. do. On the other hand, when the preceding instruction is an instruction which does not execute the write processing to the memory, the first access request signal is " 1 " and the A bit of the foreign operand buffer 25 means " 1 " Is set.

The information set in the A and AR bits is logically operated by the AND gates 27 and 29 and the OR gate 31 together with the AV bit information and the termination signal indicating the end of execution of the preceding instruction. As a result, a second access request signal is generated.

That is, the AND gate 27 is applied with the information of the AR bit and the end signal to the input terminal, and the output signal is applied to one input terminal of the OR gate 31. The OR gate 31 is supplied with information of A bits to the other input terminal thereof, and its output signal is applied to one input terminal of the AND gate 29. The AND gate 29 is supplied with AV bit information at its other input terminal, and its output signal is applied to the bus controller 17 as a second access request signal.

In the above-described syntax, if the next instruction executed after the preceding instruction currently being executed is decoded by the instruction decoder 1, and the next instruction is a instruction requiring reading of the memory overland, The memory address of the memory operand obtained by the decoding of the instruction is set in the AP field from the instruction decoder 1. At the same time, " 1 " is set in the AV bit by the instruction decoder 1 to indicate the validity of the AP field.

Here, when the hazard detector 9 detects that the preceding command being executed is a command for writing to the memory, and the detection signal for that purpose is applied to the instruction decoder 1, the instruction decoder 1 is executed. "0" is set in the A bit and "1" is set in the AR bit. In this state, since the output of the OR gate 3l becomes "0" and the second access request signal which is the output of the AND gate 29 becomes "0", the memory access is not started.

Then, when the end signal becomes " 1 " and is applied to the AND gate 27 by ending the preceding instruction in execution, the output of the AND gate 27 becomes " 1 ". Accordingly, the output of the OR gate 31 also becomes "1", so that the second access request signal becomes "1". This signal is applied to the bus controller 17, and the bus controller 17 receives the signal and applies the access start signal to the memory.

Accordingly, when the memory access is started and the memory operand is read from the memory, the read memory operand is set in the DP field of the operand buffer 25 and then read out to the internal bus 23 via the buffer circuit 21. do.

On the other hand, when the hazard detector 9 detects that the preceding instruction being executed is an instruction which does not execute the writing to the memory, and the detection signal for that purpose is applied to the instruction decoder 1, the instruction decoder ( 1) sets "1" to the A bit and "0" to the AR bit.

In such a case, the output of the OR gate 31 becomes "1", and the second access request signal becomes "1" regardless of whether execution of the preceding instruction is completed or not. As a result, the reading of the memory operand is performed as described above.

In one embodiment of the present invention, regardless of whether or not the preceding command is a command for executing the write process to the memory, even if the preceding command is being executed, the instruction is decoded to perform predetermined information in the operand buffer 25. Can be set. Thus, the decoding process of the instruction decoder 1 is not interrupted during execution of the preceding instruction as shown in FIG.

Thus, confusion in parallel processing between the decoding process and the execution process does not occur. For this reason, the decoding processing of the next instruction is finished earlier than in the prior art, and therefore the execution of the instruction is quicker, and the processing speed is improved.

[Effects of the Invention]

As described above, according to the present invention, when the next instruction requires a memory operand, it can be executed without interrupting the decoding operation of the next instruction regardless of whether or not the preceding instruction includes a write process to the memory. Therefore, the confusion in the parallel processing of performing the decoding and execution processing of the instructions in parallel can be reduced, thereby improving the processing speed of the information processing apparatus.

Claims (1)

An instruction decoder (1) for decoding an instruction, a hazard detector (9) connected to the instruction decoder (1) and detecting whether a preceding instruction preceding the instruction is a command for executing a write process to a memory; Information processing having an operand buffer 25 connected to the instruction decoder 1 for storing the decoded instruction and a controller 17 for controlling access to the memory based on the information stored in the operand buffer 25. In the apparatus, the operand buffer 25 has a bit AR for receiving a signal from the instruction decoder 1 indicating whether the preceding instruction is a command for executing a write process to a memory and storing the signal. And a signal for requesting access to the memory to the controller 17 by performing a logical operation on the signal stored in the bit AR and the signal indicating the end of execution of the preceding instruction. The information processing apparatus, characterized in that with a logic unit (27,29,31) that.

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