JP2000076069A - Instruction reading and decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed and inexpensive instruction reading and decoding device. SOLUTION: This device is provided with an internal memory 101 for instruction load, an internal memory write control circuit 102 for controlling write to the internal memory 101 for instruction load, an internal memory read control circuit 103 for controlling read from the internal memory 101 for instruction load, an internal load instruction decoding circuit 104 for finding out an internal load instruction, a load address range holding circuit 105 for holding addresses decoded by the internal memory load instruction decoding circuit 104, an address comparator circuit 106 for comparing the address held by the load address range holding circuit 105 with a current address, a memory data bus switching circuit 107 for switching external memory data and data in the internal memory 101 for instruction load according to the compared result of the address comparator circuit 106, and an access timing change circuit 108 for switching access timing according to the compared result of the address comparator circuit 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for reading and decoding an instruction code.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional instruction reading and decoding apparatus. In FIG. 3, the inside of the broken line indicates the inside of the LSI. Reference numeral 301 denotes an external memory, 302 denotes an instruction decoding unit, 303
Is a program counter, and 304 is an access control unit. The 303 program counter increments the 305 program count value from the zero value each time an instruction is executed. The 304 access control unit receives the 305 program count value, and generates a 307 chip select signal and a 308 address signal for the 301 external memory. 3
01 The external memory outputs a data value corresponding to the 308 address signal as the 309 data signal when the 307 chip select signal is valid. The 302 instruction decoding unit decodes the 309 data signal and generates a 310 execution control signal. If the decoded instruction is a jump instruction, the value of the program counter is changed to the jump destination address by the 306 program counter control signal.

[0003]

However, in the above-mentioned conventional instruction execution device, instructions are sequentially read from the external memory 301 and executed. Since the access speed of the external memory is slower than the operable speed of the internal circuit, the execution speed of the instruction becomes slow depending on the access speed of the external memory. Further, incorporating a high-speed external memory or an internal memory having the same capacity as the external memory in the LSI increases the cost. In view of the above, the present invention is to solve such a problem in the conventional technology, and an object of the present invention is to provide a high-speed and low-cost instruction reading and decoding apparatus.

[0004]

In order to solve the above problems, an instruction reading and decoding apparatus according to the present invention comprises an internal memory for loading instructions and an internal memory write control circuit for controlling writing to the internal memories for loading instructions. An internal memory read control circuit for controlling reading from the internal memory for loading instructions, an internal load instruction decoding circuit for finding an internal load instruction, and a load address range for holding an address decoded by the internal memory load instruction decoding circuit. A holding circuit, an address comparison circuit that compares the current address with the address held by the load address range holding circuit,
A memory data bus switching circuit that switches between external memory data and data in the instruction loading internal memory according to the comparison result of the address comparison circuit; and an access timing change circuit that switches access timing according to the comparison result of the address comparison circuit. The instruction load into the instruction load internal memory is started by an internal load start instruction, and the instruction load into the instruction load internal memory is ended by an internal load end instruction.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, the inside of the broken line indicates the inside of the LSI. FIG. 2 shows an example of an internal load start instruction and an internal load end instruction. 11
The 0 program counter increments the 124 program count value from the zero value each time the instruction is executed. The 111 access control unit receives the 124 program count value and the 125 access timing change signal, and
It generates 113 chip select signals and 114 address signals for 9 external memories and 101 internal memories. 109
The external memory outputs a data value corresponding to the 114 address signal when the 113 chip select signal is valid to a 115 external memory data signal. 107 memory data bus switching circuit 122 when the compare match signal is valid 116
When the internal memory data signal is not valid, the external memory data signal 115 is selected, and after selecting 123, it is output to the data signal. The 112 instruction decoding unit decodes the data signal after selecting 123 to generate a 127 execution control signal. If the decoded instruction is a jump instruction, the value of the program counter is changed to the jump destination address by the 126 program counter control signal.

The 115 external memory data signal from the 109 external memory includes a 201 internal load start instruction and a 202 internal load end instruction as shown in FIG. 104
The internal load instruction decoding circuit validates the internal memory hold execution instruction signal when the external memory data signal is the internal load start instruction. The load address range holding circuit 105 transfers the address signal 114 when the internal memory holding execution command signal changes from invalid to valid.
Stored in correspondence with the block number of the internal load start instruction. The 102 internal memory write control circuit receives the next 113 chip select signal after the 121 internal memory holding execution command signal becomes valid, and converts the 114 address signal into the 117 internal memory write address and the 113 chip select signal into the 119 internal memory write signal. While the internal memory holding execution command signal is valid, the external memory data signal is written to the internal memory.

Thereafter, 115 external memory data signal is
When the 02 internal load end instruction is output, the 104 internal load instruction decoding circuit invalidates the 121 internal memory holding execution instruction signal. 105 load address range holding circuit is 12
(1) The 114 address signal when the internal memory holding execution command signal changes from valid to invalid is held again, and the 121 address signal held when the internal memory holding execution command signal changes from invalid to valid is changed to 121 internal signal. 1 when the memory retention execution command signal changes from valid to invalid
The range up to 14 address signals is output to the 106 address comparison circuit as a 128 comparison range signal. The 102 internal memory write control circuit stops the 119 internal memory write signal when the 121 internal memory hold execution command signal becomes invalid.
During the operation from the 201 internal load start instruction to the 202 internal load end instruction, the comparison between the 114 address signal and the 128 comparison range signal in the 106 address comparison circuit does not match, and the 122 comparison match signal is invalid. Therefore, the 107 memory data bus switching circuit selects the 115 external memory data, and the 127 execution control signal operates in parallel with the write operation to the 101 internal memory.

Next, when the instruction execution proceeds and the 114 address signal again matches the 128 comparison range signal due to a jump instruction or the like, the 122 comparison match signal becomes valid. At this time 1
The 08 access timing change circuit makes the 125 access timing change signal valid, makes the 113 chip select signal from the 111 access control circuit correspond to the 101 internal memory, and speeds up the read cycle. The 103 internal memory read control circuit replaces 113 chip select with 120 internal memory read signal and 114 address signal with 118 internal memory read address while the 122 comparison match signal is valid. As a result, 101 internal memory has 1 corresponding to 118 internal memory address signal.
16 outputs internal memory data. The 107 memory data bus switching circuit selects the 116 internal memory data since the 122 comparison coincidence signal is valid, and outputs the data after selecting 123. Therefore, the 112 instruction decoding unit is 101
A 127 execution control signal is generated using the data in the internal memory. As described above, the second and subsequent instructions are read from the internal load address range 203, not from the external memory 109, but from the internal memory 101. Also, by distinguishing after the block number of the 201 internal load start instruction, a plurality of blocks can be loaded into the 101 internal memory.

[0009]

As described above, according to the present invention, 1
Each time the instruction in the address range loaded into the internal memory can be read from the high-speed internal memory, there is an effect that the instruction can be executed faster than when reading from the external memory.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 shows an example of a load instruction according to the present invention;

FIG. 3 is a conventional instruction reading and decoding apparatus.

[Explanation of symbols]

 101 Internal Memory 102 Internal Memory Write Control Circuit 103 Internal Memory Read Control Circuit 104 Internal Load Instruction Decoding Circuit 105 Load Address Range Holding Circuit 106 Address Comparison Circuit 107 Memory Data Bus Switching Circuit 108 Access Timing Change Circuit 109 External Memory 110 Program Counter 111 Access Control unit 112 Command decoding unit 113 Chip select signal 114 Address signal 115 External memory data signal 116 Internal memory data signal 117 Internal memory write address 118 Internal memory read address 119 Internal memory write signal 120 Internal memory read signal 121 Internal memory holding execution command signal 122 Comparison match signal 123 Selected data signal 124 Program count value 125 Access timing change signal No. 126 Program counter control signal 127 Execution control signal 128 Comparison range signal 201 Internal load start instruction 202 Internal load end instruction 203 Internal load address range 301 External memory 302 Instruction decoding unit 303 Program counter 304 Access control unit 305 Program count value 306 Program counter Control signal 307 Chip select 308 Address signal 309 Data signal 310 Execution control signal

Claims (1)

[Claims] An internal memory for instruction loading; an internal memory write control circuit for controlling writing to the internal memory for instruction loading; an internal memory read control circuit for controlling reading from the internal memory for instruction loading; An internal load instruction decoding circuit for finding an internal load instruction; a load address range holding circuit for holding an address decoded by the internal memory load instruction decoding circuit; and an address held by the load address range holding circuit and a current address. An address comparison circuit, a memory data bus switching circuit that switches between external memory data and data in the instruction load internal memory according to the comparison result of the address comparison circuit, and an access timing that switches access timing according to the comparison result of the address comparison circuit Change circuit and For example, internally by the load start command starts the instruction load to the internal memory for the instruction load, instruction reading decryptor instructions were to terminate the loading by the internal end of the load instruction to the instruction internal memory for loading.