KR920005232B1 - Data processing unit - Google Patents

Abstract

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Description

Information processing device

1 is a diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention.

2 is a diagram showing one configuration of a conventional information processing apparatus.

* Explanation of symbols for the main parts of the drawings

1: Register group for address storage 5: Memory address register

7: Register group for data storage 9: Register for error address storage

23: control logic

Industrial use

The present invention relates to an information processing apparatus configured to store a plurality of error addresses when an error occurs during execution of a bus cycle for performing a read out of a memory operand.

[Traditional Technology and Problems]

In the information processing apparatus, in order to improve the processing speed, there is a case in which the memory operand is read out by a prefetched instruction.

FIG. 2 is a diagram showing a main part configuration for performing a read operation of a memory operand in such an information processing apparatus. The memory address corresponding to the memory operand to be read from the pseudo memory part (not shown) is addressed by a micro command. The stored memory address is stored in a register of the register group (1; AP) for storing, and the stored memory address is transferred to the memory address register (Mar: MAR) by an AP selection signal applied from the control logic (3). The address is applied to the external memory after being latched in the MAR 5 by an address latch signal applied further from the control logic 3.

Accordingly, the operand data read from the external memory unit is a data storage register group designated by the DP selection signal outputted to the second logic 3 in synchronization with the bus cycle end signal applied to the external boot control logic 3. By storing in the register (7), the reading operation of the bemorioperland data is performed.

In such a read operation, a bus cycle error may occur. This bus cycle error is one of errors that occur when the information processing apparatus accesses the external memory. An error is detected by a parity error check circuit in the external storage. This error occurs when a bus cycle error signal is output, for example, when trying to access an external storage area where access is not permitted. When this bus cycle error occurs, the information processing apparatus needs to store (retract and hold) the address causing the bus cycle error by interrupt processing and deliver it to the interrupt controller as interrupt information. The address causing the error is applied to the stack and stored.

Therefore, in the configuration shown in FIG. 2, when a bus cycle error occurs when the memory operand is read, the bus cycle error signal is applied to the control logic 3 from the outside, and an EAR selection signal synchronized with the bus cycle error signal is generated. It is applied from the control logic 3 to the error address storage register 9 to generate a bus cycle error, and the address stored in the MAR 5 is applied to the error address storage register 9 specified by the EAR selection signal. It is stored. That is, the address stored in the MAR 5 is copied to the error address storage register 9 as an error address, and the copied error address is an interrupt processing microprogram that is started by an interrupt signal output from the control logic 3. Is read from the EAR 9 and pushed onto the stack (not shown) via the internal bus 11.

In the information processing apparatus that reads the operand data as described above, the read operand data is not necessarily used but may not be used. Therefore, the interrupt signal is output until every read operand data is actually used. It doesn't work. That is, the interrupt signal is not output even if the bus cycle error occurs in the pre-reading step, and the interrupt signal is output in the step that is actually used. Can not be done.

Therefore, in the information processing apparatus shown in FIG. 2, the error address storing register 9 needs to store the same amount of addresses as the addresses stored in the address storing register group 1. That is, the error address storing register 9 needs to be composed of the same number of registers in the address storing register group 1, so that the address stored in the address storing register group 1 is increased. This causes a problem that the configuration of the error address storage register 9 is enlarged.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made in view of the above point, and an object thereof is to provide an information processing apparatus capable of evacuating and maintaining a plurality of error addresses when a bus cycle error occurs without causing a significant increase in configuration.

[Configuration of Invention]

According to an aspect of the present invention, there is provided an information processing apparatus for performing a read operation of a memory operand stored in an external storage unit, comprising: first storage means for storing and storing an address for accessing the external storage unit; Selecting means for selecting the read address of the external memory section outputted from the means and data read out from the external storage section, second storage means for holding a plurality of contents selected by the selecting means and data recorded in the external storage section, and Third storage means for storing an address read out from the second storage means or an address read out from the first storage means, and storing the stored address at the time of execution of the interrupt process, and an error in the read operation of the external storage portion. If so, the selection means can select an address output from the first storage means. In the case where an error occurs during the recording operation of the external storage unit, the third storage unit controls to hold the address output from the first storage unit, and when the address is read from the second storage unit. And three storage means having control means for controlling to hold the address.

(Action)

According to the present invention configured as described above, when an error occurs during the read operation of the external storage unit, the number of inputs and outputs of the external storage unit is normally provided in the read operation of the external storage unit using the address accessed by the external storage unit as the error address. After storing the data in the storage means for storing and storing the data, the error addresses are transferred to dedicated storage means for storing the error addresses, and the error addresses are interrupted as error information.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing the main parts of an information handling apparatus according to an embodiment of the present invention. The information processing apparatus is controlled by a microprogram method to perform read-out of operand data. In FIG. FIG. 1 shows a configuration for performing access to a part (not shown). In FIG. 1, the same reference numerals are used to designate parts having the same functions as those in FIG. 2, and detailed description thereof will be omitted.

In FIG. 1, the public information processing apparatus includes an address storing register group 1 (AP), a memory address register (MA: MAR), and a data storing register group 7 provided in the information processing apparatus shown in FIG. And a selector 21 and a control logic 23 in addition to the error address storage register 9.

The selector 21 selects an address stored in the memory address register 5 (MAR) and operand data read through the data bus 25 from an external storage unit (not shown). This selection operation is controlled. It is performed in accordance with the selection signal applied from the logic 23, and the selected address or operand data is applied to the data storage register 7 and stored therein.

The control logic 23 includes an address storing register group 1, a memory address register 5 and data according to a signal applied from a microcommand control unit (not shown) and an external circuit unit for outputting a signal relating to a bus cycle. By controlling the storage register group 1, the error address storage register 9, and the selector 21, the AP selection signal is transferred in accordance with the microcommand control signal applied from the microcommand control unit. The AP selection signal is a register group for storing an address (read address, read address) or write address (write address) of an external storage unit on the internal bus 11. This signal is selected from (1).

The control logic 23 applies an address latch signal to the memory address register 5, which transfers the address stored in the address storing register group 1 to the MAR 5, as well as the address. The signal is applied to the external memory through the bus 27.

In addition, the control logic 23 applies a DP selection signal to the data storage example gist group 7 in synchronization with the bus cycle end signal applied from the external furnace, and selects the operand data read from the external storage unit to be selected. The signal is applied to the selector 21. On the other hand, when the bus cycle error signal is applied to the control logic 23 together with the bus cycle end signal, the control logic 23 applies the selection signal to the selector 23 so that the error address held in the MAR 5 is selected.

In addition, when the error address is read from the data storage register group 7 to the internal bus 11, the control logic 23 outputs an interrupt signal to the microcommand controller to request an interrupt handler, and at the same time, an EAR (error address latch). The signal is applied to the EAR 9 so that the error address read out from the internal bus is taken into the EAR 9 to be stored. This EAR signal is a signal stored in the EAR (g) by taking in the address held in the MAR (5) when the pseudo memory section is in the recording state.

Next, the specific operation of the embodiment will be described.

First, a case in which a bus cycle error occurs during a read (read) operation of the external storage unit will be described.

When the microcommand control signal is applied from the microcommand controller to the control logic 23, the AP selection signal is applied from the control logic 23 to the address storing register group 1 so that the read address on the internal bus 11 selects the AP. It is taken in and stored in the register specified by the signal.

Next, when the address latch signal is applied from the control logic 23 to the MAR 5, the read address stored in the address storing register group 1 is transferred to the MAR 5, and the read address is maintained. A read cycle is started in which the operand data is read out from the external memory by being output from the MAR 5 and applied to the external storage through the address bus 27.

When the read cycle is finished and the bus cycle end signal 5 is applied to the control logic 23, a selection signal for selecting the operand data read from the external storage unit is applied from the control logic 23 to the selector 21. do. In addition, the DP selection signal specifying the register to store the read operand data is applied to the data storage register group 7 in synchronization with the bus cycle end signal, so that the operand data read from the external storage unit is transferred to the data bus 25 and the selector. (21) are mediated and stored in the register designated by the data storage register group (7).

On the other hand, when a bus cycle error occurs during the read operation of the external storage unit and the bus cycle error signal is applied to the control logic 23 at the same time as the bus cycle termination signal, the selection signal for selecting the address stored in the MAR 5 and the pole air address Is applied to the syntax generator 21, and the error address stored in the MAR 5 is selected by the selector 21 as the DP selection signal is applied from the control logic 23 to the data storage register group 78. And stored in the register designated by the DP selection signal.

Next, when the contents stored in the data storage register group 7 are read into the internal bus 11 by the micro instruction, the interrupt signal is transferred from the control logic 23 to the micro instruction controller if the read contents are an error address. Is read in and requires interrupt processing.

In addition, since the EAR signal is applied from the control logic 23 to the error address storage register 9, the error address read on the internal bus 11 is taken in and stored in the error address storage register 9, and the stored error. The address is read into the internal bus 11 and pushed onto the stack by an interrupt processing microprogram that is started by an interrupt signal.

Next, a case where a bus cycle error occurs during the write (write) operation of the external storage unit will be described.

First, the write address applied on the internal bus 11 is taken in and stored in the register designated by the AP selection signal in the address storing register group 1 by the execution of the micro instruction, and similarly, the write data is stored in the data storing register group ( 7) It is applied to and stored in the register designated by the DP selection signal. At the same time, the address latch signal is applied to the MAR 5 so that the write address is maintained from the address storage register group 1 to the MAR (5 / hr transfer word) and applied to the external storage through the address bus 27. A recording cycle for recording data in the storage unit is started.

When a bus cycle error occurs in this recording cycle and a bus cycle termination signal and a bus cycle era signal are applied to the control logic 23, an EAR signal is applied to the EAR 9 from the control logic 23, thereby providing a MAR (5). The recording address held in the above, that is, the error address is copied to the EAR 9 and the interrupt signal is outputted to the micro command control unit. After the interrupt signal is output, the error address stored in the EAR 9 is pushed onto the stack via the internal bus 11 as in the case of the read cycle.

When a bus cycle error occurs during the read operation of the external memory unit as described above, the error address for the bus cycle error is stored in the register storage group 7 of the natter storage and then transferred to the error address storage register 9. On the other hand, during the write operation of the external storage unit, the error address is stored directly in the error address storage register 9.

Therefore, even when a plurality of error addresses are generated as a result of the pre-read, only one dedicated register for storing the error address needs to be provided, thus making it possible to reduce the size of the error address storage register. In addition, an interrupt processing microprogram can push an error address onto a stack for one error address storage register. Therefore, the microprogram for interrupt processing can be simplified compared with the conventional multiple error address storage registers. Will be.

[Effects of the Invention]

As described above, according to the invention, the error address corresponding to an error occurring during the read operation of the external storage unit is stored once in the storage unit for storing a plurality of data normally prepared in the read operation of the external storage unit. Since the error addresses are transferred to dedicated storage means for storing the error addresses, respectively, so that interrupt processing can be performed, it is possible to save and maintain a plurality of error addresses without significantly increasing the configuration.

Claims (1)

An information processing apparatus for performing a read-out of a memory operand stored in an external storage unit, the information processing apparatus comprising: first storage means (1) for storing and storing an address for accessing the external storage unit, and outputted from the first storage means (1); Selection means 21 for selecting the read-out dress of the external storage unit and data read out from the external storage unit, and second storage for holding a plurality of contents selected by the selection unit 21 and data recorded in the external storage unit. A third memory in which the means 7 and the address read out from the second storage means 7 or the address read out from the first storage means 1 are stored, and the stored address is read out at the time of execution of the interrupt process. Control means so that the selection means 21 can select an address output from the first storage means 1 when an error occurs during the read operation of the means 9 and the external storage portion. On the other hand, when an error occurs in the recording operation of the external storage unit, the third storage means (9) controls to hold the address output from the first storage means (1) and from the second storage means (7) And control means (23) for controlling the third storage means (9) to hold the address when an address is read out.

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