JPH04124738A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by using a means which holds temporarily the trace data of small capacity and sharing a highly integrated memory between a control storage and a trace data memory. CONSTITUTION:When the microprogram control is set in a processing waiting state, a writing operation is allowed to a control storage 101 via a CSMR/W line 531. A selector 302 selects the trace data side via a selection line 512, and the trace data are written into the storage 101. When the trace data are written into the entire part of a trace data storage part 103, the writing opera tion of the storage 101 is inhibited via the line 531. Then the trace data are read out to an external device. When this processing is over, the writing opera tion of the storage 101 is inhibited again via the line 531 and the selector 302 selects the address side via the line 512. Then a program is read out of a microprogram storage part 102 and executed based on the address set to a register 201 via a line 522. Thus the storage 101 shares a trace data memory.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microprogram controller.

[Conventional technology]

Conventionally, in a microprogram control device, only the microprogram was stored in the control memory, and the trace data memory was independent.

FIG. 2 shows a block diagram of an example of a conventional microprogram control device of this type.

In FIG. 2, the control memory 121 is connected to the CSMR/W line 5.
31 all 531 write permission, and write the microprogram to the control memory 121 via the C8M write line 502.

Thereafter, writing is prohibited via the C3MR/W line 531, and the address of the control memory 101 set in the C8M address register 201 is specified via the C8M address line 522, and the microprogram is read out.

Additionally, trace memory is independent of control memory;
Writing is enabled via the trace memory R/W line 551, and trace data is written into the trace memory 111 via the trace data write line 561.

When all the trace data has been written into the trace memory 111, writing to the trace memory 111 is prohibited via the trace memory R/W line 55, and the trace data is read to an external device.

[Problem to be solved by the invention]

The conventional microprogram control device described above has a layout in which control memory and trace memory are separately prepared, which increases the amount of hardware.

[Means to solve the problem]

The microprogram control device of the present invention includes means for temporarily holding trace data for sequentially tracing and storing internal states of a data processing device, and a means for temporarily holding trace data when the microprogram control is in a processing wait state. and means for writing the trace data into the control memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

001 is a buffer memory that temporarily holds trace data for sequentially tracing and storing the internal state of the data processing device; 101 is a microprogram storage unit 10;
2 and a trace data storage unit 103, which can be written/read.

201 is a CSM address register that holds the address of the microprogram storage unit 102 in the control storage unit 101, and 202 is an ATM address register that holds the address of the trace data storage unit 103 in the control storage unit 101.

301 is a write data selector that selects whether the data to be written in the control memory 101 is a microprogram or trace data; 302 is a CSM that selects whether the address of the control memory 101 is the microprogram memory 102 or the trace data memory 103; It is an address selector.

Reference numeral 401 denotes an address counter that generates the next address when writing to or reading from the trace data storage unit 103.

501 is a buffer memory write line for writing trace data into the buffer memory 001 that temporarily holds the trace data, and 502 is a C3M write line for writing the microprogram into the microprogram storage unit 102.

503 is a buffer memory read line for writing trace data from buffer memory 001, 551 is control memory 0
The data to be written to 01 is a CSM data select line that selects either trace data or microprogram.

512 is a C9M address select line which selects whether the address of the control memory 001 is the micro brochure storage unit 102 or the trace data storage unit 103, and 521 is a buffer memory address line which indicates the address of the buffer memory 001. 522 is a CSM address line that indicates the address of the microprogram storage unit 102 in the control memory.

531 is C that instructs writing/reading of the control memory 101;
3MR/W line, 532 is ATM start address register 2
ATM start address R that instructs writing/reading of 02
/W line.

Next, an example of the operation in FIG. 1 will be shown.

The control memory 101 is enabled for writing via the C3MR/W line 531, the write data selector 301 is selected by the microprogram via the C3M data select line 511, and the microprogram is written to the control memory via the microprogram write line 502. Write the program.

At this time, the address is the C3M address select line 51
2, the CSM address selector 3゜2 is selected to the microprogram address side, and the C3M address line 522
Instructs the address of the microprogram storage unit 102 in the control storage set in the C5M address register 201.

When the microprogram has been loaded into the microprogram storage unit 102, via the C3MR/W line 531,
The control memory 101 is write-inhibited, and the write data selector 301 is selected to the trace data side via the C3M data select line 511.

The microprogram in the microprogram storage section 102 is read and executed using the address set in the C3M address register 201 via the C3M address line 522 .

At this time, the internal state of the data processing device is sequentially data traced and stored in the buffer memory 001.

Here, when the microprogram control enters the processing waiting state, the control memory 101 is enabled for writing via the C3MR/W531, and the C9M address select line 512 is
The 8M address selector 302 is set to the trace data side, and the trace data is written into the control memory 10].

Furthermore, when the trace data is written to all of the trace data storage section 1.03, the control memory 10] is made write-inhibited via the C3MR/W line 53, and the trace data is read out to an external device.

Once this process is complete, the CS M R/W 53
1, the control memory 101 is write-protected and the CSM
Through the address select line 512, select the C3M address selector 302 to the microprogram address side,
The microprogram in the microprogram storage section 102 is read and executed using the address set in the C3M address register 201 via the C3M address line 522 .

In this way, the present invention allows the control storage to share the trace memory.

〔Effect of the invention〕

As explained above, the present invention uses a means for temporarily holding trace data of gait amount, and also shares the write/read circuit by using a highly integrated memory as a control memory and a memory for trace data. The amount can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a block diagram showing a conventional example. 001... Buffer memory, 101... Control memory,
102...Microprogram storage unit, 103...
Trace data storage unit, 201...C3M address register, 202...ATM address register, 3゜1
. . . Write data selector, 302 . . . Address selector, 401 . . . Address counter.

Claims (1)

[Claims] Means for temporarily holding trace data for sequentially tracing and storing the internal state of a data processing device; and means for temporarily holding the trace data when the microprogram control is in a processing wait state. , means for writing the trace data into the control memory, and storing the trace data and the microprogram in the control memory.