JPH03256127A - Microprocessor system - Google Patents

Abstract

PURPOSE:To use a slow ROM as a program ROM and to improve the performance of a system by providing this system with a direct memory access (DMA) mechanism, and at the time of resetting the system, writing the program of the ROM in a high-speed RAM. CONSTITUTION:When a system reset signal is applied, a microrpocessor (MP) 1 is held at a reset state, and when a reset signal is released, the program stored in the slow program ROM 4 is written in the high-speed program RAM 3 while holding the MP 1 at the reset state as it is. After ending the writing operation, the reset state of the MP 1 is released and the DAM mechanism 2 is disconnected from the MP 1. After releasing the reset state, the MP 1 fetches the program stored in the RAM 3 and rises. Since the slow-speed ROM with low cost and large capacity can be used as the program ROM, the system of high performance can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ROM-embedded microprocessor system.

[Prior Art] There has been remarkable progress in microprocessor systems in recent years, and ROM-embedded computer systems that store several megabytes or more of programs in ROM are not uncommon.

In addition, operating clocks have become much faster, and as a result, response times for access requests to memories and the like have become shorter.

On the other hand, EFRO is easy to erase and rewrite memory contents.
M has become the mainstream of current embedded program memory due to the increase in capacity per chip and faster response time, but faster access response time has led to faster microprocessor operating clocks. It is slower compared to other machines, and the difference in performance is only widening.

Note that it is possible to interface with a low-speed memory by inserting a wait cycle (wait time) into the access cycle of the microprocessor, and this is a method that is often used in practice.

However, the insertion of wait cycles has the disadvantage that the arithmetic processing performance of the microprocessor is significantly reduced, making it impossible to achieve its original performance.

Therefore, improvements are currently being made using the following three methods.

The first method is program copying using software. That is, immediately after the system reset is released, the microprocessor fetches the program from the low-speed ROM and starts up. The program is roughly divided into two blocks: one is called the boot rotor, and the other is the original arithmetic processing section. Immediately after the system reset is released, the microprocessor executes the contents of the bootloader. The bootloader copies the program of the original arithmetic processing unit to the high-speed RAM, and when the copy is completed, the program is transferred to the RA.
Contains an instruction to transfer execution to a program on M.

Although the first method has the advantage of simplifying the hardware configuration, it increases the difficulty of software development and debugging. Moreover, it is necessary to allocate two original programs in the address space, which is disadvantageous in terms of increasing the program capacity.

The second method is to use a high-speed FROM, such as bipolar, as the program ROM.

However, high-speed ROM such as bipolar has a smaller capacity per chip than the mainstream EPROM.
The number of memory cells required is several times that of the case where EPROMs are used. Furthermore, due to the characteristic of the device itself that once a program is written, it cannot be erased again, and a large amount of FROM must be discarded when debugging software.

The third method is a small capacity high-speed R called cache memory.
This is an approach that uses AM with a very complex control mechanism.

However, this method requires a complicated hardware configuration, and depending on how the program is created, the cache hit rate may decrease. Furthermore, no effect can be expected on commands such as long jumps, calls, and task switching.

[Problems to be solved by the invention] Conventionally, due to the above-mentioned problems, the difficulty of software development and debugging has increased, it has been disadvantageous in terms of increasing the capacity of programs, and high-speed FRs such as bipolar
It required a large amount of OM to be discarded and was complicated, such as a cache memory, so there was some concern about its effectiveness.

The present invention was made in view of the above-mentioned circumstances, and allows an inexpensive, large-capacity, low-speed ROM to be used as a program ROM.
Software development - debugging is not difficult,
The purpose of the present invention is to provide a high-performance microprocessor system that is not disadvantageous in terms of increasing program capacity.

[Means for Solving the Problems] The present invention provides a ROM-embedded microprocessor system in which the microprocessor is put into a reset state when the system is reset, and programs in the ROM are transferred to high-speed RA.
Equipped with a direct memory access mechanism to write to M,
After writing the program to the high-speed RAM, the microprocessor fetches the program stored in the high-speed RAM and starts up.

[Operation] When the DMA mechanism is given a system reset signal,
The microprocessor side is held in the reset state, and when the reset signal is released, the program stored in the ROM is transferred to the high-speed RAM while the microprocessor is held in the reset state.
After writing is completed, the reset of the microprocessor is canceled and the DM is sent from the microprocessor.
Disconnect mechanism A. When the microprocessor is released from reset, it fetches the program stored in the high-speed RAM and starts up.

[Example code] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a microprocessor system according to the present invention. Note that, in order to clarify the features of the present invention, detailed control signals and the like around the microprocessor are omitted from the figure.

In Figure 1, 1 is a microprocessor, 2 is a DMA
(direct memory access) mechanism, 3 is a high-speed program RAM, 4 is a low-speed program RAM, 5 is an address bus, 6 is a data bus, 7 is a microprocessor.
8 is a data bus buffer of the microprocessor, 9 is an address buffer of the DMA mechanism 2, and 10 is a data bus buffer of the DMA mechanism 2.

A microprocessor 1 is in charge of controlling the entire system, and is connected to an address bus 5 and a data bus 6 via an address buffer 7 and a bidirectional data bus buffer 8.

The DMA mechanism 2 directly writes the high-speed program RAM 3 and the low-speed program R without going through the microprocessor 1.
Accessing OM4, system reset manually 1
1 and a microprocessor reset output 12. The system reset human power 11 of the DM A tJ & system 2 is given a system reset signal by, for example, operating a system reset switch sw. Also,
The microprocessor reset output 12 is connected to the reset input 13 of the microprocessor 1 and to the output enable terminals 14 of the address buffer 7 and data bus buffer 8. Furthermore, the microprocessor reset output 12 is connected to the output enable section terminal 14 of the address buffer 9 and the data bus buffer 10 via an inverter 15. The DMA mechanism 2 starts operating when the reset signal is released, and outputs address data to the address bus 5 via the address buffer 9.

The high-speed program l'tAM3 is directly connected to the address bus 5 and data bus 6, and is connected to the D
Low-speed program ROM accessed by MA mechanism 2
4 is loaded and thereafter accessed by microprocessor 1.

The low speed program ROM 4 is connected directly to the address bus 5 and also to the data bus 6 via the read data bus buffer 10 of the DMA mechanism 2 . This low-speed program ROM 4 stores a system program in advance, and is accessed by the DMA mechanism 2 only when the system is reset.

The operation of the above embodiment will be explained below.

When the DMA mechanism 2 receives a reset signal from the system reset manual 11 at the time of system startup, etc.,
A reset signal is output to the microprocessor reset output 12. The reset signal output from the DMA mechanism 2 holds the microprocessor in a reset state, and also holds the address buffer 7 and data bus buffer 8 of the microprocessor in a reset state.

At the same time, the reset signal output from the DMA mechanism 2 is inverted by the inverter 5 and input to the address buffer 9 of the t-DMA mechanism 2 and the output enable terminal 14 of the data bus buffer 10. As a result, I
) The address buffer 9 and data bus buffer 10 of the MA mechanism 2 become output enabled.

Next, when the reset signal to the system reset input 11 of the DMA mechanism 2 is released, the DMA mechanism 2 starts operating. At this time, the DMA mechanism 2 maintains the state in which the reset signal is output from the microprocessor reset output 12. Therefore, the microprocessor stops operating, its address buffer 7 and its data bus buffer 8 are output disabled, and the address buffer 9 and data bus buffer 10 of the DMA mechanism 2 are output enabled.

In this state, the DMA mechanism 2 transfers the address to the address bus 5.
The program stored in the low-speed program ROM 4 is read out and written to the same address in the high-speed program RAM 3. Thereafter, in the same manner, the DMA mechanism 2 sequentially reads out the stored contents of the low-speed program ROM 4 while updating the addresses, and writes them into the high-speed program RAM 3.

When the DMA mechanism 2 finishes writing all the stored contents of the low-speed program ROM 4 to the high-speed program RAM 3, the DMA mechanism 2 releases the reset signal of the microprocessor reset output 12.

As a result, address buffer 7 of microprocessor 1
and data bus buffer 8 are enabled for output, address buffer 9 and data bus buffer 10 of DMA mechanism 2 are disabled for output, and DMA mechanism 2 and low-speed program ROM are output from the microprocessor 1 side.
4 is cut and 0 is separated.

When the reset signal is released, the microprocessor 1 fetches the program stored in the high-speed program RAM 3 without a wait, starts up, and executes the program without a wait.

[Effects of the Invention] As described above, according to the present invention, an inexpensive, large-capacity, low-speed ROM can be used as a program ROM. Furthermore, by performing program fetches without waiting, the arithmetic processing performance of the microprocessor can be maximized, and the difficulty of software development and debugging does not increase, making it possible to increase the capacity of programs. It is possible to realize a high-performance system that is not disadvantageous in terms of.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a microprocessor system according to an embodiment of the present invention. 1... Microprocessor, 2... DMA mechanism, 3
1...High-speed program RAM, 4...Low-speed program ROM, 5...Address bus, 6...Data bus,
7...Address buffer, 8...Data bus buffer, 9...Address buffer, 10...Data bus buffer, 11...System reset input, 12...
- Microprocessor reset output, 13... Microprocessor reset input, 14... Output enable section terminal.

Claims (1)

[Claims] In a ROM-embedded microprocessor system,
A microprocessor system comprising a direct memory access mechanism that puts the microprocessor into a reset state at the time of system reset and writes a program in a ROM to a high-speed RAM.