JP2007264978A - Information processor and method for starting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the quick and smooth start of an information processor in which a program from a non-volatile memory to a volatile memory is transferred at startup, and a CPU executes the program on the volatile memory. <P>SOLUTION: A method for starting an information processor is provided to store the reset of a CPU 33 at startup of an ASIC 30, and to start the transfer of F/W or the like from a serial ROM 21 to an RAM 23 by hardware (DMA controller 34, F/W copy controller 35, bus controller 36, serial ROM controller 31, RAM controller 32) other than the CPU 33, and to release the reset of the CPU 33 in a preliminarily designated start timing(the transfer end timing of a boot loader) during the transfer. After the reset release of the CPU 33, initialization processing by the CPU 33 and the transfer of the F/W or the like are executed in parallel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus in which a CPU executes processing according to a program transferred from a nonvolatile memory to a volatile memory, and a startup method thereof.

  Conventionally, firmware (F / W), which is a program for controlling devices, is stored in a small (low pin count) and inexpensive serial ROM, and the data (F / W) on this serial ROM is stored when the power is turned on. W, etc.) is transferred to a RAM that can be accessed at high speed, and an information processing apparatus configured such that a CPU executes a program on the RAM is known.

  In this type of information processing apparatus, in general, since the reset of the CPU is released after the data transfer from the serial ROM to the RAM is completed, the startup of the CPU and the rise time of the apparatus (request from the outside after power-on) There was a problem that it took a long time to accept.

  On the other hand, when power is turned on, data transfer from the serial ROM to the RAM is started, and the reset of the CPU is also released. An apparatus that generates a signal and stops the operation of a CPU is disclosed (for example, see Patent Document 1).

In this device, it is also disclosed that a part of the data in the ROM is transferred to the RAM by hardware, and the remaining data in the ROM is transferred by the CPU.
Japanese Patent Laid-Open No. 2005-10942

  However, in the former method for generating the wait signal, the CPU operation is irregularly repeated after the power is turned on until the data transfer from the serial ROM to the RAM is completed. There was a problem that it may appear as if it were unstable.

  For example, if the program is executed during the transfer of a program that displays a plurality of characters on the display unit, if a wait occurs during the display, it will appear as if the device is frozen.

Further, the latter method using the data transfer by the CPU has a problem that it takes longer time than the transfer by the hardware, and the rise time of the apparatus is prolonged.
In order to solve the above problems, the present invention provides an information processing apparatus in which a program is transferred from a non-volatile memory to a volatile memory at startup and the CPU executes the program on the volatile memory. The purpose is to make it possible to stand up.

  In order to achieve the above-mentioned object, the invention according to claim 1 is the information that the CPU executes processing according to the program transferred from the first storage means consisting of the non-volatile memory to the second storage means consisting of the volatile memory. A method of starting a processing apparatus, wherein the CPU reset is held when the information processing apparatus is started, and the transfer of the program is started by hardware other than the CPU, and is designated in advance during the program transfer The reset of the CPU is released at the release timing, and after the reset of the CPU is released, a predetermined initialization process by the CPU and the transfer of the program are executed in parallel.

  That is, according to the activation method of the present invention, when a program for executing the minimum necessary processing (initialization processing) that is immediately required by the CPU is transferred, the CPU does not wait for the completion of the transfer of all the programs. Since the reset is released, the rise time of the device can be greatly shortened, and since the program transfer is continued in parallel with the CPU processing, the program transfer is also performed in the minimum necessary time. be able to.

  Next, the invention according to claim 2 is directed to a first storage unit comprising a nonvolatile memory for storing a program, a second storage unit comprising a volatile memory, and the program stored in the first storage unit. A transfer means for transferring to the second storage means; a CPU for executing processing in accordance with a program stored in the second storage means by the transfer means; and holding the reset of the CPU when the apparatus is activated, and the transfer means Reset control means for releasing the reset of the CPU at a release timing specified in advance during the program transfer by the CPU, and after the reset release of the CPU by the reset control means, a predetermined initialization process by the CPU and the transfer An information processing apparatus characterized in that program transfer by means is executed in parallel.

That is, the present invention is an apparatus for realizing the method according to claim 1, and can obtain the same effect as that of claim 1.
By the way, as described in claim 3, the first storage means stores start timing information indicating the release timing, and the reset release means is released by monitoring the transfer amount of data transferred by the transfer means. You may comprise so that timing may be judged.

In this case, the activation timing of the CPU can be easily changed simply by changing the activation timing information indicating the release timing stored in the first storage means.
The data transfer amount may be monitored by any of the transfer source address, the transfer destination address, and the number of transfer bytes.

  Further, as described in claim 4, the program is divided into a designated program for executing a designated process designated in advance and a non-designated program other than the designated program to indicate the end of transfer of the designated program. It is desirable to set the address as the release timing.

  In this case, the designation process can be executed on the RAM immediately after the CPU is started, and in the middle of the designation process, unlike the conventional apparatus, no weight is generated. The device can be started up smoothly.

  And when the interface means which consists of at least one among the external device I / F which inputs / outputs data with the user I / F which accepts the operation from the outside or the external device as described in claim 5 is provided The designation process preferably includes at least a process for initializing the interface unit to a usable state.

  According to the information processing apparatus of the present invention configured as described above, it is possible to accept an external request via the interface means in a necessary minimum time after the apparatus is activated.

  Furthermore, as described in claim 6, the CPU detects whether or not the program corresponding to the request accepted by the interface means has been transferred to the second storage means, and the program to be started is not transferred. In some cases, it may be configured to wait until the transfer of the program is completed.

  According to the information processing apparatus of the present invention configured as described above, the waiting time until the requested processing is started because the transferred program is started immediately without waiting for the transfer of all programs. Can be minimized.

In the case where the display means for performing various displays is provided, it is desirable that the designation process includes at least a process for performing display control of the display means.
According to the information processing apparatus of the present invention configured as described above, it is possible to prevent the display on the display unit from being frozen when the apparatus is started up, and to quickly change the operation state of the apparatus. And it can display smoothly.

In addition, as specified in claim 8, it is desirable that the designation process includes at least a process for detecting an error in each part of the apparatus.
According to the information processing apparatus of the present invention configured as described above, it is possible to quickly detect the presence or absence of an error when the apparatus is started up.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an image forming apparatus 1 to which the present invention is applied.
The image forming apparatus 1 according to the present embodiment is configured as a so-called multi-function machine having functions as a printer, a scanner, a copier, and a FAX.
[Entire configuration of image forming apparatus]
As shown in FIG. 1, an image forming apparatus 1 includes an image forming unit 3 that prints image information on a print medium such as paper, an image reading unit 5 that reads image information recorded on a document, and a general public line. Communication interface (I / F) 7 for communicating image information, cursor keys and switches for inputting various settings and commands, menu screens showing various menu items, contents input by users and errors Input / output of image data to and from an operation panel 9 including a liquid crystal panel for display, an external memory card I / F 11 including a card slot for mounting various storage media, and an external personal computer via a parallel cable Parallel I / F 13 consisting of a connector for performing an operation and an external personal computer or digital camera via a USB cable And an external device comprising a connector for inputting and outputting image data USB I / F15 in.

In addition, since the structure of these each part is a well-known thing, description is abbreviate | omitted for the detail.
The communication I / F 7, the input configuration of the operation panel 9, the external memory card I / F 11, the parallel I / F, and the USB I / F 15 are examples of interface means that constitute the present invention. Is an example of the display means constituting the present invention.

  Here, the image forming apparatus 1 is configured according to commands and settings input via the operation panel 9 (image forming unit 3, image reading unit 5, communication I / F 7, external memory card I / F 11, parallel I / F). / F13, USB I / F15), a control unit 20 that realizes functions as a printer, a scanner, a copier, and a FAX, and a power supply unit 40 that supplies power to each unit including the control unit 20 I'm getting ready.

  Then, the control unit 20 includes firmware (F / W) that is a program for controlling the operation of each unit of the apparatus, various settings necessary for execution of the program, initial values, and the like (hereinafter collectively referred to as “F / W”). The serial ROM 21 (an example of the first storage means) in which the F / W and the like on the serial ROM 21 are copied and the RAM 23 (second storage) that stores temporary data generated in various processes. An example) and an I / O control unit that controls input / output of various signals between each unit 3 to 15, a memory control unit that controls input / output of ROM 21 and RAM 23, and startup control that controls startup of the device ASIC (Application Specific Integrated Circuit) 30 including a CPU and a CPU for executing various programs.

  The serial ROM 21 is a well-known nonvolatile memory that serially outputs data, and the RAM 23 is a well-known volatile memory that can randomly access data.

  The power supply unit 40 receives a power supply from a commercial power supply (AC 100 V), and mainly uses a high voltage power source DH (5 V in the present embodiment) for power supply to a drive system such as a motor or an actuator, and the control unit 20. A low-voltage power supply DL (3.3 V in this embodiment) used for power supply to the control system is generated.

Furthermore, the power supply unit 40 monitors the power supply voltage of the low-voltage power supply DL, and when the power supply voltage rises above a predetermined value, the power supply unit 40 becomes H (high) after a stable time required for the power supply and circuit operation to stabilize. ) IC reset signal RST_N that becomes L (low) level / reset holding when the level / reset is canceled and the power supply voltage falls below a predetermined value (where the symbol “_N” represents negative logic. The same applies hereinafter.) Is supplied to the ASIC 30.
[Contents of serial ROM]
Here, FIG. 2A is an explanatory diagram showing an outline of the contents stored in the serial ROM 21, and FIG. 2B is a state where the F / W or the like has been transferred (copied) to the RAM 23, and an outline of the transferred contents. It is explanatory drawing shown.

  As shown in FIG. 2A, the serial ROM 21 stores information necessary for data transfer to the RAM 23, a header area in which CPU startup timing information is stored, an F / W to be transferred to the RAM 23, and the like. Data area.

  Among these, F / W, etc. stored in the data area uses a boot loader consisting of a program group necessary for starting up the apparatus 1, a program related to printing using the image forming unit 3, the image reading unit 5, etc. And a group of application programs executed in response to an external request, such as a program related to the scanner and a program related to FAX using the communication I / F 7 (see FIG. 2B).

  The boot loader includes initialization of functions such as the image forming unit 3 and the image reading unit 5, user I / F (operation panel 9 and the like), PCI / F (parallel I / F 13 and USB I / F 15), communication I / F. At least F7, control of the external memory card I / F, and program management (OS) are included.

  On the other hand, in the header area, as shown in FIG. 2A, the transfer data size (4 bytes) indicating the data size such as F / W stored in the data area, and the reset release timing of the CPU 35 described later are activated. The timing (4 bytes) is stored.

The serial ROM 21 stores the transfer data size, the start timing, and the F / W main body in that order from the top address.
In the present embodiment, the start address of the application program group stored in the serial ROM 21 is set as the start timing. That is, the boot loader is an example of a designated program, and the application program group is an example of a non-designated program.
[Configuration of main parts]
Next, FIG. 3 is a block diagram showing a configuration related to the main part of the present invention, specifically, a configuration related to the CPU and memory control and start-up control in the ASIC 30.

  As shown in FIG. 3, the ASIC 30 controls a CPU 33 that executes processing according to a program, a serial ROM controller 31 that controls reading (reading) of data from the serial ROM 21, and data read / write (read / write) with respect to the RAM 23. A RAM controller 32 for controlling data transfer (so-called DMA transfer) not via the CPU 33, and an F / W for controlling data transfer from the serial ROM 21 to the RAM 23 using the DMA controller 34 when the ASIC 30 is activated. A copy controller 35 (an example of transfer means together with the DMA controller 34), a serial ROM controller 31 (and serial ROM 21), a RAM controller 32 (and RAM 23), and other peripheral circuits A bus controller 36 that controls the buses (data bus, address bus, control signal line) B connected to each other, and a reset controller 37 (an example of a reset control means) that controls a reset for each part in the ASIC 30 described above. ing.

  The CPU 33, the DMA controller 34, and the F / W copy controller 35 are connected to the bus B via the bus controller 36. The bus controller 36 is configured to arbitrate access requests to various memories and peripheral devices connected to the bus B from the CPU 33, the DMA controller 34, and the F / W copy controller 35.

  Also, the F / W copy controller 35, the DMA controller 34, the bus controller 36, and the reset controller 37 are all configured as a sequencer that executes processing of a predetermined procedure in response to an input signal. Is realized.

Hereinafter, the procedure of processing executed by the reset controller 37, the F / W copy controller 35, and the DMA controller 34 will be described in detail with reference to the flowcharts shown in FIGS.
[Reset Controller Processing Procedure]
First, in accordance with the IC reset signal RST_N from the power supply unit 40 and the CPU reset release request CRST_CR from the DMA controller 34, the reset controller 37 activates the CPU reset signal CRST_N that controls the start and stop of the CPU 31 and the activation of each unit other than the CPU 35. The other part reset signal ARST_N for controlling the stop is generated (see FIG. 3).

  The reset controller 37 is configured such that when power supply to the ASIC 30 is started, the CPU reset signal CRST_N and the other-part reset signal ARST_N, which are outputs thereof, are both at the L level, that is, the reset hold. As a result, the entire ASIC 30 immediately after the power is turned on is held in the reset state.

  After that, when the IC reset signal RST_N from the power supply unit 40 becomes H level and the reset is released, the reset controller 37 is activated and, as shown in FIG. The signal ARST_N is set to H level, and the reset of each part other than the CPU 35 is released (S110).

Then, it waits until the CPU reset release request CRST_CR from the DMA controller 34 becomes H level, that is, there is a request (S120). When the CPU reset release request CRST_CR becomes H level, the CPU reset signal CRST_N is set to H level, that is, By canceling the reset, the CPU 35 is activated (S130), and the series of processes is terminated.
[Processing procedure of F / W copy controller]
Next, the F / W copy controller 35 starts when the other-part reset signal ARST_N from the reset controller 37 becomes H level and the reset is released.

  Then, as shown in FIG. 5, first, the header read start request HDR_S is set to the H level, the bus controller 36 is requested to read the header area of the serial ROM 21 (S210), and the header read from the bus controller 36 is completed. It waits until the notification HDR_E becomes H level (S220).

  At this time, the bus controller 36 outputs a signal for reading the header area (that is, the first 8 bytes) from the serial ROM 21 to the serial ROM controller 31, and the header area data read from the serial ROM 21 is output. While supplying to the F / W copy controller 35, the header reading end notification HDR_E is set to the H level to notify the F / W copy controller 35 of the reading end.

  When the header read end notification HDR_E becomes H level, the F / W copy controller 35 reads the header area data supplied from the bus controller 36 and sets the header read start request HDR_S to L level to cancel the request ( S230).

  At this time, in response to the L level of the header read start request HDR_S, the bus controller 36 ends the supply of the header area data to the F / W copy controller 35 and sets the header read end notification HDR_E to the L level.

  Next, the F / W copy controller 35 sets the DMA controller 34 based on the read header area data (transfer data size, activation timing) (S240).

  Specifically, the start address of the data area in which the serial ROM 21 F / W, etc. is stored is set as the start address of the transfer source address, and the start address of the RAM 23 is set as the start address of the transfer destination address. The data in the serial ROM 21 is set to be transferred to the RAM 23. At the same time, the activation timing read in S240 is set as monitoring information. These settings are performed using a setting command for the DMA controller 34.

  Next, the F / W copy controller 35 sets the copy start request CPY_S to H level to request the DMA controller 34 to start data transfer (S250), and the copy end notification CPY_E from the DMA controller 34 is H level. It waits until it becomes (S260).

When the copy end notification CPY_E becomes H level, the request is canceled by setting the copy start request CPY_S to L level (S270), and a series of processing ends.
[Processing procedure of DMA controller]
When the monitoring information (start timing) is set in addition to a known configuration for performing DMA transfer according to the setting contents set by the setting command, the DMA controller 34 sets the transfer source address of the DMA transfer to the monitoring information, that is, the start When the timing coincides, a monitoring circuit is provided that outputs a CPU reset release request CRST_CR (outputs an H level for a certain period) to the reset controller 37.

  Specifically, the DMA controller 34 is activated when the other-part reset signal ARST_N from the reset controller 37 becomes H level and the reset is released, and the copy from the F / W copy controller 35 is performed as shown in FIG. Wait until the start request CPY_S becomes H level (S310).

However, after the DMA controller 34 is activated, the DMA transfer can be set by appropriately receiving a setting command separately from this processing procedure.
When the copy start request CPY_S becomes H level, DMA transfer, here, F / W main body transfer from the serial ROM 21 to the RAM 23 is started according to the setting information set by the setting command (S320), and the transfer source address Is monitored until the transfer source address matches the activation timing (monitoring information) set by the F / W copy controller 35 (S330).

  When the transfer source address coincides with the start timing, the CPU reset release request CRST_CR is set to H level to request the reset controller 37 to release the reset of the CPU 33 (S340), and the number of data transfers by the DMA controller 34 is The process waits until it matches the transfer data size set by the F / W copy controller 35, that is, until the DMA transfer is completed (S350).

When the DMA transfer ends, the copy end notification CPY_E is set to the H level to notify the F / W copy controller 35 of the end of the copy. In response to this, when the copy start request CPY_S becomes the L level, the copy ends. The notification CPY_E is also set to the L level (S360), and the series of processing ends.
[Operation of main part]
Here, FIG. 7 is a timing chart showing the operation timing of each part of the ASIC 30.

  As shown in FIG. 7, in the ASIC 30, when the IC reset signal RST_N becomes H level, the reset controller 37 is activated (time T0). Then, the activated reset controller 37 sets the other-part reset signal ARST_N to the H level, and the part other than the CPU 33 of the ASIC 30 is activated (time T1).

  Thus, the activated F / W copy controller 35 sets the header read start request HDR_S to the H level, thereby requesting the bus controller 36 to read the data in the header area of the serial ROM 21. Then, when the reading of the data in the header area from the serial ROM 21 is completed, the bus controller 36 notifies the F / W copy controller 35 to that effect by setting the header reading end notification HDR_E to the H level (time T2).

  In response to this header read end notification HDR_E, the F / W copy controller 35 fetches the header area data supplied from the bus controller 36 and sets the header read start request HDR_S to L level to cancel the request (time). T3). In response to this header read start request HDR_S, the bus controller 36 returns the header read end notification HDR_E to the L level.

  Further, the F / W copy controller 35 that has fetched the header area data sets the DMA controller 34 in accordance with the header area data (transfer data size, activation timing), and then sets the copy start request CPY_S to the H level. Thus, the DMA controller 34 is requested to copy (data transfer) such as F / W from the serial ROM 21 to the RAM 23 (time T4).

  In response to the copy start request CPY_S, the DMA controller 34 that has started data transfer monitors the transfer source address. When the transfer source address matches the start timing, the DMA reset 34 issues a CPU reset release request CRST_CR for a certain period. The reset controller 37 is requested to cancel the reset of the CPU 33 (that is, start) (time T5).

  In response to the CPU reset cancellation request CRST_CR, the reset controller 37 activates the CPU 33 by setting the CPU reset signal CRST_N to the H level (time T6). The activated CPU 33 starts executing an initialization process described later.

  That is, from time T4 to T6, only copying such as F / W from the serial ROM 21 to the RAM 23 by the DMA controller 34 is executed, and from time T6, F is executed in parallel with the initialization processing of the CPU 33 being executed. Copying such as / W is continuously executed.

  Thereafter, when the data transfer of the set amount (transfer data size) is completed, the DMA controller 34 sets the copy end notification CPY_E to the H level to notify the F / W copy controller 35 of this (time T7). ).

In response to this copy end notification CPY_E, the F / W copy controller 35 sets the copy start request CPY_S to L level to cancel the request (time T8). In response to this, the DMA controller 34 copies End notification CPY_E is set to L level.
[CPU initialization processing]
Here, the initialization process executed immediately after the CPU 33 activated at time T6 will be described with reference to the flowchart shown in FIG.

At the time when this process is started, the RAM 23 is in a state where a copy of the boot loader is stored.
As shown in FIG. 8, when this process is activated, initial settings are made to enable the respective units 3 to 15 to operate (S410), and each I so that requests and data from the outside can be received. / F7, 11, 13, and 15 are activated (S420).

Note that since all programs for executing these processes are included in the boot loader, these processes are executed smoothly without being interrupted.
Next, the transfer status such as F / W is acquired from the DMA controller 34 (S430), and it is determined whether or not all data has been transferred (S440). In S430, the progress status of the transfer is stored so that it can be grasped which application program has been transferred (that is, in an executable state) each time.

  If all the data has not been transferred, it is determined whether any request has occurred via each I / F 7, 11, 13, 15 or operation panel 9 activated in S420 (S450). ), If no request is generated (S450: NO), the process returns to S430.

  On the other hand, if a request has occurred (S450: YES), it is determined whether or not the application program corresponding to the generated request has been transferred (S460). If it has been transferred, the application program is started. (S480), the process returns to S440.

  If the application program corresponding to the generated request has not been transferred (S460: NO), the transfer status such as F / W is acquired from the DMA controller 34 (S470), as in S430, and the process proceeds to S460. By returning, it waits until the corresponding application program has been transferred.

If it is determined in S440 that all data has been transferred (S440: YES), the request is input according to each I / F 7, 11, 13, 15 or a request input via the operation panel 9. The normal IDLE control for starting the application program in response to the request is started (S490), and this process ends.
[effect]
As described above, the image forming apparatus 1 holds the reset of the CPU 33 when the ASIC 30 is activated, and the hardware other than the CPU 33 (DMA controller 34, F / W copy controller 35, bus controller 36, serial ROM). The controller 31 and the RAM controller 32) start the transfer of F / W or the like from the serial ROM 21 to the RAM 23, and cancel the reset of the CPU 33 at a pre-specified start timing (boot loader transfer end timing) during the transfer, After the reset of the CPU 33, the initialization process by the CPU 33 and the transfer such as F / W are executed in parallel. Note that the boot loader includes a group of programs necessary to start up the apparatus until it can accept external requests and data.

  Therefore, according to the image forming apparatus 1, since the reset of the CPU 33 is released without waiting until the transfer of F / W or the like is completed, the rise time of the apparatus can be greatly shortened. Since the program transfer is continued in parallel with the initialization process, the program can be transferred in the minimum necessary time.

  In addition, when the CPU 33 is activated, all the programs necessary for starting up the device are all transferred to the RAM 23. Therefore, the processing of the CPU 33 is not interrupted during the start-up process, and the device can be smoothly operated. Can be launched.

  Further, according to the image forming apparatus 1, since the reset of the CPU 33 is released in accordance with the start timing stored in the serial ROM 21, the start timing of the CPU 33 can be easily changed simply by rewriting the start timing. be able to.

  In the image forming apparatus 1, after the CPU 33 can accept requests and data from the respective I / Fs 7, 11, 13, 15 and the operation panel 9, application programs corresponding to the requests accepted by these are displayed. If the application program has already been transferred to the RAM 23, the application program is immediately started. If the application program has not been transferred yet, the application program waits until the transfer of the application program is completed.

Therefore, according to the image forming apparatus 1, the waiting time until the process (application program) corresponding to the received request is started can be minimized.
[Other Embodiments]
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.

  For example, in the above-described embodiment, a group of programs for performing initialization of various functions, control of various I / Fs, and program management is used as a boot loader. However, a program group for detecting an error in each part of the apparatus may be included. In this case, the presence or absence of an error can be promptly detected when the apparatus is started up.

In the above embodiment, the activation timing is specified by the transfer source address, but may be specified by the transfer destination address or the data transfer amount.
When the activation timing is specified by the transfer destination address, as shown in FIG. 9A, the DMA controller 34 sets the transfer destination address to which the DMA controller 34 is currently transferring, in S330, as shown in FIG. What is necessary is just to comprise so that the starting timing set by the copy controller 35 may be compared.

  When the activation timing is specified by the data transfer amount (the data size of the boot loader), the DMA controller 34 sets the data transfer amount by the DMA controller 34 to F / W in S330 as shown in FIG. 9B. What is necessary is just to comprise so that the starting timing set by the copy controller 35 may be compared.

  When the activation timing is specified by the transfer source address or the transfer destination address, the activation timing is not limited to the start address of the application program group, and the end address of the boot loader may be used.

1 is a block diagram illustrating an overall configuration of an image forming apparatus. Explanatory drawing which shows the structure of the data stored in serial ROM, and the state of RAM after transferring F / W etc. FIG. The block diagram which shows the structure of ASIC (main part of invention). The flowchart which shows the content of a series of processes which a reset controller performs. 6 is a flowchart showing the contents of a series of processes executed by the F / W copy controller. The flowchart which shows the content of a series of processes which a DMA controller performs. The timing diagram which shows the operation | movement at the time of starting of each ASIC part. The flowchart which shows the content of the process which CPU performs at the time of starting. The flowchart which shows the modification of a series of processes which a DMA controller performs.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 3 ... Image forming part, 5 ... Image reading part, 7 ... Communication I / F, 9 ... Operation panel, 11 ... External memory card I / F, 13 ... Parallel I / F, 15 ... USB I / F, 20 ... control unit, 21 ... serial ROM, 23 ... RAM, 30 ... ASIC, 31 ... serial ROM controller, 32 ... RAM controller, 33 ... CPU, 34 ... DMA controller, 35 ... F / W copy controller, 36 ... Bus controller 37 ... Reset controller 40 ... Power supply unit B ... Bus

Claims (8)

A method of starting an information processing apparatus in which a CPU executes processing according to a program transferred from a first storage unit made of a nonvolatile memory to a second storage unit made of a volatile memory,
Holding the reset of the CPU at the time of starting the information processing apparatus, by using hardware other than the CPU, to start the transfer of the program,
The reset of the CPU is released at a release timing specified in advance during the program transfer, and after the reset of the CPU is released, a predetermined initialization process by the CPU and the transfer of the program are executed in parallel. An information processing apparatus activation method. First storage means comprising a nonvolatile memory for storing a program;
Second storage means comprising a volatile memory;
Transfer means for transferring the program stored in the first storage means to the second storage means;
A CPU that executes processing according to a program stored in the second storage unit by the transfer unit;
A reset control means for holding the reset of the CPU at the time of startup of the apparatus and canceling the reset of the CPU at a predetermined release timing during the program transfer by the transfer means;
An information processing apparatus, wherein after the reset of the CPU by the reset control means is released, a predetermined initialization process by the CPU and a program transfer by the transfer means are executed in parallel. The first storage means stores start timing information indicating the release timing,
The information processing apparatus according to claim 2, wherein the reset release unit determines the release timing by monitoring a transfer amount of data transferred by the transfer unit. The program includes a designated program for executing a designated process designated in advance and a non-designated program other than the designated program,
The information processing apparatus according to claim 2, wherein a timing indicating completion of transfer of the designated program is set as the release timing. An interface unit comprising at least one of a user I / F that accepts an external operation or an external device I / F that inputs and outputs data with an external device;
The information processing apparatus according to claim 4, wherein the designation process includes at least a process of initializing the interface unit to a usable state. The CPU
It is detected whether the program corresponding to the request accepted by the interface means has been transferred to the second storage means, and when the program to be started has not been transferred, the program waits until the transfer of the program is completed. The information processing apparatus according to claim 5, wherein: Provided with display means for performing various displays,
The information processing apparatus according to claim 4, wherein the designation process includes at least a process of performing display control of the display unit.   The information processing apparatus according to claim 4, wherein the designation process includes at least a process of detecting an error in each part of the apparatus.

Images