JPS597972B2 - data transfer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control device that controls data transfer between a data transfer device such as a channel device and a storage device.

Figure 1 shows an example of the configuration of a conventional data transfer control device. In particular, it is assumed that there are four data transfer devices (hereinafter referred to as channels) and a storage device (hereinafter referred to as memory) in a four-bank configuration. are doing.

In the figure, 1 is a channel buffer register, 2 is a bank register, 3 is a bank multiplexer, 4 is a bank selector, 5 is a channel address register, 6 is a channel multiplexer, T is a channel selector, 8 is a memory buffer register, and 9 is channel data 10 is a memory data bus, 11 is a data line for bank o, and 12 is a data line for channel o. First, channel o (C
The data received from H#0) is transferred to memory bank 0 (B
The operation of READ type commands written to K#0) will be explained.

Data sent through the channel data bus 9 for the o-th channel is set in the channel buffer register 1 for the o-th channel. The channel buffer register 1 is a data buffer register having a capacity that does not cause channel overrun. The data set in the channel buffer register 1 for the o-th channel is placed on the data line 11 for bank 0 by the action of the bank multiplexer 3 which receives instructions from the bank register 2.
The data placed on the data line for bank o is set in the memory buffer register 8 of bank o by the action of channel selector T which receives instructions from channel address register 5 for bank 0. The memory buffer register 8 is a buffer register for guaranteeing write data to the memory, and the data set in the memory buffer register 8 is transferred to the memory data bus 10 of bank o.
through to memory (bank 0). Next, the operation of a WRITE command that sends data read from bank o of the memory to channel o will be explained. Data sent from the memory data bus 10 of bank 0 is set in the memory buffer register 8 of bank o. The data set in the memory buffer register 8 is placed on the data line 12 for channel No. 0 by the action of the channel multiplexer 6 of bank O, which receives instructions from the channel address register 5. The data placed on the data line 12 for the No. 0 channel is set in the channel buffer register 1 for the No. 0 channel by the function of the bank selector 4 which receives instructions from the bank register 2 of the No. 0 channel. The data set in the channel buffer register 1 is sent to the O-th channel through the channel data bus 9 for the O-th channel. Similarly, data transfer between channel i and bank j is generally possible. However, the conventional technique shown in FIG. 1 has the following drawbacks.

For example, when a READ command is used to send data from channel 0 first to bank O and then to bank 1, the bank multiplexer 3 is switched from bank O to bank 1. data cannot be guaranteed. Therefore, a memory buffer register 8 is provided for each bank in order to guarantee write data to the memory. However, this register is
This register is shared by all channels from channel No. 3 to channel No. 3, so for example, if channel No. 0 is using this register, other channels must wait until the use of channel No. O is finished. . Also, WRI
Even in the operation of TE type commands, for example, if channel O first receives data from bank O and then receives data from bank 1, the bank selector 4 is switched from bank O to bank 1, so the data in bank O is guaranteed. However, the memory buffer register 8 corresponding to the bank is still required. However, even in this case, for example, 0
If channel No. 0 is using this register, other channels will have to wait until channel No. O is finished using it. In this way, in conventional data transfer control devices, when multiple channels try to use the same bank, the subsequent channels wait until the memory buffer register is available for use after the memory access operation of the preceding channel is completed. The drawback was that I was unable to move at all until I realized that.

SUMMARY OF THE INVENTION An object of the present invention is to increase as much as possible the contention range of memory access operations from a plurality of channels to the same bank in a data transfer control device, and to reduce the time taken by each channel.

In order to achieve the above object, the present invention provides a memory buffer register that is shared by a plurality of channels in the past for each channel, and at the same time provides a buffer function by making it a data register with a shift structure. It is characterized by: Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 2 shows an embodiment of a data transfer control device according to the present invention, and the same parts as in FIG. 1 are given the same symbols.

In the figure, reference numeral 28 denotes a memory buffer register with a shift structure, which has a storage area for READ-related commands and WRITE-related command operations corresponding to each bank for each bank. For convenience, referring to the storage area for channel 0 in the memory buffer register 28 of bank O, one of the areas is connected to the bank multiplexer 3 through the data line 11 for bank O, and the write data line 1 for bank O.
The other one is connected to the channel multiplexer 6 through the read data line 14 for the 0th channel, and to the bank selector 4 through the data line 12 for the 0th channel. First, the operation of a READ command that writes data received from channel 0 to bank O of the memory will be explained.

The data sent on the channel data bus 9 for channel No. 0 is set in the channel buffer register 1 for channel No. 0. The data set in the channel buffer register 1 is placed on the data line 11 for bank O by the action of the bank multiplexer 3 which receives instructions from the bank register 2. The data placed on the data line for bank O is set in the storage area for channel O on the memory buffer register 28 of bank O. The data set in the storage area for channel O is shifted within the area and placed on the write data line 13 for channel O in bank O, and is stored in the channel address register 5 of bank O. The channel selector 7 receives the instruction and sends the data to the memory via the memory data bus 10 of bank O. Assume that during this operation, for example, a request to write data received from channel 1 to banter 0 occurs. In this case, in parallel with the above operation, the data sent on the channel data bus 9 for the first channel is set in the storage area for the first channel on the memory buffer register 28 of the bank O. , then wait for channel 0 to finish writing,
It will be sent to memory via memory data bus 10 in bank 0. Next, the operation of a WRITE command that sends data read from bank 0 of the memory to the O channel will be explained.

The data sent on the memory data bus 10 of bank O is placed on the read data line 14 for channel No. 0 in bank O by the action of the channel multiplexer 6 which receives instructions from the channel address register 5. This data is set in the storage area for channel O on the memory buffer register 28 of bank 0. The data set in the storage area for the 0th channel is shifted through that area, placed on the data line 12 for the 0th channel, and then transferred to the bank specified by the bank register 2 for the 0th channel. By the action of the selector 4, it is set in the channel buffer register 1 for the O channel. The data set in the channel buffer register for the 0th channel is sent to the 0th channel via the channel data bus 9 for the 0th channel. During this operation, for example, if a request to write data received from channel 1 to bank O occurs, the data sent on channel data bus 9 for channel 1 will be written in the same way as before. It is independently set in the storage area for the 1st channel on the memory buffer register 28 of Banter 0, and sent to the memory of bank O after waiting for the end of reading of the 0th channel. Also, for example, if a request to send data from bank 0 to the first channel occurs successively, the data read from bank O will be transferred to the memory buffer register 28 of bank O.
Immediately after being set in the storage area for channel O above, the channel multiplexer 6 of bank O is switched to channel 1, so that the next data read from bank O is stored on the memory buffer register 28 of bank 0. Since this is independently set in the storage area for the 1st channel, the WRITE commands for the 0th channel and the 1st channel are executed in parallel. As explained above, according to the present invention, the data buffer function that was conventionally available only in channel images can be extended to memory images. time can be reduced.

[Brief explanation of drawings]

Fig. 1 } 1 A diagram showing a conventional example of a data transfer control device, 2
The figure shows an embodiment of the present invention. 1... Channel buffer register, 2...
...Bank register, 3...Bank multiplexer, 4...Bank selector, 5...
Channel address register, 6...Channel multiplexer, 7...Channel selector, 8,
28...Memory buffer register, 9...
... Channel data bus 10 ... Memory data bus, 11, 12 ... Data line, 13.
...Write data line 14...Read data line.

Claims (1)

[Scope of Claims] 1. Between a plurality of data transfer devices (hereinafter referred to as channels) and a storage device consisting of a plurality of banks (hereinafter referred to as memory), any channel and any bank may be connected as appropriate. In the data transfer control device, a buffer register having a data storage area equal to the number of channels is provided for each bank of the memory, and data transfer from a plurality of channels to the same bank is performed using the buffer register for the bank. A data transfer control device that performs data transfer in parallel. 2. The data transfer control device according to claim 1, wherein the buffer register has a shift configuration.