JPH03147457A - Debugger for peripheral equipment in exchange - Google Patents

Abstract

PURPOSE:To attain debugging without need for rewrite of a program and a data from a central control circuit by providing a debug means in addition to a central control means to apply write/read of a data from a terminal equipment to a memory circuit. CONSTITUTION:A debug control circuit y recognizes a request from a terminal equipment 9 via a terminal control circuit 8, controls the circuit 8 to obtain a data inputted to the equipment 9, decodes it and in the case of a memory read request, a reference instruction of the memory circuit 4 and the reference address data for the circuit 4 are obtained. Then the circuit 7 controls a memory access circuit 6 to access the circuit 4 when the bus 5 is idle and to read a required data and controls the circuit 8 to send the readout data to the equipment 9. The equipment 9 displays the content of the sent data from the circuit 4. when the request from the equipment 9 is a memory write request, the circuit 7 recognizes the memory rewrite request from the equipment 9 via the circuit 8 to control the circuit 8 thereby acquiring the rewrite data of the circuit 4 inputted to the equipment 9.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a peripheral device of a switch having a central control circuit, and more particularly to a debugging device for a peripheral device in a switch that can be used during the operation of the peripheral device. be.

[Conventional technology]

Conventionally, as a debugging device for a peripheral device in this type of exchange, there has been one having a configuration as shown in FIG.

In FIG. 2, reference numeral 21 denotes a peripheral device of the exchange, and the peripheral device 21 of the exchange is composed of a central control circuit 22, a relay circuit 23, a bus 24, and a terminal control circuit 25. Reference numeral 26 denotes a terminal device, which is connected to the terminal control circuit 25 and used as a debugging terminal for the peripheral device 21.

In the debugging device for a peripheral device in an exchange configured as described above, the central control circuit 22 directly controls the terminal control circuit 25 according to a program stored in the memory circuit 23 in response to a debug command input from the terminal device 26. After receiving, analyzing and processing the command, the results are returned to the terminal device 26 via the terminal control circuit 25.

[Problem to be solved by the invention]

In the above-mentioned conventional debugging device for peripheral devices in exchanges, since the terminal control circuit is controlled by the central control circuit, there is a problem in that a program for the terminal control circuit must be prepared in the program for the central control circuit.

Furthermore, in order to control the terminal control circuit for debugging, the central control circuit operates in a manner different from its original operation, making accurate debugging impossible.

[Means to solve the problem]

A debugging device for a peripheral device in an exchange according to the present invention is a peripheral device for an exchange having a central control circuit, and includes a debug control means for debugging the central control circuit during operation, and a debug control means for the central control circuit to use a bus. a bus control means having a function of detecting when the debug control means is using the bus and having its central control circuit prohibit bus access when the debug control means is using the bus; and a bus use state detected by the bus control means. is sent to the above debug control means,
Memory access that connects the debug control means and the bus according to instructions from the debug control means, causes the debug control means to use the bus, and notifies the bus control means of the state in which the debug control means and the bus are connected. It houses means and a terminal device.

It is equipped with a terminal control means for controlling.

[Effect]

In the present invention, a debug control means separate from the central control means is provided to write and read data from the terminal device to the memory circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a debugging device for a peripheral device in an exchange according to the present invention.

In the figure, 1 is a peripheral device, and this peripheral device 1 is a central control circuit 2. Bus control circuit 3. Memory circuit 4, bus 5. Memory access circuit 6. Debug control circuit 7. It is composed of a terminal control circuit 8.

Reference numeral 9 denotes a terminal device, which is connected to the terminal control circuit 8 and used as a debugging terminal for the peripheral device 1.

Here, the central control circuit 2 is connected to the bus 5 via the bus control circuit 3. Further, the memory circuit 4 is connected to the bus 5 and stores programs and data necessary for the operation of the central control circuit 2.

Furthermore, the memory access circuit 6 is connected to the bus 5 and the bus control circuit 3.
and a debug control circuit 7, and arbitrates access to the bus 5 according to instructions from the debug control circuit 7.

The debug control circuit 7 constitutes debug control means for debugging the central control circuit 2 during operation, and the bus control circuit 3 detects when the central control circuit 2 is using the bus. The central control circuit 2 constitutes a bus control means having a function of prohibiting bus access when the debug control means is using the bus.

Further, the memory access circuit 6 sends the bus usage status detected by the bus control means to the debug control means,
The debug control means connects the debug control means and the bus 5 according to instructions from the debug control means, the debug control means uses the bus 5, and notifies the bus control means of the state in which the debug control means and the bus 5 are connected. The terminal control circuit 8 constitutes a terminal control means for accommodating and controlling the terminal device 9.

Next, the operation of the embodiment shown in FIG. 1 will be explained. First, the central control circuit 2 performs necessary control for the operation of the peripheral device 1 according to the program and data stored in the memory circuit 4. The bus control circuit 3 transmits and receives data between the central control circuit 2 and the bus 5, and the memory access circuit 6 determines whether the central control circuit 2 is accessing the bus 5 or not. Notify.

On the other hand, in order to refer to the data stored in the memory circuit 4 while the peripheral device 1 is in the normal operating state t, the address where the reference data is stored and the number of bytes of the data are input to the terminal device 9. .

The terminal R9 then sends the input data to the terminal control circuit 8. This terminal control circuit 8 notifies the debug control circuit T when data is sent from the terminal device 9.

This debug control circuit T learns that there is a request from the terminal device 9 via the terminal control circuit 8, controls the terminal control circuit 8, obtains the data input to the terminal device 9, and interprets it. For example, in the case of a memory read request, a reference command for the memory circuit 4 and reference address data for the memory circuit 4 are obtained.

Next, the debug control circuit 7 includes a memory access circuit 6
When the bus 5 is empty, the memory circuit 4 is accessed to read out necessary data, and the terminal control circuit 8 is controlled to send the read data to the terminal device 9. The terminal device 9 displays the sent contents of the memory circuit 4.

Further, when the request from the terminal device 9 is a memory write request, the debug control circuit 7 learns via the terminal control circuit 8 that there is a memory rewrite request from the terminal device 9, and controls the terminal control circuit 8. Then, the rewritten data of the memory circuit 4 manually entered into the terminal device 9 is obtained.

The debug control circuit T includes a memory access circuit 6
Information on whether the bus 5 is empty or in use is read out, and when the bus 5 becomes empty, a memory access circuit 6 is instructed to connect to the bus 5, and data from the terminal device 9 is written into the memory circuit 4.

The memory access circuit 6 notifies the bus control circuit 3 that the bus is in use while the debug control circuit 7 is accessing the bus 5.

Here, if the central control circuit 2 attempts to access the bus while the memory access circuit 6 is accessing the bus 5, the bus control circuit 3 will stop the central control circuit 2 from accessing the bus 5. let

In the embodiment shown in FIG. 1, the terminal device sending device 1
1- explains how to read and write data from the memory circuit connected to the bus 5, but it is also possible to read and write data in the same way even when using another interface circuit other than the memory circuit 4 connected to the bus 5. It can be carried out. Therefore, reading to the memory circuit 4.

The scope of the present invention is not limited to writing only.

〔Effect of the invention〕

As explained above, the present invention includes a debug control means separate from the central control means, and writes and reads programs and data for the central control circuit by writing and reading data from the terminal device to the memory circuit. There is no need to change the central control circuit, and debugging can be performed without changing the operation of the central control circuit from normal operation, making it possible to easily and accurately debug.

In addition, the bus control circuit, memory access circuit, debug control circuit, and terminal control circuit nodeware and 7
Armware has the advantage that once developed, it can be used universally for different peripheral devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a debugging device for a peripheral device in an exchange according to the present invention, and FIG. 2 is a block diagram showing an example of a debugging device for a peripheral device in a conventional exchange. 1...Peripheral device, 2...Central control circuit, 311
〇・Bus control circuit, 4...also memory circuit, 5...
・Bus, 6...Memory access circuit, T...Debug control circuit, 8・Φ・One terminal control circuit, 9...
Terminal device.

Claims (1)

[Claims] In a peripheral device of an exchange having a central control circuit, the central control circuit includes debug control means for debugging during operation, and the debug control means detects when the central control circuit is using a bus. bus control means having a function of prohibiting the central control circuit from accessing the bus when the central control circuit is using the bus; and sending the bus usage state detected by the bus control means to the debug control means;
Memory access for connecting the debug control means and a bus according to instructions from the debug control means, allowing the debug control means to use the bus, and notifying the bus control means of a state in which the debug control means and the bus are connected. 1. A debugging device for a peripheral device in an exchange, comprising: a device for debugging a peripheral device in an exchange; and a terminal control device for accommodating and controlling a terminal device.