JPH03208158A - Electronic controller - Google Patents

Abstract

PURPOSE:To avoid the occurrence of the abnormality of an action owing to the combination of the types of program storage means by collectively storing control program data in a master control means and a slave control means in single ROM. CONSTITUTION:Program data for master CPU 20 and slave CPU 80 are previously stored on ROM 50 in prescribed address arrangement. The action of CPU 80 is prohibited immediately after power is supplied, and CPU 20 transfers program data for CPU 80, which is stored in ROM 50, onto a common memory means RAM 70. Then, the action of CPU 80 is allowed and CPU 80 reads data transferred on RAM 70 and executes the program. Writing can be executed on RAM 70 from CPU 80 and the area of program data and the work area of CPU 80 co-exist on RAM 70. A decoding means 90 and a write prohibition means G2 are provided and the writing of CPU 80 is prohibited, whereby the erroneous writing of CPU 80 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic control device comprising a plurality of independent control means such as microprocessors.

[Conventional technology] Because the control content of conventional technology, such as copying machines and facsimile machines, has become complicated, it is often impossible to control the entire system with a single CPU (eg, microprocessor 2 or less). Therefore, in such applications, the control device is often equipped with multiple CPUs. By the way, in general control devices, the control program for the CPU is stored in advance in a ROM (read-only memory) that the CPU can access.
Processing is executed sequentially while reading the contents of M. In a control device equipped with multiple CPUs, an independent ROM is connected to each CPU, and each ROM stores a corresponding CPU control program.
Each is configured so that only the intended CPU can access it.

[Problem to be solved by the invention] By the way, in order to improve the processing content and take measures against bugs, the CPU
The program is updated from time to time. When updating the control device program, the CPU can be updated by replacing the ROM connected to the CPU with another ROM with updated contents.
Change the data of the program read by . multiple CPUs
Even in a control device equipped with a CPU, the ROM of the CPU to be changed is replaced every time the program for each CPU is updated.

However, in a control device equipped with multiple CPUs,
Since processing is divided among multiple CPUs for the same system, processing timing, content of output data,
Processing address values, etc. may mutually affect the operations of different CPUs. Therefore, depending on the combination of mutual program versions of multiple CPUs, system functions may not function properly. If all CPU programs were placed on a single ROM, the above combination problem would not occur, but
Since multiple CPUs cannot commonly access a single ROM, problems caused by combinations of multiple ROMs have conventionally been unavoidable.

Therefore, it is an object of the present invention to eliminate the occurrence of operational abnormalities due to combinations of types of program storage means in a control device including a plurality of control means such as a CPU.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, main reset means for generating a main reset signal: master control means for receiving the main reset signal; at least one of the master fI/IJl1 A slave control means that performs processing independent of the slave control means; A sub-reset means that generates a sub-reset signal to be applied to the slave control means; A sub-reset means that is connected to the master control means and controls both the master control means and the slave control means. read-only memory means for retaining information determining the operation of the controller; and common memory means at least writeably connected to the master control means and at least readably connected to the slave control means; , the master control means controls the sub-reset means, transfers the information on the read-only memory means onto the common memory means in response to the main reset signal, and after the transfer is completed, the slave control means controls the sub-reset means. Configure to allow operation.

[Operation] According to the present invention, control program data for the master control means and slave control means (CPU) can be stored together in a single read-only memory means (ROM). Therefore, there is no possibility that abnormal operation will occur due to a combination of program versions.

For example, immediately after the power is turned on, the operation of the slave control means is prohibited, and in this state, the master control means transfers the program data for the slave control means stored in the read-only memory means onto the common memory means. , then permit the operation of the slave control means. The slave control means reads the data transferred onto the common memory means and executes the program.

In a preferred embodiment of the present invention, which will be described later, the common memory means is configured to be writable also by the slave control means,
The program data area and the work area of the slave control means coexist on the common memory means. Further, in order to prevent the slave control means from erroneously writing to the program data area, an address decoding means and a write inhibiting means are provided, and writing by the slave control means to the program data address is prohibited.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

Embodiment FIG. 1 shows the structure of the main parts of a control device according to an embodiment. In FIG. 1, illustrations of the controlled object, the input and output ports connected thereto, and the input/output interface circuit are omitted.

Referring to FIG. 1, the control device includes two microprocessors 20 and 80.

In this example, one microprocessor 20 is the master C
The other microprocessor 80 is assigned as a PU.
is assigned as a slave CPU. Master CP
The data bus 2l of U20 includes ROM (read-only memory) 50, RAM (read/write memory) 60 and 7.
0 is connected.

ROM50, RAM60 and 70 are master CPU20
are assigned to mutually different addresses, and the master C
The PU can selectively access any of these chips by specifying an address. The address information output by the master CPU is identified by the address decoder 40, and when an address within a specific area allocated to each chip is detected, a chip selection signal applied to each chip is activated (corresponding to an access permission state). ).

On the ROM 50, program data for the master CPU 20 and program data for the slave CPU 80 are stored in advance at predetermined address locations. Therefore, immediately after the power is turned on and a reset signal, which will be described later, is released, the master CPU 20 stores the master CPU on the ROM 50.
reads its own program data from the address assigned to it and executes it. The RAM 60 is used as a work area for temporarily storing various information necessary for the master CPU 20 to execute its processing. On the other hand, the RAM 70 is called a dual port memory and has two sets of input/output channels including a data bus and an address bus. This memory is manufactured by Fujitsu (
The MB8421 is manufactured by Co., Ltd., and can perform input (i.e., writing) and output (i.e., reading) asynchronously from any input/output channel. In this embodiment, one channel of the RAM 70 is connected to the master CPU.
20 is connected and the slave CPtJ is connected to the other channel.
The RAM 70 to which the CPU 80 is connected is used both as an area for storing program data for the slave CPU 80 and as a work area for the slave CPU 80. Since the RAM 70 is a volatile memory, no program data exists on the RAM 70 in the initial state. In this example, the program data for the slave CPU 80 is provided on the ROM 50, so when the power is turned on, the master CPU 20 first
○Slave CP that accesses M50 and exists in it
The program data for U is transferred to a predetermined address on the RAM 70. After that, the operation of the slave CPU 80 is permitted.

The reset circuit 10 is a circuit that generates a pulse of a reset signal for a predetermined period of time when the power is turned on, and this reset signal is applied to the master CPU 20 and the flip-flop 30. The master CPU 20 is initialized by a reset signal and sets the address counter to an initial value (generally o o
o o) and the reset signal is released,
The program data is read from the initial value address and the program is executed sequentially.

The flip-flop 30 resets i! Upon receiving the main reset signal output from the slave CPU 810, it outputs a sub reset signal to the slave CPU 80. This sub-reset signal is held even after the main reset signal is released, and is released under the next set condition. That is, after the main reset signal is released, the master CPU 20 resets the flip-flop 30.
When data with a predetermined bit (the bit connected to input D) set is written to a predetermined address assigned to the flip-flop 30, the flip-flop 30 is set and its output terminal Q becomes H (high level). Therefore, slave CPU8 0
The reset will be canceled.

When the slave (:PU80) is released from its reset, it reads the program data from the initial address cleared by the sub-reset signal and executes the program sequentially. In this embodiment, the initial address is RAM7.
Since the address is assigned to match the first address of 0, the slave CPU 80 is
0, the program data transferred from the ROM 50 to the RAM 70 is read and the program is executed.

In this control device, a memory address map is allocated as shown in FIG. Referring to Figure 3,
The master CPU 20 can read and write all addresses on the RAM 70, but for the slave CPU 80, the addresses on the RAM 70 are divided into two functionally different areas. That is, the slave CPU 80 can read but cannot write to the program area, and can read and write to other work area addresses.

Referring again to FIG. 1, the second write control terminal WR2 (inverted symbol (overline) is omitted, the same applies hereinafter) of the RAM 70 is connected to the slave CPU 80 via the gate G2.
A gate signal output from the decoder 90 is applied to one input terminal of the gate G2.

The decoder 90 is connected to the address bus of the slave CPU 80, detects when the slave CPU 80 outputs address information within a specific range, and outputs a signal. In reality, the signal output from the decoder 90 is
The signal that becomes active when a value within the entire address area on the RAM 70 shown in the figure is detected. These are two signals that become active when a value in the work area on the RAM 70 is detected. The former signal is applied to the chip select terminal CS2 of the RAM 70, and the latter signal is applied to the input terminal of the gate G2. In other words, when the slave CPU 80 outputs address information of the program area to the address bus, even if the slave CPU's programming terminal WR becomes active (L), the output of the gate G2 remains inactive (H). As a result, the write terminal WR2 of the RAM 70 does not enter the sleep state, and therefore no writing is performed to the program area. This can prevent the occurrence of erroneous writing and reduce the possibility of device runaway. In Figure 1, RST is the reset terminal, RD, R
DL, RD2 are read control terminals, WR, WRI, WR2
indicates a write control terminal, CS, CSI, and CS2 indicate chip select control terminals, CLR indicates a clear control terminal, and OE indicates an output permission terminal.

FIG. 2 shows an outline of the processing when the power of the master CPtJ20 shown in FIG. 1 is turned on. That is, in FIG. 2, in step 1, the master CPU initializes itself;
In step 2, some data on the ROM (slave CP
The program data of U) is transferred to the program area on the RAM 70. In the next step 3, the sub-reset signal is released by setting the flip-flop 3o, and the operation of the slave CPU 80 is permitted. After this, the master CPU performs normal operations.

In the above embodiment, a case is shown in which the control device is configured with a single master cPU and a single slave CPU, but the present invention can be implemented in the same way, for example, when a plurality of slave CPUs are provided. I can do it. In that case, a dual port memory may be interposed between each slave CPU and master CPU. Furthermore, for example, a lower slave CPU may be connected to the slave CPU. In that case, a dual port memory may be interposed between the upper slave CPU and the lower slave CPU.

In the above embodiment, a dual boat memory that can be read and written from either channel was used, but the minimum function is that it can be written from the master side and read from the slave side. It's fine as long as it's possible.

[Effects] As described above, according to the present invention, program data for both the master control means (20) and the slave control means (80) can be arranged together on a single read-only memory means (50). can. Therefore, even if a program is updated to improve the program or take measures against bugs, and multiple types of ROMs with different versions are created, the compatibility of the master control means and slave control means for any of the ROMs is not compatible. You can make it so that it doesn't exist from the beginning. It is possible to avoid malfunction of the device due to ROM replacement.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the electrical circuitry of one type of control device embodying the invention. FIG. 2 is a flowchart showing the operation of the master CPU 20 of FIG. 1 immediately after power is turned on. FIG. 3 is a memory map of the main parts of the device of FIG. 1. 10: Reset circuit (main reset means) 20: Master C
PU (master control means) 30: flip-flop (sub-reset means) 40: address decoder 50: ROM (read-only memory means) 60:
RAM 70: Dual port memory (common memory means) 80:
Slave CPU (slave control means) 90: Decoder (address decoding means) G2: Gate (write inhibiting means)

Claims (3)

[Claims] (1) Main reset means for generating a main reset signal; master control means for receiving the main reset signal; slave control means for executing at least one process independent of the master control means; sub-reset means for generating a sub-reset signal; read-only memory means connected to said master control means for holding information determining the operation of both said master control means and said slave control means; and said master control means. a common memory means at least writeably connected to the slave control means and at least readably connected to the slave control means; and the master control means controls the sub-reset means and receives the main reset signal. An electronic control device responsive to transferring information on said read-only memory means onto said common memory means and permitting operation of the slave control means after the transfer is completed. (2) The electronic control device according to claim 1, wherein the common memory means is configured to be freely writable to the slave control means. (3) address decoding means for recognizing a specific address from the address information output by the slave control means;
3. The electronic control device according to claim 2, further comprising write inhibiting means for inhibiting writing from the slave control means to the common memory means when said means detects a specific address.