JP2005228142A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control circuit for preventing malfunction due to the delay of access even at the time of continuously performing access to a plurality of different banks. <P>SOLUTION: This memory control circuit is provided with a control circuit which controls access to a memory having a plurality of banks. This memory control circuit is provided with an access deciding circuit which decides an access method to the memory based on the first signal for selectively designating the addresses of the plurality of banks and a second signal for selectively activating the plurality of banks. The access deciding circuit is configured to control the control circuit in order to set a period to inactivate the plurality of banks when the activation of the plurality of banks is switched based on the decision result when the first signal shows the designation of the plurality of banks, and the second signal shows the continous activation of the plurality of banks. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory control circuit.

Some memories are divided into a plurality of blocks (banks) and accessed for writing and reading data. Access to the memory is executed by a memory control circuit described later.
The memory control circuit selects one of a plurality of banks constituting the memory according to an instruction from the CPU, and writes or reads data by designating a predetermined address in the selected bank. (For example, refer to Patent Document 1).

  FIG. 5 shows a time chart for explaining the timing of change of the read state by the conventional memory control circuit. This figure shows an example in which a memory control circuit accesses and reads out a memory (16 bits × 1 memory, hereinafter referred to as a 16-bit memory) having 16 bits stored in each address. That is, it is a time chart when accessing one bank. For example, an SRAM can be used as the memory.

  The memory control circuit is connected to the CPU via an address bus and a data bus, and generates Valid and State signals in accordance with instructions from the CPU in the memory control circuit. Valid is a signal indicating access to the memory, and the state signal is a signal for setting various states in the memory.

  The memory control circuit outputs an address signal ADDR, a chip select signal nCS, a read signal nRD, a low byte select signal nLB, an nHB / nWRH signal to the connected memory, and a terminal for inputting / outputting a DATA signal. It has. On the other hand, the connected 16-bit memory has a terminal for inputting an address signal ADDR, a chip select signal nCS, a read signal nRD, a low byte select signal nLB, an nHB signal, and a DATA signal corresponding to the output of the memory control circuit. It has a terminal for input and output. Each of the above signals changes in synchronization with the system clock CLK set for operating the memory control circuit in the CPU.

First, signals in the memory control circuit will be described.
The address bus is a memory address transfer path between the CPU and the memory control circuit, and the memory address to be read or written is designated by the CPU.
The data bus serves as a transfer path for reading and writing data of a designated memory between the CPU and the memory control circuit.

The state signal is a signal indicating the state of access to the memory in the memory control circuit. There are TACS, TCOS, TACC, and TCOH as signals indicating the memory access state.
TACS is a signal that specifies a memory address but does not activate the memory.
The TCOS is a signal indicating a state in which the memory is activated but writing or reading is not performed.
TACC is a signal indicating a state in which writing or reading is executed.
TCOH is a signal indicating a state in which the memory is not deactivated after completion of writing or reading.

IDLE is a signal indicating that the memory is not being accessed.
The state of the normal memory access changes through a state corresponding to this state signal when the state signal changes in the order of IDLE → TACS → TCOS → TACC → TCOH → IDLE. The memory control circuit can control the length and timing of this state signal.

  Valid is a signal indicating that the memory is activated when it becomes “HIGH” and the memory is accessed. After this Valid becomes “HIGH”, it becomes “LOW” after the same clock period as the period in which the state signals TACS, TCOS, TACC, and TCOH sequentially change.

Next, signals output from the memory control circuit to the memory will be described.
The address signal ADDR is a signal for the memory control circuit to specify the memory address specified by the address bus to the memory. Therefore, the same address as the address bus is designated for the address signal ADDR. This memory address designation starts when the memory control circuit changes from the IDLE state to another state. In addition, the period in which the memory control circuit designates this address is the same clock period as the period in which the state signals TACS, TCOS, TACC, and TCOH sequentially change.

  The chip select signal nCS is a signal for selecting a memory bank, and the selected bank is activated when the chip select signal nCS becomes “LOW”. The period when the chip select signal nCS is “LOW” (“predetermined period”) is the same clock period as the period when the state signals TCOS, TACC, and TCOH of the memory control circuit sequentially change. After this period, the chip select signal nCS becomes “HIGH” and the bank is inactivated.

  The read signal nRD is a signal for reading data output from the memory accessed by the memory control circuit, and is activated when it becomes “LOW”. The period in which the read signal nRD is “LOW” is the same clock period as the period of the state signal TACC, and becomes “HIGH” after this period.

  The DATA signal is a signal for transferring write data or read data for the memory between the memory control circuit and the memory. The data stored in the memory is read at a timing when the state signal is switched from TACC to another signal.

  The low byte select signal nLB is a signal indicating that the lower bit (byte) of the memory is selected, and is activated when it becomes “LOW”. For example, when a 16-bit memory is used, when nLB becomes “LOW”, the lower 8 bits (1 byte) are selected. The period when the low byte select signal nLB is “LOW” is a period when the memory to be accessed is a 16-bit memory and the chip select signal nCS is “LOW”. When the memory to be accessed is 8 bits, the nLB signal becomes “HIGH”.

nHB / nWRH has a terminal shared by nHB and nWRH, and is switched depending on the type of memory to be connected.
The high byte select signal nHB is a signal for selecting the upper side of the memory, for example, the upper 8 bits (1 byte) of 16 bits, and is activated only when the memory to be accessed is a 16-bit memory.
The write high byte signal nWRH is a signal for writing to the memory and indicates that the upper side of the data bus is valid.

  Access to the memory is, for example, a 16-bit memory, and a memory having two memories each having an 8-bit number of bits stored in each address (8-bit × 2 memory, hereinafter referred to as 8-bit memory) ), The terminal switches from nHB to nWRH. Since the memory to be accessed is 16 bits in FIG. 5, the terminal functions as nHB at this time.

  In the read operation, nHB / nWRH is “LOW” when the chip select signal nCS is “LOW” when accessing the 16-bit memory, and “HIGH” when accessing the 8-bit memory.

  Next, the time chart of FIG. 5 will be described. <Internal signal> indicates a signal in the memory control circuit, and <Terminal> indicates a signal output from the memory control circuit to the memory.

First, <internal signal> will be described.
The address A0 of the memory that is accessed from the CPU during the period from t0 to t1 is designated on the address bus.
At the same time, Valid becomes “HIGH” at t0, and the state signal changes from IDLE to TACS at t1 accordingly.
Valid becomes “LOW” after the same clock cycle as the period other than the period when the state signal is IDLE, that is, at t4.

  The state signal changes in the order of IDLE → TACS → TCOS → TACC → TCOH → IDLE. First, it changes to TACS at t1, TCOS at t2, TACC at t3, and TCOH at t4. Further, the state signal changes to IDLE at t5 when Valid becomes “LOW” at t4.

Next, the signal of <terminal> will be described. All of these signals change based on the state signal.
First, at t1 when the state signal changes to TACS, the address A0 specified by the CPU on the address bus is specified as the address signal ADDR.
The chip select signal becomes “LOW” at t2 when the state signal changes to TCOS.
Since the memory to be accessed at the same time is a 16-bit memory, nLB becomes “LOW” and nHB / nWRH also becomes “LOW”.
Next, at t3 when the state signal changes to TACC, the read signal nRD becomes “LOW”.
At t4 when the state signal changes from TACC to TCOH, the read signal nRD becomes “HIGH”, and the data D0 stored at the address A0 is read to the DATA signal.
The read data D0 is output to the data bus of <internal signal>.
At t5 when the state signal changes to IDLE, the chip select signal nCS becomes “HIGH”, and the designation of the address A0 of the address signal ADDR is completed.

  As described above, in the memory control circuit, the state signals TACS, TCOS, TACC, and TCOH for the state for reading or writing of the memory are set, and address setup and bank selection are performed for tacc during the period of reading or writing. Periods tacs, tcos, and tcoh for setup are provided.

In this embodiment, if one clock period is 1, tacs = tcos = tcoh = 1 and tacc = 3, and the state signal changes according to this period. Although tacc, which is a period during which writing or reading is performed, is a value other than 0, tacs, tcos, and tcoh can be set to 0 when accessing at high speed.
Japanese Patent Laid-Open No. 11-328095

FIG. 6 is a time chart for explaining a problem caused by a conventional memory control circuit.
In this example, two banks of a 16-bit memory (hereinafter referred to as bank 0) and an 8-bit memory (hereinafter referred to as bank 1) are connected as memories accessed by the memory control circuit.
The memory control circuit receives read and write instructions from the CPU via the address bus and data bus, and generates Valid and state signal signals.
In addition, the memory control circuit performs an address signal ADDR, a chip select signal nCS0 to the bank 0, a chip select signal nCS1 to the bank 1, a read signal nRD, a low byte select signal nLB, nHB / A terminal for outputting an nWRH signal and a terminal for inputting and outputting a DATA signal are provided.
Bank 0, which is a 16-bit memory, inputs a terminal for inputting an address signal ADDR, a chip select signal nCS0, a read signal nRD, a low byte select signal nLB, an nHB signal and a DATA signal corresponding to the output of the memory control circuit. A terminal for output is provided.

On the other hand, bank 1, which is an 8-bit memory, has terminals for inputting address signal ADDR, chip select signal nCS1, read signal nRD, nWRH and terminals for inputting / outputting DATA signals corresponding to the output of the memory control circuit. I have.
Each of the above signals changes in synchronization with the system clock CLK set for operating the memory control circuit in the CPU.

Next, the time chart of FIG. 6 will be described.
In the case of FIG. 6, tacs = tcos = tcoh = 0 is set in accordance with the state signal in both bank 0 and bank 1 for high speed access. Note that tacs, tcos, tacc, and tcoh for bank 0 are tacs0, tcos0, tacc0, and tcoh0, respectively, and tacs, tcos, tacc, and tcoh for bank 1 are tacs1, tcos1, tacc1, and tcoh1, respectively. The valid and state signals for bank 0 are the Valid0 and state 0 signals, respectively, and the valid and state signals for bank 1 are the Valid1 and state 1 signals, respectively.

First, <internal signal> will be described.
The address A0 of the bank 0 is specified from the CPU to the address bus during the period t0 to t1, and then the address A1 of the bank 1 is specified from the time t1 to t3.
By specifying the address A0 of the bank 0, Valid0 becomes “HIGH” at t0.
Valid0 becomes “LOW” after the same clock period has elapsed in the state 0 signal other than the period other than IDLE, that is, at t2.
When Valid0 is “HIGH”, the state 0 signal changes from IDLE to TACC at t1. In this example, since tacs0 = tcos0 = tcoh0 = 0, the state 0 signal changes in the order of IDLE → TACC → IDLE.
Further, the state 0 signal changes from TACC to IDLE at t3 in response to Valid0 becoming “LOW” at t2.

On the other hand, at t2, Valid0 becomes “LOW” and at the same time, Valid1 according to the designation of the address A1 of the address bus becomes “HIGH”.
Valid1 becomes “LOW” after the same clock period as that of the period other than IDLE in the state 1 signal, that is, at t4.
When Valid1 is “HIGH”, the state 1 signal changes from IDLE to TACC at t3. In this example, since tacs1 = tcos1 = tcoh1 = 0, the state 1 signal changes in the order of IDLE → TACC → IDLE.
The state 1 signal changes from TACC to IDLE at t5 when Valid1 becomes “LOW” at t4. Next, the signal at <terminal> will be described. All of these signals change based on the state signal.
First, at t1 when the state 0 signal changes to TACC, the address A0 designated by the CPU on the address bus is designated as the address signal ADDR.
At the same time, the chip select signal nCS0, the read signal nRD, the low byte select signal nLB, and the nHB / nWRH signal of the bank 0 become “LOW”, and the read access of the bank 0 is started.
Then, at t3 when the state 0 signal changes from TACC to IDLE and the state 1 signal changes from IDLE to TACC, the designation of the address signal ADDR is switched from the address A0 of the bank 0 to the address A1 of the bank 1. Further, the chip select signal nCS0 of the bank 0 becomes “HIGH”, and the chip select signal nCS1 of the bank 1 becomes “LOW”.
In this case, since the bank 0 and the bank 1 are continuously read, the read signal nRD remains “LOW” at t3.

Since the memory to be accessed is changed from the 16-bit memory to the 8-bit memory, the low byte select signals nLB and nHB / nWRH signals become “HIGH” at t3.
Data D0 stored at address A0 is read out to the DATA signal.
The read data D0 is output to the data bus of <internal signal>.
At the same time, the change of the state 1 signal causes the chip select signal nCS1 to be “LOW” at t3, and the bank 1 read access is started.
At t5 when the state 1 signal changes from TACC to IDLE, the read signal nRD and the chip select signal nCS1 become “HIGH”, and the designation of the address A1 by the address signal ADDR is completed.
The data D1 stored at the address A1 is read to the DATA signal. The read data D1 is output to the data bus of <internal signal>.

  As shown in the time chart of FIG. 6, when the state signals TACS, TCOS, and TCOH are passed to perform high-speed access, switching between Valid0 and Valid1 “HIGH” period is continuous at t2, and from A0 of the address signal ADDR. The designation switching to A1 is also continuous. In this case, the change of the chip select signal nCS0 from “LOW” to “HIGH” and the change of the chip select signal nCS1 from “HIGH” to “LOW” are t3 of the same timing.

  The nHB / nWRH terminal is switched from nHB to nWRH in accordance with the switching to the 8-bit memory of bank 1, and the nHB / nWRH signal is changed from “LOW” to “HIGH so that writing to bank 1 is not performed. To change. When the rising timing of nHB / nWRH to “HIGH” is delayed as indicated by a dotted line in FIG. 6 due to a circuit delay or the like, the chip select signal nCS1, the nWRH signal, and the read signal nRD all become “LOW”. A period arises. Therefore, writing and reading of the bank 1 are indefinite and there is a risk of malfunction.

  As described above, the conventional memory control circuit has a problem that there is a risk of malfunction due to access delay when accessing different banks successively.

  It is an object of the present invention to provide a memory control circuit that prevents malfunction due to access delay even when consecutive accesses are made to a plurality of different banks.

  A main invention according to the present invention is a memory control circuit comprising: a control circuit that controls access to a memory having a plurality of banks; a first signal for selectively designating addresses of the plurality of banks; An access determination circuit for determining an access method for the memory based on a second signal for selectively activating a plurality of banks, wherein the access determination circuit has the first signal for the plurality of banks. And deactivating both the plurality of banks when the activation of the plurality of banks is switched based on the determination result when the second signal indicates that the plurality of banks are to be activated continuously. The control circuit is controlled so as to provide a period.

  Other features of the present invention will become apparent from the accompanying drawings and the description of this specification.

  According to the present invention, it is possible to prevent malfunction due to access delay even when consecutive accesses are made to a plurality of different banks.

=== Configuration of Memory Control Circuit ===
FIG. 1 is a block diagram for explaining a memory control circuit according to an embodiment of the present invention. Note that the memory control circuit shown in FIG. 1 is an integrated circuit.

In the following description, the inside of the integrated circuit is referred to as the inside, and the outside of the integrated circuit is referred to as the outside.
The integrated circuit 100 includes a CPU 200 and a memory control circuit 300. In the present embodiment, the memory control circuit 300 accesses the memory 400 and the memory 500 based on an instruction from the CPU 200 to perform reading or writing.
Here, a 16-bit memory, for example, is connected to the memory 400 (hereinafter referred to as bank 0), and an 8-bit memory, for example, is connected to the memory 500 (hereinafter referred to as bank 1). For example, SRAM can be used as these memories.
The CPU 200 outputs a signal for writing or reading data to or from the memories 400 and 500 to the internal bus.

The memory control circuit 300 is connected to an address bus for selectively designating bank addresses and a data bus for data transfer from an internal bus.
The memory control circuit 300 receives from the internal bus a select signal indicating access to the memory, a status signal indicating whether the internal bus is active, and a system clock CLK for operating the memory control circuit 300. .
Then, based on an instruction from the CPU 200, the memory control circuit 300 sends an address signal ADDR, a DATA signal, a chip select signal nCS 0 for the bank 0, a chip select signal nCS 1 for the bank 1 to the externally connected memories 400, 500. Low byte select signal nLB, read signal nRD, and nWR / nWRL and nHB / nWRH signals are input / output to perform write or read access.

  Note that nWR / nWRL is used for both nWR and nWRL terminals, and is switched depending on the type of memory to be connected. The write signal nWR is a signal for performing writing, and the write raw byte signal nWRL is a signal for performing writing and indicates that the lower side of the data bus is valid. The nWR / nWRL terminal is switched to nWR when the memory to be accessed is a 16-bit memory, and to nWRL when the memory to be accessed is an 8-bit memory.

  The memory 400 (bank 0) corresponds to the output of the memory control circuit 300, a terminal for inputting an address signal ADDR, a chip select signal nCS0, a read signal nRD, a low byte select signal nLB, an nHB signal, and an nWR signal, and DATA A terminal for inputting and outputting signals is provided.

  On the other hand, the memory 500 (bank 1) inputs / outputs a terminal for inputting an address signal ADDR, a chip select signal nCS1, a read signal nRD, an nWRH signal, an nWRL signal, and a DATA signal corresponding to the output of the memory control circuit 300. It has a terminal to do.

  The memory control circuit 300 includes a register access circuit 10, registers ("setting circuit") 20, 21, state control circuits ("control circuit") 30, 31, an external interface circuit 40, a memory access detection circuit 50, an access determination. A circuit 60 is provided. All the circuits described above operate in synchronization with the clock CLK input from the internal bus.

The register access circuit 10 determines a signal for accessing the register among the signals input from the internal bus, and outputs the signal to the corresponding register group 20 or 21.
The register group 20 includes registers 70, 71, 72, 73, 74, and 75.
The register 71 is set with a value corresponding to a period tacs from the designation of the address of the memory to be accessed until the memory is activated.
The register 72 is set with a value corresponding to a period tcos from the activation of the memory to the start of reading.
The register 73 is set with a value corresponding to a period tacc for executing writing or reading of the memory.
The register 74 is set with a value corresponding to a period tcoh from the end of writing or reading until the memory becomes inactive.
The register 75 is set with a value for switching the terminal setting depending on the type of memory connected to the outside. For example, the terminal of nHB / nWRH is switched to nHB or nWRH by an input from the CPU 200 indicating whether the memory to be accessed is 8 bits or 16 bits.
The register 70 is set to a value corresponding to a period (“period in which both banks are deactivated”) added when consecutive accesses are performed in a plurality of different banks.
The values of these registers 70 to 75 are set by the CPU 200.

  The register group 21 is configured in the same manner as the register group 20. The memory control circuit 300 includes the same number of register groups 20 and 21 as the number of banks.

Based on the value set in the register group 20, the Valid output from the memory access detection circuit 50, and the output of the access determination circuit 60, the state control circuit 30 generates signals IDLE and TACS indicating the access state to the memory. , TCOS, TACC, and TCOH outputs are controlled.
In order to perform this control, the state control circuit 30 includes an ACS counter, a COS counter, an ACC counter, and a COH counter that down-counts the values of the registers 71, 72, 73, and 74 of the register group 20, respectively. Then, the state control circuit 30 counts down from the values set in the registers 70 to 75 in synchronization with the clock CLK, and sets the period until the register value becomes “0” as TACS, TCOS, TACC, and TCOH, respectively. Outputs a signal to set the state. The state of the signal output from the external interface circuit 40 is controlled by this signal.
The state control circuit 31 is configured in the same manner as the state control circuit 30. In this embodiment, the state control circuits 30 and 31 are provided corresponding to the register groups 20 and 21, but the number of the state control circuits 30 and 31 may be one. For example, each value may be input to the state control circuit 30 from the register groups 20 and 21 so as to be switched as appropriate.

  The memory access detection circuit 50 is a circuit that detects that an external memory is accessed from the internal bus, and receives a select signal that indicates that the memory is accessed from the internal bus, and is valid that indicates that the external memory is accessed. ("Second signal") is output.

The access determination circuit 60 determines an access method to an external memory based on the address bus, Valid, and a status signal indicating whether the internal bus is active, and outputs the result to the status control circuit 30.
For example, when the address bus designates the addresses of a plurality of banks and the valid of the corresponding banks is continuously “HIGH”, the ACS counter counts down the added value corresponding to tacs and talent.

  The external interface circuit 40 has an address signal ADDR, a DATA signal, the timing of input and output to the memory being controlled according to the transfer contents of the address bus and data bus, the set value of the register 75, and the output of the state control circuit 30. Chip select signals nCS0 and nCS1, low byte select signal nLB, read signal nRD, nWR / nWRL signal, and nHB / nWRH signal are output.

  For example, the chip select signal nCS becomes “HIGH” when the state control circuit 30 outputs an IDLE or TACS signal, and becomes “LOW” otherwise. The read signal nRD is “HIGH” when the state control circuit 30 outputs IDLE, TACS, TCOS, and TCOH signals, and “LOW” when the TACC signal is output. NWR / nWRL and nHB / nWRH are switched by a register 75 in the register group 20 indicating whether the memory to be accessed is 16 bits or 8 bits.

=== Change in Output of State Control Circuit 30 ===
FIG. 2 is a diagram for explaining a state change of the state control circuit 30 in the memory control circuit 300 according to the embodiment of the present invention. When the external memory 400 or 500 is not accessed, the state control circuit 30 has a valid signal “LOW” and outputs a state signal for setting the memory to the IDLE state. The state signal changes from this IDLE in the order of TACS → TCOS → TACC → TCOH as described above.

  In FIG. 2, when Valid is “LOW”, that is, a signal indicating that the memory is not accessed is input from the memory access detection circuit 50, the output of the state control circuit 30 is any of TACS, TCOS, TACC, and TCOH. Even if it is a state signal, the output of the state control circuit 30 changes to an IDLE state signal. In the following description, it is assumed that Valid is “HIGH”.

  Further, each counter = 1 in FIG. 2 indicates that one cycle of the clock CLK is counted down. The down count is assumed to be a fixed multiple CLK that is an integral multiple of the clock CLK. For example, in the case of tacs, a register value corresponding to one cycle of the clock CLK is set in the register 71, and down-counting is performed by a counter corresponding to the register. Then, it changes to the next state at the timing when the register value becomes “0”.

When the register 71, the register 72, and the register 74 are 0, the down count is not performed and the state is changed to the next state.
Note that, as described above, the register 73 during the period of writing or reading is set to a value other than 0, and the TACC is not passed.

<When accessing the same bank or non-contiguous memory>
First, in a state where the state signal is IDLE, when the Valid becomes “HIGH”, access to the memory designated by the CPU is started. The state control circuit 30 outputs TACS as a state signal when tacs ≠ 0. When tacs = 0 and tcos ≠ 0, TCOS is output. When tacs = 0 and tcos = 0, TACC is output.

  When the state signal changes to TACS, the value of the register 71 is taken into the ACS counter corresponding to this state in the state control circuit 30 and counting is performed. When the ACS counter finishes counting down one cycle of the clock CLK, the state control circuit 30 outputs TCOS as a state signal when tcos ≠ 0, and outputs TACC when tcos = 0.

  When the state signal changes to TCOS, the value of the register 72 is taken into the COS counter corresponding to this state in the state control circuit 30, and counting is performed. When the COS counter finishes counting down one cycle of the clock CLK, the state control circuit 30 outputs TACC.

  When the state signal changes to TACC, the value of the register 73 is taken into the ACC counter corresponding to this state in the state control circuit 30, and counting is performed. When the count down of one cycle of the clock CLK is completed by the ACC counter, the state control circuit 30 outputs TCOH as a state signal when tcoh ≠ 0, and when tcos = 0, Valid becomes “LOW” and IDLE is set. Output.

  When the state signal changes to TCOH, the value of the register 74 is taken into the COH counter corresponding to this state in the control circuit 30, and counting is performed. When the COH counter finishes counting down one cycle of the clock CLK, Valid becomes “LOW” and the state control circuit 30 outputs IDLE as a state signal.

<< When accessing different banks continuously >>
As shown in FIG. 2, when the state control circuit 30 of the present invention continuously accesses different banks, the state control circuit 30 sets the addition value of the register 70 and the register 71 as ACS by setting the state signal to change from IDLE to TACS. It is controlled by the access determination circuit 60 so as to be taken into the counter. The CPU 200 sets a value other than 0 as the addition value tacs + tare of the register 70 and the register 71. For example, a value longer than one clock period of the clock CLK is set. Therefore, even if tacs = 0 is set, the TACS state is not passed. Thereafter, changes are made as usual.
Note that the addition of “tare” is performed when accessing different banks continuously regardless of the value of “tacs”. Therefore, the value of “tacs” in the case of “tacs + teare” does not have to be zero.

=== Operation of Memory Control Circuit ===
FIG. 3 is a time chart for explaining the operation of the memory control circuit 300 according to the embodiment of the present invention in FIG. FIG. 3 shows an example in which the address A0 of the memory 400 (bank 1) is continuously accessed from the address A0 of the memory 400 (bank 0).

  It is assumed that register group 20 corresponds to bank 0 and register group 21 corresponds to bank 1. For high-speed access, the register group 20 is set to tacs0 = tcos0 = tcoh0 = 0, tacc0 = 3, and tara0 = 1, and the register group 21 is tacs1 = tcos1 = tcoh1 = 0, tacc1 = 3, and tara1 = 0 is set.

  For access to each bank, Valid and state signals for bank 0 are set to Valid0 and State0 signals, respectively, and Valid and state signals for bank1 are set to Valid1 and State1 signals, respectively.

First, <internal signal> will be described.
The address A0 of the bank 0 is specified from the CPU to the address bus during the period from t0 to t1, and then the address A1 of the bank 1 is specified during the period from t1 to t3.
By specifying the address A0 of the bank 0, Valid0 becomes “HIGH” at t0.
Valid0 becomes “LOW” after the same clock cycle as that in the period other than the IDLE period of the state 0 signal, that is, at t2.
When Valid0 is “HIGH”, the state 0 signal changes from IDLE to TACC at t1. In this example, since tacs0 = tcos0 = tcoh0 = 0, the state 0 signal changes in the order of IDLE → TACC → IDLE.
Further, the state 0 signal changes from TACC to IDLE at t3 when Valid0 becomes “LOW” at t2.

On the other hand, at t2, Valid0 changes to “LOW”, and at the same time, Valid1 corresponding to the designation of address A1 on the address bus becomes “HIGH”.
Valid1 becomes “LOW” after the same clock period as that of the period other than IDLE has passed in the state 1 signal, ie, at t5.
Since Valid1 is “HIGH”, the state 1 signal changes from IDLE at t3. In this case, since continuous access to different banks is performed, tacs1 + tare0 is set as a period in which the state 1 signal is TACS. The state 1 signal changes in the order of IDLE → TACS → TACC → IDLE.

As shown in FIG. 3, the state 1 signal changes from IDLE to TACS at t3, and changes to TACC at t4. The state 1 signal changes from TACC to IDLE at t6 in response to Valid1 changing to “LOW” at t5. Note that the state signal indicating whether the internal bus is active is sent to the address bus by an instruction from the CPU. A period is active. In this case, since the CPU continuously designates the address A0 and the address A1, the status signal indicates active continuously during this period.

Next, the signal of <terminal> will be described. All of these signals change based on the state signal.
First, at t1 when the state 0 signal changes to TACC, the address A0 designated by the CPU on the address bus is designated as the address signal ADDR.
At the same time, the chip select signal nCS0, the read signal nRD, the low byte select signal nLB, and the nHB / nWRH signal of the bank 0 become “LOW”, and the read access of the bank 0 is started.

Then, at t3 when the state 0 signal changes from TACC to IDLE and the state 1 signal changes from IDLE to TACS, the designation of the address signal ADDR is switched from the address A0 of the bank 0 to the address A1 of the bank 1. Further, the chip select signal nCS0 of the bank 0 becomes “HIGH”. Since the state 1 signal is in the TACS state, the chip select signal nCS1 of the bank 1 remains “HIGH” and becomes the read signal nRD “HIGH”.
Further, since the memory to be accessed is changed from the 16-bit memory to the 8-bit memory, the low byte select signals nLB and nHB / nWRH signals become “HIGH” at t3.
Data D0 stored at address A0 is read out to the DATA signal.
The read data signal D0 is output to the <internal signal> data bus.

Next, at t4 when the state 1 signal changes from TACS to TACC, the chip select signal nCS1 becomes “LOW”, and reading access to the bank 1 starts.
At time t6 when the state 1 signal changes from TACC to IDLE, the read signal nRD and the chip select signal nCS1 become “HIGH”, and the designation of the address A1 by the address signal ADDR is completed.
The data D1 stored at the address A1 is read to the DATA signal.
The read data D1 is output to the data bus of <internal signal>.

  As described above, in the case of continuous access to different banks, by adding “tare” as the setting of the TACS of the state signal, it is possible to set a period in which both the chip select signals nCS0 and nCS1 are “HIGH”, and nHB / nWRH It is possible to prevent malfunction due to a delay in timing when the signal becomes “HIGH”.

=== Other Embodiments ===
FIG. 4 is a time chart for explaining the operation of the memory control circuit 300 according to another embodiment of the present invention.

  This time chart includes, for example, a cache memory (not shown) for temporarily storing data in the CPU 200 and a cache-dedicated bus (not shown), and the memory control circuit 300 accesses the cache memory. An example in which the internal bus includes a period in which it is IDLE is shown. As described above, when the cache memory is provided in the CPU and specific data that is repeatedly used is stored in the cache memory, the access time can be greatly shortened.

  FIG. 4 is different from the above-described embodiment in that the designation of address buses A0 and A1 is not continuous and there is no signal for designating an address from the CPU on the address bus from t1 to t2. The status signal also corresponds to the address bus, and is a bus IDLE with no signal on the internal bus from t1 to t2.

  However, the timing of change from “HIGH” to “LOW” of Valid0 of bank 0 and the timing of change from “LOW” to “HIGH” of Valid1 of bank 1 are both t2, and different banks are used for external memory. It becomes continuous access to.

In this way, even if the IDLE state exists during address designation in the internal bus, the timing of the fall of Valid0 and the rise of Valid1 are the same, depending on the set values of the register groups 20 and 21, and the address signal ADDR designated A0 is designated. Switching from A1 to A1 may be continuous.
Therefore, in this case as well, since the external memory is continuously accessed to different banks, the memory control circuit 300 adds “tare0” to tacs1 as the setting of the TACS period.

As described above, the chip select signals nCS0 and nCS1 are both set to “HIGH” by setting a value obtained by adding “tare” to “tacs” as a period in which the state signal is TACS when accessing different banks continuously. A period can be provided. Since both banks are “HIGH” during this period, it is possible to prevent malfunction due to signal delay, for example, delay in timing when the nHB / nWRH signal changes from “LOW” to “HIGH”. Although the case where tacs = 0 is described, even when tacs is not 0, when continuously accessing different banks, the signal is obtained by setting a value obtained by adding “tare” to “tacs” as a period in which the state signal is TACS. In addition, when tacs is 0, that is, when the address designation period and the bank activation period are simultaneous due to high-speed access, when activation of different banks is switched, Since the activation of the bank is switched simultaneously and malfunction is likely to occur, tacs = 0 It may be added to the tarea in the case. In this case, malfunction during high-speed access can be prevented.
By providing a register for setting the value of the “tare” corresponding to the bank to be accessed, it is possible to add a “tare” corresponding to each bank.

  In addition, since the value obtained by adding “tare” to “tacs” as a period in which the state signal is TACS is set to at least one clock period of the system clock CLK, switching between the activation periods of the bank 0 and the bank 1 is not continuous. Therefore, malfunction can be prevented.

  In the present invention, even if the bus IDLE period exists in the internal signal, when the access to the memory is continuous, it can be regarded as continuous access and the malfunction can be prevented by adding the period of the TACS state.

As mentioned above, although embodiment of this invention was described concretely based on the embodiment, it is not limited to this and can be variously changed in the range which does not deviate from the summary.
For example, the memories 400 and 500 do not have to have the configuration shown in FIG. Further, a memory other than SRAM, for example, a flash memory may be used.

It is a block diagram for demonstrating the memory control circuit which concerns on the form of this invention. It is a figure for demonstrating the state change of the control circuit in the memory control circuit which concerns on the form of this invention. 6 is a time chart for explaining the operation of the memory control circuit according to the embodiment of the present invention. It is a time chart for demonstrating operation | movement of the memory control circuit which concerns on other embodiment of this invention. It is a time chart for demonstrating operation | movement of the conventional memory control circuit. It is a time chart for demonstrating the problem of the conventional memory control circuit.

Explanation of symbols

10 Register access circuit
20, 21 registers
30, 31 State control circuit 40 External interface circuit
50 Memory access detection circuit
60 Access determination circuit
100 integrated circuits
200 CPU
300 Memory control circuit
400, 500 memory

Claims (5)

In a memory control circuit comprising a control circuit for controlling access to a memory having a plurality of banks,
An access determination circuit for determining an access method to the memory based on a first signal for selectively designating addresses of the plurality of banks and a second signal for selectively activating the plurality of banks. With
The access determination circuit includes:
When the activation of the plurality of banks is switched based on the determination result when the first signal designates the plurality of banks and the second signal indicates that the plurality of banks are continuously activated. The memory control circuit is characterized in that the control circuit is controlled so as to provide a period for deactivating all of the plurality of banks. The control circuit includes:
Each of the plurality of banks is activated for a predetermined period;
When switching the activation of the plurality of banks, immediately after the predetermined bank is activated for a predetermined period, a period for deactivating both the bank and the bank to be activated next is provided. 2. The memory control circuit according to claim 1, wherein after the elapse of time, the bank to be activated next is activated for a predetermined period from deactivation. A plurality of setting circuits corresponding to the plurality of banks for setting a period for inactivating both of the plurality of banks;
3. The control circuit according to claim 1, wherein a period for inactivating both of the plurality of banks is provided when the plurality of banks are activated based on setting values of the plurality of setting circuits. The memory control circuit according to 1.   4. The memory according to claim 1, wherein the period during which the plurality of banks are inactivated is at least one clock period of a system clock for operating the memory control circuit. Control circuit. In a memory control circuit comprising a control circuit for controlling access to a memory having a plurality of banks,
A setting circuit for setting a period from address designation to activation for the plurality of banks;
When a value indicating that the address designation and activation for the plurality of banks is simultaneously set for the setting circuit,
The memory control circuit, wherein the access determination circuit controls the control circuit to provide a period during which the plurality of banks are deactivated when the activation of the plurality of banks is switched.

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