JPH05233446A - Cache storage device - Google Patents

Abstract

PURPOSE:To improve the data processing capacity by continuously performing writing operation. CONSTITUTION:When a write ON/OFF flag 1 indicates writing, namely, when the memory operation command in a last cycle is a write command, the contents of an address register 2 are supplied to a data memory 12. When the write ON/OFF flag 1 indicates another command, the address which is supplied in the current cycle is supplied to the data memory 12. Consequently, when write commands succeed, writing corresponding to the precedent command and hit decision making corresponding to the following command are carried out in parallel. Consequently, the successive write commands are processed without delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device interposed between a processor and a main memory device.

[0002]

2. Description of the Related Art As is well known, a method of providing a cache memory is known as a method for accelerating memory access from a processor 11 (Motooka, Ed.
First edition Asakura Shoten, 1983 p.122-p.124 “Cache memory”). FIG. 2 is a block diagram of an example of a conventional cache storage device. In the device having such a configuration,
FIG. 3 shows an example of the timing when a cache hit occurs.
And shown in FIG. In FIG. 2, the cache storage device 2
0 is provided between the processor 21 and a main storage device (not shown).

The cache storage device 20 includes a data memory 22, a cache tag memory 23, a comparator 24,
The cache control unit 25. The processor 21
The data in the main memory is processed by repeatedly reading and writing data in the main memory (not shown). The data memory 22 is a random access memory composed of storage elements that can be accessed at a higher speed than the main memory, and stores a part of the data in the main memory, that is, cache memory. Cache tag memory 23
Is a memory for storing the address on the main memory of the data stored in the cache.

The comparator 24 compares the address output from the processor 11 with the address stored in the cache tag memory 13. The cache control unit 25 accesses the data from the data memory 22 or sends a response signal Hold for the processor 21 to directly access the data on the main memory based on the comparison result of the comparator 24. In FIG. 2, MOC means a memory operation command. This command instructs the processor 21 whether to read or write to the memory. Hold is a signal for notifying the processor from the memory when the memory access cannot be completed within a predetermined time (for example, when a cache miss), and causes the processor to wait (“CY7C600 RISC FAMILY U”).
SERS GUIDE '' Cypress Semiconductor Corporation, 1988
See p.9-7 to p.9-8). Next, the operation of the above-mentioned device will be described.

FIG. 3 is a time chart for explaining the read timing. Processor 2 for reading
At the same time when the cache is read with the lower bit of the address Adr output from 1, the cache hit determination is performed (FIGS. 3A, 3B, and 3C). In this cache hit judgment,
Cache tag memory 2 with lower bit of address Adr
3 is read out, and its contents are compared with the upper bits of the address Adr. If the contents of the cache tag are valid and match the address Adr, there is a cache hit (FIG. 3 (d)), and the contents of the data memory 22 are passed to the processor 21 (FIG. 3 (e)).

FIG. 4 is a time chart for explaining the write timing. In the case of writing, cache hit determination is performed in the first cycle (FIGS. 4 (a), (b), (c)).
If it is a cache hit, the data output from the processor 21 is written to the data memory 22 in the next cycle (FIGS. 4 (d), (e), (f)). In case of cache miss, Hol
The d signal is output and data is transferred to and from a main memory device (not shown), but details thereof will be omitted.

[0007]

However, the above-mentioned conventional techniques have the following problems. That is, in the case of writing, hit judgment is performed in the first cycle,
Since writing is performed in the second cycle, it is necessary to save the address for two cycles (Fig. 4 (b)). Therefore, the processor 21 is subject to the limitation that it cannot issue a write command to another address in the next cycle after writing (FIG. 4 (c)). In particular, RISC (Reduced I) that executes one instruction in one cycle
nstruction Set Computer) type processor, if you want to execute write command continuously, N
Whether to insert an OP (no operation) command (Fig. 4 (c)),
A mechanism to hold the subsequent write command must be added. In any case, one instruction cannot be executed substantially in one cycle, and the data processing capability is reduced.

The present invention has been made in view of the above points, and provides a cache memory device which can perform subsequent write operations without delay even in the cycle next to the write operation if a cache hit occurs. The purpose is.

[0009]

A cache storage device of the present invention includes a data memory for storing a part of data on a main memory accessed by a processor and a cycle immediately before the current cycle of the cycles in which the processor operates. Write cycle presence / absence flag for storing whether or not there is a write request, an address register for holding an address given in the cycle immediately preceding the processor, and the write presence / absence flag when an address is given to the data memory. When the write request is shown, the contents of the address register are selected and given, while when the write presence / absence flag shows that there is no write request, the address given in the current cycle Is provided with an address selecting means for selecting and giving That.

[0010]

In the cache memory device of the present invention, the content of the address register is given to the data memory when the write presence / absence flag indicates write, that is, when the memory operation command of the immediately preceding cycle is write. On the other hand, when the write presence / absence flag indicates other than write, the address given in the current cycle is given to the data memory. As a result, when the write commands are consecutive, the write corresponding to the preceding command and the hit determination corresponding to the subsequent command are performed in parallel. As a result, consecutive write commands are processed without delay.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a cache storage device of the present invention. In this figure, only the necessary parts at the time of a cache hit are described, and some of the routes used at the time of a cache miss are omitted. In the figure, a cache storage device 10 is a processor 11
And a main storage device (not shown). The cache storage device 10 includes a data memory 12, a cache tag memory 13, a comparator 14, and a cache control unit 15.

The processor 11 repeats reading and writing of data in a main memory device (not shown) to process the data in the main memory device. Data memory 1
Reference numeral 2 is a random access memory composed of storage elements that can be accessed at a higher speed than the main memory, and stores a part of data in the main memory, that is, cache memory. The cache tag memory 13 is a memory that stores an address on the main memory of data stored in the cache.

The comparator 14 compares the address output from the processor 11 with the address stored in the cache tag memory 13. The cache control unit 15 accesses the data from the data memory 12 or sends the response signal Hold for the processor 11 to directly access the data in the main memory based on the comparison result of the comparator 14.

Further, the cache storage device 10 is provided with a write presence / absence flag 1, an address register 2, and an address selecting means 3, which are the features of the present invention. The write presence / absence flag (PREV_WR) 1 is a flag for storing that the memory operation in the immediately preceding cycle of the processor 11 was a write. The address register (PREV_ADR) 2 is a register that holds the address given in the immediately preceding cycle. The address selection means (AdrSel) 3 is a selector for selecting an address to be given to the data memory 12 from an address given in the current cycle or an address given in the immediately preceding cycle.

The input / output of the processor 11 is as follows. Adr is an address on the main memory (not shown) output from the processor 11. M
In the OC, the processor 11 is the main memory or the data memory 12
Is a memory operation command for instructing whether to read or write. When the memory access cannot be completed within a predetermined time (for example, a cache miss), Hold notifies the processor 11 from the cache controller 15 of the fact, and the processor 11
This is a signal to make the user wait. Data is a bus that transfers data between the processor 11 and the data memory 12.

Next, the operation of the above-mentioned device will be described. In FIG. 1, the cache storage device 10 receives the address Adr and the memory operation command MO from the processor 11.
C is received and the operation corresponding to the memory operation command of the immediately preceding cycle and the current cycle is performed. To determine whether or not a cache hit occurs in the cache memory device 10, first, the address Adr
The cache tag memory 13 is read by the lower bit of
Check if the contents are valid. At the same time, the comparator 14 compares the contents with the upper bits of the address Adr. Content is valid and this content is address Adr
If it matches with the high-order bit of, it is a cache hit. Whether the contents of the cache tag memory are valid can be realized by providing a valid flag for each word of the cache tag memory and checking it.

In the case of a cache miss, the Hold signal is output and data is transferred to and from the main memory, but the details are omitted since they are not directly related to the description of the present invention. The case of a cache hit will be described below with reference to the time charts of FIGS. 5 and 6.

FIG. 5 is a time chart for explaining the read and write timings. This figure shows the timing when there is no continuous memory operation command in the write command write, that is, when the commands specified in the cycles immediately before and after the write command write are no operations nop. Clock CLOCK in the figure
Is a clock input to the processor 11, the write presence / absence flag 1, and the address register 2 (FIG. 5A).

As shown in the figure, it is assumed that a read command is given by the address Adr = A1 (FIG. 5 (b)) from the processor 11 and the output of the memory operation command MOC = read (FIG. 5 (c)). At this time, Adr = A0 of the immediately preceding cycle is set in the address register 2 (FIG. 5 (d)), and the write presence / absence flag 1 is reset (FIG. 5 (e)). As a result, A1 is given to the cache tag memory 13 and a hit determination is made. At the same time, as the address DMadr, the address selection unit 3 selects the address Adr, that is, the address A1 output from the processor 11 in the current cycle,
It is given to the data memory 12 (FIG. 5 (f)). At the end of this cycle, the content D1 read from the data memory 12 is passed to the processor 11 (FIG. 5 (h)).

Next, it is assumed that Adr = A2 (FIG. 5B) and the write command write are given from the processor 11 in the cycle next to the above-described cycle (FIG. 5C). As in the case described above, Adr of the immediately preceding cycle is set in the address register 2 (see FIG. 5).
(d)), the write presence / absence flag 1 is reset (FIG. 5 (e)). A2 is given to the cache tag memory 13 to make a hit determination. In the example shown, as a result,
At the same time, the address selection means 3 selects Adr, that is, the address A2 output from the processor 11 in the current cycle and supplies it to the data memory 12 (FIG. 5 (f)). Will not be accessed. If there is a cache hit, the write presence flag 1 is set (FIG. 5 (e)).

In the next cycle, it is assumed that the non-operation nop is given as the memory operation command MOC (FIG. 5).
(c)). Since the write presence / absence flag 1 has been set (FIG. 5 (e)), the address selection means 3 uses the address register 2
, That is, the address A2 (FIG. 5 (d)) output from the processor 11 in the immediately preceding cycle is selected and given to the data memory 12 (FIG. 5 (f)). Also, the write signal CW
C is sent to the data memory 12 (FIG. 5 (g)), and the data D2 output to Data is written (FIG. 5 (h)).
After this, the write presence / absence flag 1 is reset (see FIG. 5).
(e)).

FIG. 6 is a time chart for explaining the timing when writing is continued. The clock CLOCK in the figure is the processor 11 and the write presence / absence flag 1
And a clock input to the address register 2 (FIG. 6 (a)). As shown, processor 11 to Adr
= A1 (FIG. 6 (b)) and the write command write is given through the memory operation command MOC (FIG. 6 (c)). At this time, Adr = A0 of the immediately preceding cycle is set in the address register 2 (see FIG. 6).
(d)), the write presence / absence flag 1 is reset (FIG. 6 (e)). A1 is given to the cache tag memory 13 to make a hit determination. The data memory 12 operates in the same manner as in FIG. If there is a cache hit, the write presence flag 1 is set (FIG. 6 (e)).

In the next cycle, the processor 11 sends an Ad
r = A2 (FIG. 6 (b)), and write command write
Is given (FIG. 6 (c)). In the address register 2, Adr = A1 in the immediately preceding cycle is set (FIG. 6 (d)), and the write presence / absence flag 1 is set (FIG. 6 (e)). A2 is given to the cache tag memory 13 to make a hit determination. At the same time, the contents of the address register 2 (see FIG.
(b)), that is, the address A1 output from the processor 11 in the immediately preceding cycle is selected and given to the data memory 12. Further, the write signal CWC is sent to the data memory 12 (FIG. 6 (g)), and the data D1 is written at the address A1 (FIG. 6 (h)). Here, the write presence / absence flag 1 is set (FIG. 6 (e)). As described above, the hit determination of the address A2 (FIG. 6B) and the writing to the address A1 (FIGS. 6D and 6H) are performed in parallel. This is performed as long as the write command write continues.

As described above, the write presence / absence flag 1
Indicates write, that is, the memory operation command MOC of the immediately preceding cycle is the write command write.
When it is e, the contents of the address register 2 are given to the data memory 12. As a result, the write command wri
When te continues, the preceding write command writ
write corresponding to e and subsequent write command wri
Hit determination corresponding to te is performed in parallel. As a result, continuous write commands “write” are processed with almost one cycle per command without delay. On the other hand, when the writing presence / absence flag 1 indicates other than writing, the address given in the current cycle is given to the data memory 12. As a result, the data present at the address Adr currently requested by the processor 11 is read.

If the read command read is given immediately after the write command write, access to the data memory 12 conflicts with this configuration. Therefore, such a combination is prohibited or means for making the read command read wait. I have to add.

[0026]

As described above, according to the cache memory device of the present invention, the write presence / absence flag for storing the fact that the memory operation command in the immediately previous cycle was a write, and the address given in the immediately previous cycle. Since it is provided with an address register for holding and an address selection means for selecting an address to be given to a data memory for storing data as a cache memory, if a cache hit occurs, a write operation is performed even in the cycle next to the write operation. Operations can be performed without delay. Therefore, even when the write instruction is continuously executed by the processor that executes one instruction in one cycle, the execution of the instruction is not kept waiting, and as a result, the performance of data processing can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a cache storage device of the present invention.

FIG. 2 is a block diagram of an example of a conventional cache storage device.

FIG. 3 is a time chart illustrating a read timing.

FIG. 4 is a time chart illustrating write timing.

FIG. 5 is a time chart explaining read and write timings.

FIG. 6 is a time chart explaining a timing when writing is continued.

[Explanation of symbols]

 1 Write Presence / Absence Flag 2 Address Register 3 Address Selector 10 Cache Storage Device 11 Processor 12 Data Memory 13 Cache Tag Memory 14 Comparator 15 Cache Control Unit

Claims (1)

[Claims] 1. A data memory for storing a part of data in a main memory accessed by a processor, and a memory for storing whether or not a write request is made in a cycle immediately before a current cycle among cycles in which the processor operates. A write presence / absence flag, an address register that holds an address given in the immediately preceding cycle of the processor, and a case where the write presence / absence flag indicates that there is a write request when the address is given to the data memory, Address selecting means for selecting and giving the address given in the current cycle when the write presence / absence flag indicates that there is no write request. A cache storage device characterized by the above.