JPH0553908A - High-speed access storage device - Google Patents

Abstract

PURPOSE:To reduce average memory access time in the case of a processing to access the wide data area of image data or the like. CONSTITUTION:This device is equipped with (n) [(n) >=2] data memories to execute parallel operations and a memory access controller 2 to control parallel read/write to those data memories while receiving a memory access request from a CPU. The memory access controller 2, is formed as an address predicting circuit 4 to predict the next memory read access request address from the CPU, to previously read the data of the plural predicted addresses from the memory, to store the addresses in a read buffer 6, to compare memory read access request addresses from the CPU with these stored predicted addresses, to output the data of the coincident predicted address to the CPU and to read the data of the address from the memory only when the address is not coincident.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to high speed access storage devices.

[0002]

2. Description of the Related Art A high-speed memory that enables high-speed access from a general-purpose CPU has a drawback that it has a small capacity and is expensive. Therefore, conventionally, a memory system with a cache memory is used as a high-speed access storage device. The cache memory is a semiconductor high-speed memory that is installed between the CPU and main memory, and is a part of the program (for example, 8 kilobytes) when the program is executed.
Are read into this memory, where instructions are executed at high speed.

By using this cache memory system, when referring to certain data from the CPU, a data block containing the data is copied to the cache memory, and data access is performed on the cache memory to realize high-speed access. It becomes possible to do.

[0004]

Conventionally, since the capacity of the cache memory used in the cache memory system is small, the amount of data that can be copied onto the cache memory at one time is small.

Therefore, in the case of a process in which there are many local data accesses, the ratio of accessing the data in the data block in the cache memory becomes relatively large, and the average data access time becomes short.

However, in the case of processing for accessing a wide data area such as image data, the ratio of data access on the cache memory becomes small, and even if the cache memory is used, the average data access time cannot be shortened. Can not. It is an object of the present invention to provide a device capable of high speed access even in the case of a process of accessing a large data area.

[0007]

SUMMARY OF THE INVENTION A high speed access storage device of the present invention receives n (n ≧ 2) data memories which execute parallel operations and data access requests from the CPU to these data memories. A memory access controller for controlling parallel read / write is provided. The memory access controller predicts the next data read access request address from the CPU, prefetches and holds the data, and a memory from the CPU. The read access request address is compared with these stored predicted addresses, and the data of the matching predicted address is C
It is provided with a means for outputting to the PU and reading the data of the address from the memory only when they do not match. When a data write access request is issued from the CPU, a speedup is achieved by providing a means for returning a write completion signal when the address to be written is received and then executing the write.

[0008]

The memory access controller configured as described above receives a memory access request from the CPU for n (n ≧ 2) data memories that execute parallel operation, and performs parallel read / write as follows. Take control.

At the time of memory read, the address of a plurality of memory read accesses thereafter is predicted from the address in the previous memory read access from the CPU, and the data at that address is prefetched and held. If the predicted addresses for a plurality of memory read accesses are in different data memories 1i (i = 1, 2, ..., K), prefetching can be executed in parallel in a plurality of memories. When the CPU actually makes a memory read access, the address of the actual memory read access is compared with the prefetched address, and if they match, the data of the prefetched address is returned to the CPU. As a result, parallel data access can be realized for continuous data access, and the average access time can be shortened.

At the time of memory write, a memory write access request from the CPU is received, a write completion signal is returned to the CPU when the address to be written is received, and then the write is executed. Even when there are consecutive memory write requests, the data memories 1i (i = 1, 2, ..., K) whose write addresses are different from each other
With, writes can be performed in parallel on multiple memories. Therefore, if the data address is determined so as to sequentially write to a plurality of data memories, parallel data access can be realized and the average access time can be shortened.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention. In the figure, k memory access controllers 2i (i = 1, 2, ..., K) are connected in parallel to the address data bus 9 to which the CPU 10 is connected, and each memory access controller 2i (i =
1, 2, ..., K) has data memories 1i (i = 1, 1).
2, ..., K) are connected.

FIG. 2 is a block diagram of the inside of the memory access controller 2i (i = 1, 2, ..., K) according to the present invention. The address check circuit 3, the address prediction circuit 4, the write buffer 5, and the read buffer 6 are shown. , Gate 7
a to 7d and a gate controller 8. The address check circuit 3 checks whether the address received by the memory access controller 2i from the CPU is assigned to the connected data memory. The address prediction circuit 4 predicts a plurality of addresses from the addresses in the previous memory read access, reads the data from the data memory 1i and stores the data in the read buffer 6, and the predicted memory access address and the address check circuit 3 The actual memory read request address input from is compared.

The memory read / write signals and addresses transmitted from the CPU 10 via the address data bus 9 are stored in the memory access controller 2i (i = 1, 2,
..., k). The address check circuit 3 in each memory access controller 2i uses the data memory 1 to which the memory read / write address is connected.
Whether the address is assigned to i is checked, and if it is assigned, it is checked whether it is a memory read signal or a memory write signal.

If it is a memory write signal, the address check circuit 3 checks whether or not there is data in the write buffer 5. If there is no data in the write buffer 5, the gate 7a is opened and the data (to be written) from the CPU 10 is put in the write buffer 5. At the time when the gate 7a is opened, the address check circuit 3 returns a memory write completion signal to the CPU 10, and then gives the memory write address to the write buffer 5. Gate controller 8
Opens the gate 7c and executes the write from the write buffer 5 to the data memory 1i. When the data already exists in the write buffer 5, it is determined that the memory is being written (by the memory write signal before that), and the wait is performed.

If it is a memory read signal, the address check circuit 3 sends the memory read address from the CPU 10 to the address prediction circuit 4. In the address prediction circuit 4, a plurality of addresses are predicted from the previous address value before the memory read signal is generated, and the gate controller 8 opens the gate 7d on the basis of the predicted addresses to read the data at the predicted addresses in the read buffer. Fetch in 6

In the address prediction circuit 4, the CPU 1
The memory read request address from 0 is compared with the predicted address, and if there is a match, the data in the match address stored in the read buffer 6 is
The gate 7b is opened and sent to the CPU 10. If there is no matching address, the gate controller 8 determines the gate 7d.
Is opened, the data of the memory read address received from the CPU 10 is read from the data memory 1i, fetched into the read buffer 6, and then sent to the CPU 10.

After sending the data to the CPU 10 in this way, the address prediction circuit 4 predicts the next memory read address, fetches the data in that address, and stores it in the read buffer 6. Next, a specific access example according to the present invention will be shown.

An example of reading / writing k × n array data d (i, j) will be described. d (1,1), d (2,
1), ..., D (k-1, n), d (k, n) are accessed in this order.

It is assumed that d (i, j) (j = 1, 2, ..., N) is stored in the data memory 1i. Now, the time required for writing from the write buffer 5 to the data memory 1i is t
w, the time until the address check circuit 3 checks the address and gives the address to the write buffer 5 is ta
And At this time, if ta <tw / k, all k data memories 1i execute write in parallel, and all data are written (ta + t
w) × (n + 1) or less.

Next, k written in the data memory 1i
Xn array data d (i, j) is converted into d (1,1), d
(2, 1), ..., D (k-1, n), and d (k, n) are read in this order.

In the case of reading, the address prediction is performed by the difference between the addresses. At this time, the time required until the first predicted address is obtained by all the memory access controllers 2i is (ta + tw) × k × 2, and after that, by the same parallel operation as in the case of writing, (ta + t)
All reads are completed in a time of w) × (n−1) or less.

[0023]

As described above in detail, according to the present invention,
Means for predicting the next memory read access request address from the CPU, prefetching and holding the data, and the CPU
When a memory write access request is issued from the device, a write completion signal is returned when the address to be written is received, and a means for executing the write after that is provided to access a wide-area data area such as image data. Also in the case of processing, the average memory access time can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a high speed access storage device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing details of a memory access controller in the embodiment.

[Explanation of symbols]

1 ... data memory, 2 ... memory access controller,
3 ... Address check circuit, 4 ... Address prediction circuit, 5
... write buffer, 6 ... read buffer, 7 ... gate,
8 ... Gate controller, 10 ... CPU.

Claims (1)

[Claims] 1. An n (n ≧ 2) number of data memories that execute parallel operations, and a memory access controller that controls the parallel read / write in response to a memory access request from the CPU for these data memories. The memory access controller includes means for predicting a next memory read access request address from the CPU, preliminarily reading and storing data of a plurality of predicted addresses from the memory, and a memory read access request address from the CPU. , Comparing these stored predicted addresses and causing the CPU to output the data of the matching predicted address,
A high-speed access storage device comprising means for reading the data of the address from the memory only when they do not match.