JPH06139347A - Picture arithmetic processor - Google Patents

Abstract

PURPOSE:To perform the picture arithmetic processing at a high speed with a simple configuration. CONSTITUTION:Setters 31 and 32 (Max value register and a Min value register) which set the address range of a picture memory 2 based on the indication from a central processing unit CPU 1, a mode setter 33 (mode setting register) which sets the processing mode indicating the picture operation processing to be executed based on the instruction by the CPU 1, comparators 34 and 35 which compare the access address of the CPU 1 with contents of setters 31 and 32, logic circuits 36 and 37 which output a read signal R to the memory 2 as a data latch signal D in the case of setting of a prescribed picture arithmetic processing and the access address of the CPU 1 within the set range of setters 31 and 32, etc., are provided, and data read out from the memory 2 is directly taken into a projection operation processing part 38 based on this signal D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image calculation processing device, such as an optical character recognition device (OCR), which performs image calculation processing including image projection calculation, enlargement / reduction calculation or local rotation calculation.

[0002]

2. Description of the Related Art Conventionally, when passing necessary data to, for example, an image processing unit (also called a projection LSI) that performs an image projection process, a central processing unit (also called a CPU) once transfers data from a data storage memory (image memory). 2 to read the data and write the data from the CPU to the image processing device
Generally, it is realized by a step operation. In addition, DMA (Direct Mem)
There is also a method of implementing it by using hardware for ory access).

[0003]

However, in the former method, in order to process one data, the CPU reads the data from the image memory. The read data is written from the CPU to the projection LSI. Therefore, there is a problem that the data access time is doubled. In other words, when the amount of data to be handled is extremely large, as in image processing, the faster the data access time, the higher the processing speed. It will be late.
On the other hand, the latter method has a problem that not only complicated and expensive hardware for DMA is required, but also transfer efficiency deteriorates unless transfer data is continuous (addresses are continuous). Therefore, an object of the present invention is to enable high-speed image calculation processing without requiring complicated and expensive hardware.

[0004]

In order to solve such a problem, the present invention operates in parallel with a central processing unit (CPU) that performs a predetermined process based on data from a memory, and performs an image projection operation. , CP for executing image calculation processing including enlargement / reduction calculation or local rotation calculation
An address setter for setting a range of memory addresses based on an instruction from U, a mode setter for setting a processing mode of what image arithmetic processing is to be performed based on an instruction from the CPU, and an address accessed by the CPU as the address. A comparator for comparing with the contents of the setter, and a logic circuit for converting a read signal for the memory into a data latch signal when the access address of the CPU is within a set range of the address setter in a predetermined image operation processing mode. Is provided, and the data read from the memory based on the data latch signal can be directly fetched.

[0005]

By allowing the CPU to read (read out) data from the memory and simultaneously latch (store or take in) the data directly to the image processing unit, the operation of transferring the data from the CPU to the image processing unit becomes unnecessary. ,
Enables high-speed image calculation processing.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention,
FIG. 2 is a flow chart for explaining the operation of the CPU of FIG. As is apparent from FIG. 1, the present invention is provided with an image arithmetic processing unit (projection LSI) 3 including, for example, registers 31 to 33, comparators 34 and 35, NAND gate 36, OR gate 37, and projection arithmetic processing unit 38. The feature is the point, and the others are the same as the conventional one. In addition, the code 1 is C
PU, 2 is a memory (image memory), 4 is a data bus, 5
Is an address bus, R is a read signal, W is a write signal, D
Indicate data latch signals, respectively.

The CPU 31 sets the maximum (Max) value of the address of the memory 2 in the register 31, and the register 32
Is the minimum address (Min) from CPU 1 to memory 2.
A value is set, and data indicating whether or not the projection processing mode is set is set in the register 33 by the CPU 1. Comparator 3
Reference numerals 4 and 35 compare the set values of the setters 31 and 32 with the address (adr) of the memory 2 output from the CPU 1,
The comparator 34 outputs a high level (H) signal when adr ≦ Max, and the comparator 35 outputs a high level (H) signal when adr ≧ Min. The NAND gate 36 becomes low level (L) only when the outputs of the comparators 34 and 35 and the register 33 are high. The OR gate 37 reads the read signal R only when the output of the NAND gate 36 is L.
Is converted into a data latch signal D (validated).

The operation will be described with reference to FIG. That is, the CPU 1 first sets the address Max value and the address Min value, as shown in steps S1 to S3 of FIG.
And mode setting (set to “H” when performing projection calculation). The setting is performed using the write signal W. Then, as shown in step S4, the CPU 1 designates a predetermined address to specify the image memory 2
Of data in a certain range of
The I3 comparators 34 and 35 determine whether or not the address is within a preset range, and output an H signal if within the range.

Therefore, the NAND gate 36 is connected to the comparator 3
4, 35 and register 33 become L only when all outputs are H, and OR gate 37 validates read signal R only when the output of NAND gate 36 is L, receives this as data latch signal D, and receives data bus 4 The data from the memory 2 via the projection arithmetic processing unit 38 can be latched. After that, the CPU 1 determines whether or not the target processing (projection calculation processing in this case) is completed, as in step S5 of FIG. 2, and if completed, the mode setting is canceled in step S6, and To prepare for the process.

FIG. 3 is an explanatory diagram for explaining the operation of the present invention in comparison with a conventional example. The figure (a) shows the conventional method,
This figure (b) is according to the present invention, and is a CPU 1
Indicates a route for reading data from the image memory 2, a route for writing the read data from the CPU 1 to the projection LSI 3, and a symbol 'indicates a route for the projection LSI 3 to take in data by itself. That is, in the prior art, a two-step operation is required as in (a), whereas in the present invention, the operation of'is performed in parallel with the operation of, so that one-step operation is performed. Will be enough. It should be noted that, although the projection calculation process has been mainly described above, it goes without saying that the present invention can be similarly applied to other image calculation processes such as enlargement / reduction and rotation.

[0011]

According to the present invention, the processing range on the memory is preset from the CPU, and the address is monitored on the image processing device side each time the CPU accesses the memory, which is a simple structure. Data can be directly captured. As a result, it is possible to execute the operation in one step, which conventionally requires a two-step operation in which the CPU reads data from the memory and then writes the data to the image processing apparatus, which shortens the processing time. The possible advantages will be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the CPU shown in FIG.

FIG. 3 is an explanatory diagram for explaining the present invention in comparison with a conventional example.

[Explanation of symbols]

1 ... Central processing unit (CPU), 2 ... Image memory, 3 ... Projection LSI, 4 ... Data bus, 5 ... Address bus, 31 ...
Max value register, 32 ... Min value register, 33 ... Mode setting register, 34, 35 ... Comparator, 36 ... NAND gate, 37 ... OR gate, 38 ... Projection calculation processing unit.

Claims (1)

[Claims] 1. A central processing unit (CPU), which performs a predetermined process based on data from a memory, operates in parallel,
An image calculation processing device for executing image calculation processing including image projection calculation, enlargement / reduction calculation or local rotation calculation, comprising: an address setter for setting a range of memory addresses based on an instruction from the CPU; , A mode setter for setting a processing mode of what kind of image calculation processing is to be performed, a comparator for comparing the address accessed by the CPU with the contents of the address setter, and a CPU for a predetermined image calculation processing mode. And a logic circuit for converting a read signal to the memory into a data latch signal when the access address of the memory is within the setting range of the address setter, and makes it possible to directly fetch the data read from the memory based on the data latch signal. An image calculation processing device characterized by: