KR100297562B1 - Hardware resorce recognition controller and method of control system for communication - Google Patents

Abstract

The present invention provides a communication control system using a built-in processor, a hardware resource recognition control apparatus of a communication control system for efficiently managing resource information by recognizing and controlling the change in hardware resources during power-on or during operation and The method relates to the initialization of the base register and the option registers that determine the internal registers, the memory area and the speed, etc. at the time of power-on reset, and then reads the value of the status control register from the value of the status control register. If the RS232 transceiver in the internal resource unit is enabled, enable the internal SMC transceiver, initialize the UART, and complete CPU initialization.If the RS232 transceiver is disabled, disable the internal SMC transceiver and then enable the external SMC. Then enable CPU initialization If the flash memory and DRAM module are enabled from the value of the status control register, read the status recognition register, initialize the CPU base register and option register to match the capacity and speed, initialize the UART, and then initialize the CPU. When the flash memory and the DRAM module is disabled, after initializing the appropriate base register and the option register in the external memory, and then initialize the UART, the CPU initialization is completed.

Description

Hardware resource recognition controller and method of control system for communication {Hardware resorce recognition controller and method of control system for communication}

The present invention provides a communication control system using a built-in processor, the hardware of the communication control system that can efficiently manage the resource information by recognizing and controlling the change in hardware resources during power-on or during operation A resource recognition control apparatus and method.

In the case of a communication control system incorporating a processor used in the related art, that is, a communication control system in which hardware resources should be changed when necessary, a software change according to the expansion of resources is required. Because they cannot be used for their purposes, they often lack scalability and do not efficiently use their hardware resources.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a communication control system using an embedded processor, which recognizes whether hardware resources change during power-on or during operation, so that hardware resources can be changed without additional software change. An object of the present invention is to provide a hardware resource recognition control apparatus and method for a communication control system capable of expanding and controlling a hardware to use a single resource for multiple purposes.

1 is a block diagram of a hardware resource recognition control apparatus of a control system for communication according to the present invention;

2 (a) to (e) are flowcharts showing the operation of the hardware resource recognition control apparatus of the communication control system according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: reset unit 20: processor unit

30: Registers and Control Unit 31: Hardware Reset Config Register

32: status recognition register 33: status control register

40: internal resource unit 41: DRAM module

42: flash memory 43: RS232 transceiver

50: external resource unit 51: external RS232 unit

52: external memory 61: first buffer

62: second buffer

Hardware resource recognition control apparatus and method of the control system for communication of the present invention to achieve the above object, after initializing the base register and the option register to determine the register and the memory area and the speed, etc. Reads the value of the status control register, and if the RS232 transceiver in the internal resource unit is enabled from the value of the status control register, enables the internal SMC transceiver, initializes the UART, and then completes CPU initialization, and the RS232 transceiver If is disabled, disable the internal SMC transceiver, enable the external SMC, and complete CPU initialization. If the flash memory and DRAM module are enabled, read the status recognition register from the value of the status control register. Base register of CPU to match speed Initialize the UART after initializing the memory and option registers, and then complete the CPU initialization.If the flash memory and DRAM module are disabled, initialize the UART after initializing the appropriate base registers and option registers in the external memory. Characterized in that the initialization is completed.

Hereinafter, the configuration and operation of a hardware resource recognition control apparatus of a communication control system according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a hardware resource recognition control apparatus of a control system for communication according to the present invention. The reset unit 10 generates a reset in the processor unit when the power is turned on and initializes the inside of the processor unit. And a built-in processor incorporating resources such as a memory controller and a serial communication controller. The processor is initialized according to the reset of the reset unit 10 and is an address bus and a data bus. Interface with other building blocks via control signals such as Data Bus, Hardware Reset and Chip Select (CS) and Read / Write (R / W) signals, and via SMC The processor unit 20 which interfaces with an external RS232 unit and an RS232 transceiver, and when the hardware reset is output from the processor unit 20, is input to the processor unit 20 through a data bus. Inputs the encoded information through the hardware reset config register 31, which stores the hardware reset config data, and the Presence Detect (PD) pin [1..3] of the DRAM module, and the PD pin [1..3] of the flash memory. Enable / disable the DRAM module, the flash memory, and the RS232 in the internal resource unit under the control of the processor 20 and the state recognition register 32 for inputting the decoded information to the processor 20. A register and control unit 30 including a state control register 33 for disabling control and performing a state recognition and control function of each resource, a DRAM module 41, a flash memory 42, and an RS232 transceiver 43. An internal resource unit 40 configured to provide status information to the register and the controller 30 and enable / disable operation under the control of the register and the controller 30, an external RS232 unit 51, and an external device. Me The external resource unit 50 configured to be used according to a control signal of the processor unit 20 when the internal resource is not used, and the state information of the flash memory 42 in the internal resource unit 40. Temporarily store state information of the first buffer 61 for outputting to the register and the state control register 33 in the control unit 30 and the DRAM module 41 in the internal resource unit 40. The register and the second buffer 62 output to the state control register 33 in the control unit 30.

In the hardware resource recognition control apparatus of the communication control system configured as described above, the CPU built in the processor unit 20 requires hardware reset config data (Hardware Reset Config Data) for the initial operation.

The register and the hardware reset config register 31 in the controller 30 can be read / write at any time in the processor unit 20, and the processor unit 20 defaults to reset the power-on reset. Read the value.

During hardware reset, the data in the hardware reset configuration register 31 is input to the processor unit 20 as hardware reset configuration data of the processor unit 20 via a data bus.

Whenever the hardware reset config data is to be changed, it can be written to the hardware reset config register 31 at which time the new value becomes valid when the hardware reset is activated.

The hardware reset config data stored in the hardware reset config register 31 may be initially known to the CPU in the processor unit 20 such as boot port information, internal interrupt area information, debug pin usage information, etc. of the CPU. Contains information.

The status acknowledgment register 32 can be read only at any time by the processor unit 20 and can be read at any time, and the capacity of the DRAM through the PD pin [1..3] of the DRAM module 41 in the internal resource unit 40, Speed and the like are provided to the processor unit 20 so as to receive the encoded information and to perform different initialization.

In addition, the processor 20 receives the capacity information decoded through the PD pin [1..3] of the flash memory 42 in the internal resource unit 40 and provides the information to the processor unit 20 to perform each initialization.

The state control register 33 is initialized to a default value upon reset upon power-on, and can be read / written at any time by the processor unit 20.

In the state control register 33, the enable / disable control of the DRAM module 41, the enable / disable control of the flash memory 42, and the RS232 transceiver 43 are controlled by the processor 20. Perform enable / disable control.

At this time, the resources in the internal resource unit 40 are the enable state which is the default state at the initial power-on, and in particular, the control of the DRAM module 41 and the flash memory 42 is first performed by the state control register 33 in the processor unit 20. In this case, disabling the DRAM module 41 and the flash memory 42 is controlled through the state control register 33 to control the second buffer 62 and the first buffer 61.

Each of the DRAM module 41 and the flash memory 42 in the internal resource unit 40 has an address bus and a chip select signal (internal DRAM CS, internal flash memory CS) from the processor unit 20, respectively. The data bus from the processor unit 20 is connected through the second buffer 62 and the first buffer 61 so as to be enabled / disabled according to the value of the state control register 33 in the 30. have.

In addition, the RS232 transceiver 43 is also enabled / disabled through a general input / output pin (I / O Pin) of the processor unit 20 according to the value of the status control register 33.

The external resource unit 50 including the external RS232 unit 51 and the external memory unit 52 receives the chip select signal CS of the processor unit 20 when the internal resources in the internal resource unit 40 are disabled. It can be used through.

The detailed operation of the hardware resource recognition control apparatus of the control system for communication according to the present invention configured as described above will be described with reference to the flowchart of FIG. 2.

First, as shown in the flow chart of (a) when the reset on power-up by the reset unit 10 is output to the processor unit 20 (S1), the processor unit 20 performs the initialization process for the CPU (S2) ).

That is, the default values of the hardware reset config register 31 and the status control register 33 in the register and the control unit 30 are read to initialize each register in the CPU.

Subsequently, the base register and the option register for determining the memory area, the speed, and the like are initialized (S3), and then the value of the status control register 33 is read (S4).

Next, as shown in the flowchart of (b), the value of the state control register 33 read in the step S4 is analyzed to determine whether the RS232 transceiver 43 in the internal resource unit 30 is enabled or disabled. (S5).

As a result of the determination in step S5, if the RS232 transceiver 43 is enabled, enable the internal SMC transceiver (S6), and then initialize the UART, i.e., the monitor port, as shown in the flowchart (S7). , CPU initialization is completed (S8).

As a result of the determination in step S5, if the RS232 transceiver 43 is disabled, the internal SMC transceiver is disabled and set to the standby mode (S9), and then the external SMC is turned on so that the CPU can use this resource externally. After enabling (S10), CPU initialization is completed (S8).

Subsequently, as shown in the flowchart of (d), the value of the status control register 33 read in step S4 is analyzed to determine whether the flash memory 42 in the internal resource unit 30 is enabled or disabled. (S11).

As a result of the determination in step S11, if the flash memory 42 is enabled, the status recognition register 32 is read (S12), and the base register and the option register of the CPU are initialized to match the capacity and speed (S13). After initializing the UART as shown in the flowchart of (A) (S7), the CPU initialization is completed (S8).

As a result of the determination in step S11, when the flash memory 42 is disabled, after initializing the appropriate base register and the option register in the external memory 52 so that external resources can be used in the CPU (S14), the ( After the UART is initialized as shown in the flowchart of S) (S7), the CPU initialization is completed (S8).

Finally, as shown in the flowchart of (e), the value of the status control register 33 read in the step S4 is analyzed to determine whether the DRAM module 41 in the internal resource unit 30 is enabled or disabled. (S15).

As a result of the determination in step S15, if the DRAM module 41 is enabled, the status recognition register 32 is read (S16), and the base register and the option register of the CPU are initialized to match the capacity and speed (S17). After initializing the UART as shown in the flowchart of (A) (S7), the CPU initialization is completed (S8).

As a result of the determination in step S15, when the DRAM module 41 is disabled, after initializing an appropriate base register and an option register in the external memory 52 so that external resources can be used in the CPU (S18), After the UART is initialized (S7), the CPU initialization is completed (S8).

As described above, in the prior art, although the initial configuration data read at the time of reset has to be changed in hardware and its contents cannot be changed during operation, the present invention provides the initial configuration data through the hardware reset configuration register of the register and the controller. The hardware configuration reset data can be changed at any time, and the status acknowledgment register reads the PD pins of the DRAM module and flash memory to recognize the capacity and speed, and uses them to initialize each resource appropriately. Optimized performance without software changes.

In addition, by enabling / disabling internal resources through the status control register, the resources can be used by an external resource unit, thereby facilitating scalability.

In other words, when upgrading hardware resources, there is no need to modify the software for each time, thereby reducing the cost and realizing economic effects by implementing a useful system that can efficiently manage resources.

Claims (2)

A reset unit for generating a reset in the processor unit when the power is turned on and initializing the inside of the processor unit; It is a built-in processor that has a built-in CPU and resources such as a memory controller and a serial communication controller. The built-in processor is initialized according to the reset of the reset unit. A processor unit that interfaces with other building blocks through control signals and interfaces with external RS232 and RS232 transceivers via SMC; When a hardware reset is output from the processor unit, a hardware reset config register for storing hardware reset configuration data input to the processor unit through a data bus and encoded through the PD pin [1..3] of the DRAM module. A status recognition register for inputting information and inputting decoded information through the PD pins [1..3] of the flash memory to provide the processor unit, a DRAM module in the internal resource unit, a flash memory, A register and a control unit configured to perform a state control register for enabling / disabling control of RS232, and performing a state recognition and control function for each resource; An internal resource unit comprising a DRAM module, a flash memory, and an RS232 transceiver to provide status information to the register and the controller, and to enable / disable under the control of the register and the controller; An external resource unit comprising an external RS232 unit and an external memory unit and used according to a control signal of the processor unit when an internal resource is not used; A first buffer for temporarily storing state information of the flash memory in the internal resource unit and outputting the state information to the register and a state control register in the control unit, and temporarily storing state information of the DRAM module in the internal resource unit, and then storing the state information in the register and the control unit. And a second buffer for outputting the control register to the hardware resource recognition controller of the communication control system. A reset by the reset unit when the power is turned on is output to the processor unit, and the processor unit initializes a base register and an option register for determining a CPU internal register, a memory area, a speed, and the like, and after performing the first step, the processor unit A second step of reading the values of the register and the status control register in the controller, a third step of interpreting the value of the status control register read in the second step, and a value of the status control register interpreted in the third step A fourth step of determining whether the RS232 transceiver in the internal resource unit is enabled or disabled, and if the RS232 transceiver is enabled, the internal SMC transceiver is enabled and UART is initialized after initializing the CPU. If the RS232 transceiver is disabled as a result of the determination of the fifth step and the fourth step A sixth step of disabling the internal SMC transceiver and enabling the external SMC to complete CPU initialization; and enabling or disabling the flash memory in the internal resource unit from the value of the status control register interpreted in the third step. If the flash memory is enabled as a result of the determination of the seventh step and the seventh step, the state recognition register is read to initialize the CPU base register and the option register to match the capacity and speed, and then the UART is initialized. And if the flash memory is disabled as a result of the determination of the eighth step and the seventh step, initialize the appropriate base register and the option register to the external memory, initialize the UART, and then complete the CPU initialization. The ninth step and the value of the state control register interpreted in the third step. A tenth step of determining whether the DRAM module in the internal resource unit is enabled or disabled; and if the DRAM module is enabled as a result of the determination in the tenth step, a status recognition register is read to match the capacity and speed of the CPU. An eleventh step of initializing the UART after initializing the registers and the option registers, and completing CPU initialization; and if the DRAM module is disabled as a result of the determination of the tenth step, initializes the appropriate base registers and option registers in an external memory. And a twelfth step of initializing the UART and then completing the initialization of the CPU.