JPH07160570A - Memory controller - Google Patents

Abstract

PURPOSE:To make access memory with variable access time by providing a timing control part, and setting a DSP in a hold state by receiving a write signal and a read signal from the DSP. CONSTITUTION:When the DSP 1 executes a write signal of DSP cycle and the write signal is outputted to the memory 3, it is address-decoded by the timing control part 2, and the held signal is outputted, and the DSP 1 is set in the hold state. A memory control part 4 receives the write signal from the DSP 1, and outputs the write signal whose effective time is extended to the memory control part 4. The write signal is outputted from the memory control part 4 to the memory 3, and a ready signal is outputted to the timing control part 2. The timing control part 2 disables the write signal to the memory control part 4. The ready signal is disabled, and the hold signal is also disabled, then, the DSP 1 can start again an operation from the next DSP cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage controller for accessing a memory whose access time is indefinite from a CPU.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a conventional technique, and its operation will be described with reference to this figure. The digital signal processor 901 is a DSP. 902 is a memory that can be accessed in one cycle.

The operation will be described in the order of writing and reading from the DSP 901 to the memory 902.

FIG. 2 is a timing chart when writing data from the DSP 901 to the memory 902. The DSP cycle (20
1), an address signal (202) for accessing the memory 902 from the DSP 901, a data signal (203) between the DSP 901 and the memory 902, a DSP 90
This is a negative logic write signal (204) for writing from 1 to the memory 902. DSP901 memory 902
When a write command for is executed, a write signal is output together with an address signal and a data signal. These signals are input to the memory 902, and the DSP uses these signals.
The data output from 901 to the memory 902 is written.

FIG. 3 is a timing chart when the DSP 901 reads from the memory 902. The DSP cycle (301), the address signal (302), the data signal (303) read from the memory 902, and the data from the memory 902 are sequentially read from the top. It is a negative logic read signal (304) for reading. When the DSP 901 executes the read command for the memory 902, the read signal is output together with the address signal. These signals are stored in the memory 902.
Data is read from the memory 902 by these signals.

FIG. 9 is a diagram showing a conventional example, in which 501 is an address counter, 502 is a data output section, and 503 is 3.
State buffer, 504 is comparator, 505 is 6
It is a 4 kword, 16 bit wide RAM.

First, the data output section is 5555h (h is 16
(Representing a decimal number), the 3-state buffer is enabled, and the output value of the data output unit is the RAM 505.
Input to the data line of.

The address counter increments by 1 from 0 to FFFFh and performs writing. Then, the 3-state buffer 503 is disabled, the address counter is incremented from 0 to FFFFh, and R
Read from AM505. The read data is input to the comparator 504. Compare all addresses.

Next, the data output unit 502 outputs AAAAh and the comparison is performed in the same manner.

The RAM is checked by writing different data to the RAM 505 as described above.

[0011]

However, in the conventional example, a digital signal processor DSP or processor CPU whose access time is indefinite with respect to an external memory is set to a memory whose access time is indefinite, for example, a dynamic RAM or Could not connect to multi-port RAM etc.

However, in the conventional example, although the data line is short-circuited or broken, the address line is short-circuited or broken.

[0013]

A timing control unit is provided to receive a write signal and a read signal from a DSP,
By inputting a hold signal to P and putting the DSP in a hold state, it is possible to access a memory whose access time is indefinite.

A disconnection is checked by providing a circuit for performing arithmetic operation of a sequence having a long period and writing to the RAM and a circuit for reading data from the RAM and comparing the data.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a drawing best showing the present invention, and the operation will be described with reference to this drawing. Reference numeral 1 is a DSP, 2 is a timing control unit, 3 is a memory with an indefinite access time, 4 is a memory control unit, and 5 is a memory that can be accessed in one cycle. Since writing and reading with respect to the memory 5 are the same as the access method with respect to the memory 902 of the conventional example, description thereof will be omitted here.

Write the access method to the memory 3,
It will be explained in the order of reading.

FIG. 4 is a timing chart when writing data from the DSP 1 to the memory 3. From the top, the DSP cycle (401), the address signal (402), the data signal (403), and the DSP 1 output to the timing control unit 2. Negative logic write signal (405), negative logic write signal (406) output from the timing control unit 2 to the memory control unit 4, negative logic hold signal (406) output from the timing control unit 2 to the DSP 1, Memory control unit 4
Is a negative logic ready signal (407) output from the timing control unit 2 to the timing control unit 2.

The program for writing from the DSP 1 to the memory 3 describes one write instruction. DSP1 is D
When the write command of the SP cycle 411 is executed and the write signal is output to the memory 3, the timing control unit 2 performs address decoding, the hold signal is output to the DSP 1, and the DSP is in the hold state. . The memory control unit 4 receives the write signal 404 from the DSP 1.
In response to this, a write signal 405 with an extended effective time is output to the memory control unit 4. The memory control unit 4 outputs a write signal capable of writing to the memory 3, and when completed, the memory control unit 4 outputs a ready signal 407 to the timing control unit 2. The timing control unit 2 receives the ready signal 407 and sends the write signal 40 to the memory control unit 104.
Disable 5. Ready signal 407 is the next DS
Disabled in P cycles. In addition, the hold signal is also disabled, and the next DSP cycle 415 starts DS
P resumes operation.

FIG. 5 is a timing chart when the DSP 1 reads from the memory 3, and DSPS in order from the top.
Cycle (501), address signal (502), data signal (503), negative logic read signal (504) output from the DSP 1 to the timing control unit 2, negative output from the timing control unit 2 to the memory control unit 4. A logic read signal (505), a negative logic hold signal (506) output from the timing control unit 2 to the DSP 2, and a negative logic ready signal (507) output from the memory control unit 4 to the timing control unit 2. .

The program when the DSP 1 reads from the memory 3 is based on the description of the read signal in two consecutive instructions. The first read instruction is for activating the read operation, and the next read instruction is for the DSP 1 to fetch data. First, the DSP 1 executes the read command of the DSP cycle 512, and outputs the read signal to the timing control unit 2. The timing control unit 2 receives this and outputs the read signal 505 to the memory control unit 4.
Enable. Further, by enabling the hold signal 506 output to the DSP1, the DSP1 is put in the hold state from the next DSP cycle. When the read processing from the memory 3 is completed, the memory control unit 4 outputs the ready signal 507 to the timing control unit 2. The ready signal will be disabled in the next DSP cycle. The timing control unit 2 receives the ready signal and disables the hold signal output to the DSP 1 so that the DSP 1 resumes operation from the next DSP cycle. Here, the second read instruction of the DSP cycle 516 is executed and the DSP 1 fetches the read data. In the timing control unit, the memory control unit 4 receives the second read signal.
Disable the read signal output to.

Although the present embodiment has been described by using the DSP configuration, the present invention can be applied to other similar CPUs.

<Other Embodiments> FIG. 7 shows an R according to the present invention.
This is an example of a test circuit for an AM address line, and its operation will be described in detail with reference to this drawing.

In FIG. 7, 101 is a constant output section for outputting a constant m, 102 is a multiplier, 103 is a constant output section for outputting a constant k, 104 is an adder, 105 is a latch, 10
6 is an address counter, 107 is a 3-state buffer,
Reference numeral 108 is a comparator, 109 is a 64-kword 16-bit wide RAM, and 110 is an oscillator.

In the same manner as in the conventional example, confirmation is made in advance. If there is an abnormality, the data line of the RAM 109 is short-circuited or broken. If it is normal, the process of this embodiment is performed. In this embodiment, a case where m = 9 and k = 1 will be described.

In this case, the sequence is a _{n + 1} = (9 × a _n +1) mod 10000h (Equation 1). The period of the sequence according to this formula is 10000 h.

First, the values calculated according to this equation are sequentially written from the address 0 to the final address of the RAM. The 3-state buffer 107 is enabled, and the output value of the latch 105 is input to the data line of the RAM 109.

FIG. 8 is a timing chart when the address line is tested. 201 is the output of the oscillator 110 which is the reference of the operation, and 202 is the constant output unit 101 which outputs m.
Output from the multiplier 203, output from the multiplier 102, 20
4 is a value output from the constant output unit 103 that outputs k,
Reference numeral 205 is an output of the adder 104, 206 is an output of the latch 105, and 207 is an address counter 106. 211
To 220 indicate cycles between rising edges of oscillator 110.

First, in cycle 211, the latch 105 is reset to 0. At this time, the output of the multiplier 102 is 0 and the output of the adder 104 is 1. The output of the oscillator 201 is input to the clock input of the latch 105 and is also input as a write pulse of the RAM 109. At this time, since the address counter indicates 0, data 0 is written to the address 0 of the RAM. Cycle 212
Then, the latch 105 is 1, the output of the multiplier 102 is 9, and the output of the adder 104 is Ah. Address counter 106
Is incremented by 1 to 1 and data 1 is written to address 1 of RAM 109. The calculation and the write operation are repeated in the same manner. Note that the output bit width of the multiplier 102 and the adder 104 is only 16 bits, and overflow at the time of operation disappears. As a result, the mod processing in (Equation 1) is performed. As described above, the sequence of addresses from the RAM address 0 to FFFFh (Equation 1) is written.

Next, the data is read from the RAM 109 and compared with the numerical sequence according to (Equation 1). 3-state buffer 1
07 is disabled. The data read from the RAM 109 is input to the comparator 108. Latch 1
05 is reset to 0, and the address counter 106 is also reset to 0. The latch 105 outputs the same value as at the time of writing. This value is input to the comparator 108. The output of the RAM 109 is also input to the comparator 108, and these values are compared. If a mismatch occurs, it can be determined that the address line of the RAM 109 is short-circuited or broken.

Although the hardware configuration has been described above, it goes without saying that the present embodiment can also be implemented by software.

<Other Embodiments> In order to confirm the RAM address larger than 16 k words, the number sequence is calculated in 32 bit units, and one number sequence is written for every two words. It is possible to check the short-circuit and disconnection of the address line even in the RAM having many lines.

[0032]

EFFECTS OF THE INVENTION With a small-scale circuit and a simple procedure, R
It is possible to find a short circuit or a break in the AM address line.

[Brief description of drawings]

FIG. 1 is a diagram showing an example in which the present invention is implemented.

FIG. 2 is a timing chart showing a write operation for an external memory in a conventional example.

FIG. 3 is a timing chart showing a read operation with respect to an external memory in a conventional example.

FIG. 4 is a timing chart showing a write operation with respect to an external memory in an example of implementing the present invention.

FIG. 5 is a timing chart showing a read operation with respect to an external memory in an example in which the present invention is implemented.

FIG. 6 is a diagram showing a conventional example.

FIG. 7 is a diagram showing an example in which the present invention is implemented.

8 is a timing chart showing the operation of the embodiment of FIG.

FIG. 9 is a diagram showing a conventional example.

[Explanation of symbols]

 101 Constant output section for outputting constant m 102 Multiplier 103 Constant output section for outputting constant k 104 Adder 105 Latch 106 Address counter 107 3-state buffer 108 Comparator 109 64k word 16-bit width RAM 110 Oscillator

Claims (2)

[Claims] 1. A timing control unit comprising a CPU having a fixed access time when accessing an external memory, a timing control unit, a memory having an indefinite access time, and a memory control unit controlling the memory. A storage control device characterized in that the memory is accessed by putting a CPU in a hold state in response to a hold signal from. 2. For a memory, the expressions a _{n + 1} = (m × a _n + k) mod d (n = 1,2) are assigned to different addresses.
, A ₁ = 0, m, k, d are integers, mod is the remainder of division by integers) The address line is tested by writing and reading a number sequence represented by Storage controller.