JP2003006043A - Compatible processing circuit and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compatible processing circuit meeting extension of a memory and functions by small-scale structure. SOLUTION: When a compatible instruction signal S2b to indicate the extension is inputted, data S2a for setting extended functions is outputted as data S15a as it is via an AND circuit 33. In addition, address data formed by synthesizing pieces of data read from registers 22 and 23 is outputted as data S15b. When a compatible instruction signal S2b to indicate compatibility is inputted, the data S2a for setting the extended functions is masked and outputted as the data S15a by a mask processing of the AND circuit 33. In addition, address data read from a register 24 is outputted as the data S15b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compatible processing circuit and a data processing device that enable proper operation of the device even when the memory and the processing function are expanded even after the expansion.

[0002]

2. Description of the Related Art For example, in a graphic device such as a game device, there is a demand for expanding the graphic processing function of a memory or a rendering circuit after shipping, that is, a so-called upward compatibility. In this case, for example, in order not to waste resources such as an existing program owned by the user, there is a request to selectively perform an operation before expansion and an operation after expansion in relation to a program to be used. .

[0003]

However, in the conventional graphic apparatus, if the memory or the function is expanded, the number of bits of the data to be processed is expanded, so that the upward compatibility is difficult. In particular, there has been no graphic device having a small-scale configuration and having an upward compatibility function.

The present invention has been made in view of the above-mentioned problems of the prior art, and it is an object of the present invention to provide a compatible processing circuit and a data processing device which can cope with expansion of a memory or a function with a small scale.

[0005]

In order to achieve the above-mentioned object, the compatibility processing circuit of the first aspect of the present invention comprises a higher-level device whose function and memory storage area are expanded with respect to the lower-level device, and the lower-level device. A compatibility processing circuit used to perform compatibility processing according to a program created on the basis of the function and the storage area, and an input circuit to which extended function setting data or address data is input; A first register for storing the extended function setting data input by a circuit, a second register for storing a predetermined upper bit of the address data input by the input circuit, and the address data input by the input circuit A third register for storing lower predetermined bits of the address data, and a fourth register for storing lower predetermined bits of the address data input by the input circuit. A first mask circuit for deciding whether to mask and output the data read from the first register or to output the data as it is, based on a compatibility instruction signal indicating whether or not to perform compatibility processing; A second mask circuit for deciding whether to mask and output the data read from the second register based on the compatibility instruction data, or read the data from the third register. Based on the compatibility instruction data, one of the data added with the data output from the second mask circuit as the upper bit of the most significant bit of the data and the data read from the fourth register is used. And a selection circuit for selecting and outputting.

Further, in the compatibility processing circuit of the first invention, preferably, the first register, the second register and the third register are set in a reset state and an operating state based on the compatibility instruction data. It further has a control circuit for controlling whether or not to make one of the states.

Further, the compatibility processing circuit of the first invention performs the following operation when the extended function setting data is stored in the first register. That is, the first
When the compatibility instruction data indicates that the compatibility processing is not performed, the mask circuit outputs the data read from the first register as it is to the outside of the compatibility processing circuit. As a result, the processing based on the function extended by the circuit outside the compatible processing circuit is performed based on the data read from the first register. Further, the first mask circuit masks the data read from the first register and outputs the data to the outside of the compatibility processing circuit when the compatibility instruction data indicates that the compatibility processing is performed. To do. As a result, the processing based on the function extended by the circuit outside the compatible processing circuit is not performed, and only the processing based on the compatible function is performed.

Further, the compatibility processing circuit of the first invention preferably indicates that the compatibility instruction data does not perform compatibility processing, and when the address data is stored in the first register. , The second mask circuit,
The data read from the second register is output as it is, and the selection circuit outputs the data read from the third register as an upper bit of the most significant bit from the second mask circuit. The data with the data added is selected and output to the outside of the compatible processing circuit. As a result, the extended area in the storage device of the memory outside the compatible processing circuit is accessed.

The compatibility processing circuit of the first invention preferably indicates that the compatibility instruction data performs compatibility processing, and when the address data is stored in the first register, The selection circuit selects the data read from the fourth register and outputs the data to the outside of the compatible processing circuit. As a result, only the compatible area in the storage device of the memory outside the compatible processing circuit is accessed.

In the compatible processing circuit of the second invention, a program created based on the function and the storage area of the lower device is provided in a higher device in which the storage area of the function and the memory is expanded with respect to the lower device. Is a compatibility processing circuit used to perform compatibility processing according to, and stores an input circuit to which extended function setting data or address data is input, and the extended function setting data input by the input circuit. A first register; a second register that stores the upper predetermined bits of the address data input by the input circuit; and a third register that stores the lower predetermined bits of the address data input by the input circuit, Based on compatibility instruction data indicating whether or not to perform compatibility processing,
Based on the compatibility instruction data, a first mask circuit for deciding whether to mask the data read from the first register and output the mask data, or the second mask circuit based on the compatibility instruction data.
Second mask circuit for deciding whether to mask and output the data read from the register, or to output the data as it is, as the upper bit of the most significant bit of the data read from the third register. The data obtained by adding the data output from the second mask circuit is output to the outside of the compatible processing circuit.

A data processing apparatus according to a third aspect of the present invention is a data processing apparatus which is an upper apparatus in which the storage area of the function and the memory is expanded with respect to the lower apparatus. A function setting register for storing data indicating whether or not to execute the extended function, a storage circuit, an access circuit for accessing the storage circuit, and the function and the storage area. A compatibility processing circuit that causes the data processing circuit and the memory access circuit to perform compatibility processing according to a program, the compatibility processing circuit having an input circuit to which extended function setting data or address data is input, A first register for storing the extended function setting data input by the input circuit, and a higher order of the address data input by the input circuit A second register for storing a constant bit, a third register for storing a lower predetermined bit of the address data input by the input circuit, and a third register for storing a lower predetermined bit of the address data input by the input circuit Whether the data read from the first register is masked and output as the data to be written in the function setting register based on the register No. 4 and the compatibility instruction signal indicating whether or not the compatibility process is performed. A mask circuit for deciding whether to output the data as it is, and a second mask for deciding whether to mask and output the data read from the second register based on the compatibility instruction data or to output the data as it is. A circuit and the second bit as an upper bit of the most significant bit of the data read from the third register.
Selecting circuit for selecting one of the data added with the data output from the mask circuit and the data read from the fourth register based on the compatibility instruction data and outputting the selected data to the memory access circuit. Have and.

A data processing device according to a fourth aspect of the present invention is a data processing device which is a higher-level device in which the storage area of the function and the memory is expanded with respect to the lower-level device. A function setting register for storing data indicating whether or not to execute the extended function, a storage circuit, an access circuit for accessing the storage circuit, and the function and the storage area. A compatibility processing circuit that causes the data processing circuit and the memory access circuit to perform compatibility processing according to a program, the compatibility processing circuit having an input circuit to which extended function setting data or address data is input, A first register for storing the extended function setting data input by the input circuit, and a higher order of the address data input by the input circuit Based on a second register that stores a constant bit, a third register that stores a lower predetermined bit of the address data input by the input circuit, and compatibility instruction data that indicates whether or not to perform compatibility processing, Based on the compatibility instruction data, a first mask circuit for deciding whether to mask the data read from the first register and output the data as the data stored in the function setting register; Second mask circuit for deciding whether to mask and output the data read from the second register or to output the data as it is, and the most significant bit of the data read from the third register. The data obtained by adding the data output from the second mask circuit to the access circuit is output as the upper bit of the data.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. First Embodiment FIG. 1 is an overall configuration diagram of an image processing apparatus 1 of this embodiment. As shown in FIG. 1, the image processing apparatus 1 is, for example, C
It has a PU 2 and a graphics circuit 3. This embodiment is an embodiment corresponding to the compatible processing circuit of the first invention and the data processing device of the third invention. Here, the graphic circuit 3 corresponds to the data processing device of the present invention.

[CPU 2] The CPU 2 executes a predetermined program and controls the graphic circuit 3 in accordance with the execution of the program. Further, the CPU 2 uses the data input from the graphic circuit 3 to perform a predetermined process. Specifically, the CPU 2 generates compatibility instruction data S2b for controlling the compatibility processing circuit 15 of the graphic circuit 3, and outputs this to the compatibility processing circuit 15. Also, CPU
2 generates function setting data and address data for the graphic circuit 3, and outputs this to the compatibility processing circuit 15 as data S2a. Further, the CPU 2 outputs, for example, the address data S2c to the compatibility processing circuit 15. The address data S2c is, for example, DR
When the data to be written to the AM 13 is output to the compatibility processing circuit 15 as the data S2a, the data is output from the CPU 2,
The address in the DRAM 13 for writing the setting data is shown.

Further, when the CPU 2 is executing a program (a program created for a lower-level device, a lower-level program) described on the premise that an expanded function or an expanded storage area described later is not used, , The compatibility instruction data S2 indicating the logical value "1" (high level) indicating that the compatibility processing is performed, that is, the function expansion is not performed.
b is output to the compatibility processing circuit 15. In addition, the CPU 2
When executing a program (a program created for the image processing apparatus 1 which is a higher-level device, a higher-level program) described on the assumption that an expanded function or an expanded storage area described later is used, compatibility is required. The compatibility instruction data S2b indicating the logical value "0" (low level) instructing not to perform the processing, that is, the function expansion is output to the compatibility processing circuit 15.

[Graphic Circuit 3] As shown in FIG. 1, the graphic circuit 3 includes, for example, a selection circuit 10, a function setting register 11, an image processing circuit 12, and a DRAM 1.
3. It has a memory access circuit 14 and a compatibility processing circuit 15. The function setting register 11 corresponds to the function setting register of the third invention, the image processing circuit 12 corresponds to the data processing circuit of the third invention, the DRAM 13 corresponds to the storage circuit of the third invention, and a memory. The access circuit 14 corresponds to the access circuit of the third invention, and the compatibility processing circuit 15 is the third.
It corresponds to the compatibility processing circuit of the invention.

<Selection Circuit 10> Whether the selection circuit 10 outputs the data S15a input from the compatibility processing circuit 15 to the function setting register 11 at the timing of function setting based on the control data from the control circuit (not shown). Decide whether or not. Further, the selection circuit 10 determines whether to output the data S15b input from the compatibility processing circuit 15 to the memory access circuit 14 at the access timing to the DRAM 13 based on control data from a control circuit (not shown).

<Function setting register 11> The function setting register 11 is used when the image processing circuit 12 determines whether or not to perform processing related to the extended function of the functions performed by the image processing circuit 12, for example. Is a register for accessing. The data S15a from the compatibility processing circuit 15 is written in the function setting register 11 via the selection circuit 10.

<Image processing circuit 12> Image processing circuit 12
Performs graphic processing using the data stored in the DRAM 13. The image processing circuit 12 performs an extended function process 51 and a compatible function process 52, as shown in FIG. The image processing circuit 12 accesses, for example, the function setting register 11 and the data S15a stored in the function setting register 11 indicates a low level (when it indicates that the function expansion is not performed). ) Has
The compatible function process 52 is executed, but the extended function process 51, for example, the multiple texture process is not executed. For example, when the image processing circuit 12 accesses the function setting register 11 and the data S15a stored in the function setting register 11 is at a high level (indicates that function expansion is performed), Both the extended function processing 51 and the compatible function processing 52 are executed.

<DRAM 13> The DRAM 13 stores data used for the processing of the image processing circuit 12. DR
As shown in FIG. 3, the AM 13 has a storage area including an extension storage area 55 and a compatibility storage area 56, and according to the processing of the compatibility processing circuit 15, the expansion storage area 55 and the compatibility storage area. Both of them are used, or only the compatible storage area 56 is used.

<Memory Access Circuit 14> The memory access circuit 14 includes the compatibility processing circuit 15 via the selection circuit 10.
The DRAM 13 is accessed based on the data S15b which is the address data input from the. In addition, the memory access circuit 14 accesses the DRAM 13,
It controls data transfer between the CPU 2 and the image processing circuit 12 and the DRAM 13.

<Compatibility Processing Circuit 15> FIG. 4 is a block diagram of the compatibility processing circuit shown in FIG. As shown in FIG. 4, the compatibility processing circuit 15 includes an input register 20, an extension function register 21, an extension bit register 22, and a compatibility bit register 2.
3, a compatible bit register 24, an input register 25, a control circuit 26, a mask circuit 27, and a selection circuit 28.

Here, the input register 20 corresponds to the input circuit of the present invention, the extended function register 21 corresponds to the first register of the present invention, and the extended bit register 22 corresponds to the second register of the present invention. , The compatible bit register 23 corresponds to the third register of the present invention, and the compatible bit register 2
4 corresponds to the fourth register of the present invention, and the AND circuit 33
Corresponds to the first mask circuit of the present invention, and the AND circuit 34
Corresponds to the second mask circuit of the present invention, and the selection circuit 28 corresponds to the selection circuit of the present invention.

The input register 20 selectively inputs the 10-bit data S2a, which is the setting data for extended function setting and the address data, from the CPU 2 shown in FIG. 1 and temporarily stores it. The extended function register 21 stores the upper 2 bits of the data S2a read from the input register 20. The extension bit register 22 is the input register 20.
The upper 2 bits of the data 2a read from are stored. The compatible bit register 23 stores the lower 8 bits of the data S2a read from the input register 20.
The compatible bit register 24 stores the lower 8 bits of the data S2a read from the input register 20. Extended function register 21, extended bit register 22, and compatible bit register 23 For example, when the data S31 input to the reset terminal is a logical value "1" (high level), the operation state is set, and a logical value "0" (low level). In the case of, the reset state is entered. In addition, the compatible bit register 24 is
When the data S32b input to the reset terminal has a logical value "1" (high level), the operating state is set, and when the logical value "0" (low level), the reset state is set.

The input register 20 stores the dress data S2c.
Is input from the CPU 2 shown in FIG. 1 and temporarily stored.

As shown in FIG. 4, the control circuit 26 has, for example, an inverter circuit 30, an AND circuit 31, and a decoding circuit 32. The inverter circuit 30 logically inverts, for example, 1-bit compatibility instruction data S2b input from the CPU 2 shown in FIG. 1 to generate compatibility instruction data S2b — and outputs it to the first input terminal of the AND circuit 31. The AND circuit 31 generates data S31 indicating the logical product of the compatibility instruction data S2b-from the inverter circuit 30 and the extension instruction data S32a from the decoding circuit 32, and uses this as the extension function register 21, extension bit register 22, and Output to the reset terminal of the compatible bit register 23.

The decode circuit 32 generates the extension instruction data S32a and the compatibility instruction data S32b based on the address data S2c read from the input register 25, which are respectively connected to the second input terminal of the AND circuit 31 and the compatibility. Output to the reset terminal of the bit register 24. Specifically, the decoding circuit 32, for example, when the address data S2c indicates extension, the extension instruction data S32a indicating the logical value "1" and the logical value "0".
And the compatibility instruction data S32b indicating Further, the decoding circuit 32, for example, when the address data S2c indicates compatibility, the extension instruction data S indicating a logical value "0".
32a and compatibility instruction data S32b indicating a logical value "1" are generated.

The mask circuit 27 includes AND circuits 33 and 34.
Have. The AND circuit 33 generates 2-bit data S15a which is a logical product of each bit of the 2-bit data S21 read from the extended function register 21 and the compatibility instruction data S2b_ from the inverter circuit 30, and outputs this. It outputs to the selection circuit 10 shown in FIG.

The AND circuit 34 includes the extension bit register 2
Each bit of the 2-bit data S22 read from 2 and the compatibility instruction data S2b from the inverter circuit 30
2-bit data S34, which is the logical product of and, is generated and output to the selection circuit 28. 2-bit data S34
Is added to the most significant bit of the 8-bit data S23 to become 10-bit data S39, and the data S39 is input to the first input terminal of the selection circuit 28.

The selection circuit 28 is, based on the compatibility instruction data S2b from the CPU 2, data S39 input from the first input terminal and read data of the compatible bit register 24 input from the second input terminal. Data S2
1 is selected as data S15b in FIG.
To the selection circuit 10 shown in FIG.

Hereinafter, an operation example of the image processing apparatus 1 shown in FIG. 1 will be described focusing on the operation of the compatible processing circuit 15. [First Operation Example] An operation example of the image processing apparatus 1 when the image processing circuit 12 of the graphic circuit 3 performs the extended function processing 51 shown in FIG. 2 will be described below with reference to FIG. CPU
2 to the compatible processing circuit 1 of the graphic circuit 3 shown in FIG.
5, data S, which is 2-bit extended function setting data
2a, compatibility instruction data S indicating low level (function expansion)
2b and address data S2c indicating expansion are output.

The decode circuit 32 of the compatibility processing circuit 15 shown in FIG. 5 generates the extension instruction data S32a indicating the high level based on the address data S2c and outputs it to the second input terminal of the AND circuit 31. The compatibility instruction data S32b indicating the low level is generated and output to the reset terminal of the compatibility bit register 24. As a result, the compatibility bit register 24 is reset. In addition, the inverter circuit 30 indicates that the compatibility instruction data S indicating high level.
2b is generated and output to the second input terminal of the AND circuit 33, the first input terminal of the AND circuit 34, and the first input terminal of the AND circuit 31. Then, the AND circuit 31 generates high-level data S31, which is output to the reset terminals of the extended function register 21, the extended bit register 22, and the compatible bit register 23. As a result, the extended function register 21, the extended bit register 22, and the compatible bit register 23 are in the operating state.

In parallel with the above operation, the 2-bit data S2a, which is the extended function setting data, is temporarily stored in the input register 20 of the compatibility processing circuit 15 shown in FIG. 5 and then read out. Are written in the extended function register 21. Then, the 2-bit data S2a is
Data S21 read from the extended function register 21
Is output to the first input terminal of the AND circuit 33.
Then, in the AND circuit 33, the 2-bit data S
21 and data S15a (S21), which is the logical product of the compatibility instruction data S2b_ indicating a high level, are generated and output to the selection circuit 10 shown in FIG. Data S15
a is selected by the selection circuit 10 and the function setting register 1
Written to 1. The image processing circuit 12 accesses the function setting register 11, and based on the data S15a,
An extended function, for example, multiple texture processing is executed. Further, in this case, the selection circuit 28 does not output the data to the selection circuit 10.

[Second Operation Example] Hereinafter, an operation example of the image processing apparatus 1 when the graphic circuit 3 uses both the expansion storage area 55 and the compatibility storage area 56 of the DRAM 13 shown in FIG. 4 will be described with reference to FIG. Will be explained. From the CPU 2 to the compatible processing circuit 15 of the graphic circuit 3 shown in FIG.
Data S2a that is 10-bit address data, compatibility instruction data S2b that indicates low level (function extension), and address data S2c that is an extension address are output. Here, the data S2a and the address data S2c are, for example, the same data.

The decoding circuit 32 of the compatibility processing circuit 15 shown in FIG. 5 generates expansion instruction data S32a indicating a high level based on the address data S2c and outputs it to the second input terminal of the AND circuit 31. The compatibility instruction data S32b indicating the low level is generated and output to the reset terminal of the compatibility bit register 24. As a result, the compatibility bit register 24 is reset. In addition, the inverter circuit 30 indicates that the compatibility instruction data S indicating high level.
2b is generated and output to the second input terminal of the AND circuit 33, the first input terminal of the AND circuit 34, and the first input terminal of the AND circuit 31. Then, the AND circuit 31 generates high-level data S31, which is output to the reset terminals of the extended function register 21, the extended bit register 22, and the compatible bit register 23. As a result, the extended function register 21, the extended bit register 22, and the compatible bit register 23 are in the operating state.

In parallel with the above operation, the data S2a, which is 10-bit address data, is temporarily stored in the input register 20 of the compatibility processing circuit 15 shown in FIG. The upper 2 bits of S2a are written in the extension bit register 22, and the lower 8 bits are written in the compatible bit register 23. Then, the upper 2 bits of the data S2a are read from the extension bit register 22 and output as the data S22 to the second input terminal of the AND circuit 34. Then, the AND circuit 34 generates and outputs the data S34 (S22) which is the logical product of the 2-bit data S22 and the compatibility instruction data S2b_ indicating the high level. Further, the lower 8-bit data of the data S2a is read out as the data S23 from the compatible bit register 23. Then, 2 is added on the most significant bit of the 8-bit data S23.
The 10-bit data S39 obtained by adding the bit data S34 is input to the selection circuit 28, and the data S1
5b is selected by the selection circuit 28 and output to the selection circuit 10 shown in FIG.

The 10-bit data S15b is output to the memory access circuit 14 via the selection circuit 10.
The memory access circuit 14 uses the 10-bit data S15.
The entire storage area including the expanded storage area is accessed using b.

[Third Operation Example] Hereinafter, an operation example of the image processing apparatus 1 when the graphic circuit 3 performs only the compatible function processing 52 without performing the extended function processing 51 shown in FIG.
Will be explained. From the CPU 2 to the compatibility processing circuit 15 of the graphic circuit 3 shown in FIG. 4, data S2a that is 2-bit extended function setting data, compatibility instruction data S2b that indicates a high level (compatibility), and address data S2c that is a compatibility address are provided. Is output. Then, the inverter circuit 30 causes the compatibility instruction data S2b indicating a low level.
Is generated, and the second input terminal of the AND circuit 33 is
A first input terminal of the AND circuit 34 and the AND circuit 3
1 to the first input terminal. As a result, the extended function register 21, the extended bit register 22, and the compatible bit register 23 are reset.

The 2-bit data S2a, which is the extended function setting data, is temporarily stored in the input register 20 of the compatibility processing circuit 15 shown in FIG. Be done. At this time, the extended function register 21 is in the reset state as described above. In addition, as described above, the compatibility instruction data S2b
Indicates a low level, the data S15a output from the AND circuit 33 becomes a low level. As a result, the function setting bit of the function setting register 11 shown in FIG. 1 becomes low level, and the image processing circuit 12 becomes
The extended function processing 51 shown in is not performed. That is, the image processing circuit 12 performs only the compatible function processing 52 shown in FIG.

[Fourth Operation Example] Hereinafter, an operation example of the image processing apparatus 1 when the graphic circuit 3 uses only the compatible storage area 56 without using the expansion storage area 55 of the DRAM 13 shown in FIG. Will be explained. From the CPU 2 to the compatibility processing circuit 15 of the graphic circuit 3 shown in FIG. 4, data S2a that is 10-bit address data, compatibility instruction data S2b that indicates a high level, and address data S2c that is an extended address are output. Here, the data S2
The a and the address data S2c may be the same data, for example.

The decoding circuit 32 of the compatibility processing circuit 15 shown in FIG. 8 generates the extension instruction data S32a indicating the low level based on the address data S2c and outputs it to the second input terminal of the AND circuit 31. The compatibility instruction data S32b indicating the high level is generated and output to the reset terminal of the compatibility bit register 24. As a result, the extended function register 21, the extended bit register 22, and the compatible bit register 23 are reset. In addition, the compatible bit register 24 is activated.

In parallel with the above operation, the data S2a, which is 10-bit address data, is temporarily stored in the input register 20 of the compatibility processing circuit 15 shown in FIG. The lower 8 bits of S2a are written in the compatible bit register 24. Then, the lower 8-bit data of the data S2a is read from the compatible bit register 24, and is selected as the data S24 by the selection circuit 2.
8 is output. The data S24 is selected by the selection circuit 28, and the selection circuit 1 shown in FIG. 1 is selected as the data S15b.
It is output to 0. The data S15b is output to the memory access circuit 14 via the selection circuit 10. The memory access circuit 14 uses the data S15b, which is 8-bit address data, to store the compatibility storage area 56 shown in FIG.
To access. In this case, the expansion storage area 55 is not accessed.

As described above, according to the image processing apparatus 1, since the compatibility processing circuit 15 having the configuration shown in FIG. 4 is used, the program described on the assumption that the function and the memory are not expanded ( When the low-order program) is being executed, the masked low-level data S15a is written in the function setting register 11 and
The address data S15b obtained by masking the upper 2 bits of the bit address data S2a is output to the memory access circuit 14. Therefore, the image processing circuit 1 shown in FIG.
It is possible to cause 2 to execute only the compatible function processing 52 without executing the extended function processing 51. Further, the memory access circuit 14 shown in FIG. 1 can be made to access only the compatible storage area 56 without accessing the expansion storage area 55 of the DRAM 13 shown in FIG.

Further, according to the image processing apparatus 1, by using the compatible processing circuit 15 having the configuration shown in FIG. 4, a program (upper program) described on the assumption that the function and the memory are expanded is provided. If you are running
The data S2a is written as it is to the function setting register 11 as the data S15a, and the 10-bit address data S2a is outputted as it is to the memory access circuit 14 as the data S15b. Therefore, the image processing circuit 12 shown in FIG. 1 can be made to execute both the extended function processing 51 and the compatible function processing 52. Further, the memory access circuit 14 shown in FIG.
It is possible to access both the extension storage area 55 and the compatibility storage area 56 of No. 3.

That is, according to the image processing apparatus 1, the processing can be performed using both the lower program and the upper program.

Second Embodiment FIG. 9 is an overall configuration diagram of the image processing apparatus 101 of this embodiment. As shown in FIG. 9, the image processing apparatus 101 has, for example, a CPU 102 and a graphic circuit 103. This embodiment is an embodiment corresponding to the compatible processing circuit of the second invention and the data processing device of the fourth invention. Here, the graphic circuit 103 corresponds to the data processing device of the present invention.

[CPU 102] The CPU 102 executes a predetermined program, and according to the execution of the program,
It controls the graphic circuit 103. Also, the CPU 10
2 performs a predetermined process using the data input from the graphic circuit 103. The CPU 102 also performs a predetermined process using the data input from the graphic circuit 103. Specifically, the CPU 102 generates compatibility instruction data S102b that controls the compatibility processing circuit 115 of the graphic circuit 103, and outputs this to the compatibility processing circuit 115. Further, the CPU 102 uses the graphic circuit 1
03 function setting data and address data are generated, and this is used as data S102a, and the compatibility processing circuit 115
Output to. Further, the CPU 102 outputs, for example, the address data S102c to the compatibility processing circuit 115. The address data S102c is, for example, D
When the data to be written in the RAM 113 is output to the compatibility processing circuit 115 as the data S102a, the CPU 102
The DRAM 11 that outputs the setting data and writes the setting data
Addresses in 3 are shown.

Further, when the CPU 102 is executing a program (a program created for a lower-level device, a lower-level program) described on the premise that an expanded function or an expanded storage area described later is not used, , Compatibility instruction data S indicating a logical value “1” (high level) indicating that compatibility processing is performed, that is, that function expansion is not performed.
102b is output to the compatibility processing circuit 115. Also, CP
U102 executes a program (a program created for the image processing apparatus 1 which is a higher-level device, a higher-level program) described on the premise that the expanded function or the expanded storage area described later is used. Outputs the compatibility instruction data S102b indicating the logical value "0" (low level) instructing not to perform the compatibility processing, that is, the function expansion, to the compatibility processing circuit 115.

[Graphic Circuit 103] As shown in FIG. 9, the graphic circuit 103 includes, for example, the selection circuit 1
10, function setting register 111, image processing circuit 11
2, DRAM 113, memory access circuit 114 and compatible processing circuit 115. Function setting register 11
1 corresponds to the function setting register of the fourth invention, the image processing circuit 112 corresponds to the data processing circuit of the fourth invention,
The DRAM 113 corresponds to the memory circuit of the fourth invention, the memory access circuit 114 corresponds to the access circuit of the fourth invention, and the compatibility processing circuit 115 corresponds to the compatibility processing circuits of the second and fourth inventions. .

<Selection Circuit 110> Whether the selection circuit 110 outputs the data S115a input from the compatibility processing circuit 115 to the function setting register 111 at the timing of function setting based on the control data from the control circuit (not shown). Decide whether or not. In addition, the selection circuit 110 uses the DRAM 1 based on control data from a control circuit (not shown).
At the access timing to 13, the compatible processing circuit 115
The data S115b input from the memory access circuit 1
It is determined whether to output to 14.

<Function Setting Register 111> The function setting register 111 is used when the image processing circuit 112 determines whether or not to perform processing related to the extended function of the functions performed by the image processing circuit 112, for example. Is a register for accessing. The function setting register 111 stores data S11 from the compatibility processing circuit 115 via the selection circuit 110.
5a is written.

<Image processing circuit 112> Image processing circuit 11
2 performs graphic processing using the data stored in the DRAM 113. The image processing circuit 112 is shown in FIG.
As shown in 0, the extended function processing 151 and the compatible function processing 1
52. The image processing circuit 112, for example, accesses the function setting register 111, and the data S115a stored in the function setting register 111 indicates a low level (when it indicates that the function expansion is not performed). ), The compatible function processing 152 is executed,
The extended function processing 151, for example, multiple texture processing is not executed. The image processing circuit 112, for example, accesses the function setting register 111, and when the data S115a stored in the function setting register 111 is at a high level (indicates that function expansion is performed), Both the extended function processing 151 and the compatible function processing 152 are executed.

<DRAM 113> The DRAM 113 stores data used for the processing of the image processing circuit 112. As shown in FIG. 11, the DRAM 113 has a storage area including an extension storage area 155 and a compatibility storage area 156, and according to the processing of the compatibility processing circuit 115, the extension storage area 155 and the compatibility storage area. Both of them are used, or only the compatible storage area 156 is used.

<Memory Access Circuit 114> The memory access circuit 114 receives the data S1 which is the address data input from the compatibility processing circuit 115 via the selection circuit 110.
The DRAM 113 is accessed based on 15b.
Further, the memory access circuit 114 accesses the DRAM 113, and the CPU 102 and the image processing circuit 11 are accessed.
2 and the data transfer between the DRAM 113.

<Compatibility Processing Circuit 115> As shown in FIG. 12, the compatibility processing circuit 115 includes an input register 120, an extended function register 121, an extended bit register 122, a compatible bit register 123, an input register 125, a control circuit 126, and a mask. It has a circuit 127.

Here, the input register 120 corresponds to the input circuit of the present invention, the extended function register 121 corresponds to the first register of the present invention, and the extended bit register 122 corresponds to the second register of the present invention. , Compatible bit register 1
23 corresponds to the third register of the present invention, and AND circuit 1
33 corresponds to the first mask circuit of the present invention, and the AND circuit 134 corresponds to the second mask circuit of the present invention.

The input register 120 selectively inputs, from the CPU 102 shown in FIG. 9, 10-bit data S102a, which is setting data for extended function setting and address data, and temporarily stores it. The extended function register 121 is
Data S102a read from the input register 120
The upper 2 bits of are stored. Extension bit register 122
Stores the upper 2 bits of the data 2a read from the input register 120. Compatible bit register 123
Is the data S10 read from the input register 120.
The lower 8 bits of 2a are stored. Extended function register 12
For example, 1 and the extension bit register 122 are in the operation state when the data S131 input to the reset terminal is the logical value “1” (high level), and are in the reset state when the logical value “0” (low level). Become. The compatible bit register 123 is in an operating state when the data S135 input to the reset terminal has a logical value "1" (high level), and is in a reset state when the logical value "0" (low level).

The input register 120 stores the address data S
102c is input from the CPU 102 shown in FIG. 9 and temporarily stored.

The control circuit 126, as shown in FIG.
For example, the inverter circuit 130, the AND circuit 131, the decode circuit 132, and the NOR circuit 135 are included. The inverter circuit 130 logically inverts, for example, 1-bit compatibility instruction data S102b input from the CPU 102 shown in FIG. 9 to generate compatibility instruction data S102b-, and outputs this to the first input terminal of the AND circuit 131. A
The ND circuit 131 uses the data S13 indicating the logical product of the compatibility instruction data S102b-from the inverter circuit 130 and the extension instruction data S132a from the decoding circuit 132.
1 is generated and is output to the extended function register 121, the extended bit register 122, and the first input terminal of the NOR circuit 135.

The decoding circuit 132 is provided in the input register 12
5, the extension instruction data S132a and the compatibility instruction data S based on the address data S102c read from
132b, and generate an AND circuit 131 for each of them.
To the second input terminal of the NOR circuit 135. Specifically, the decoding circuit 132
For example, when the address data S102c indicates extension, the extension instruction data S13 indicating the logical value "1"
2a and compatibility instruction data S132b indicating a logical value “0” are generated. In addition, the decoding circuit 132, for example, when the address data S102c indicates compatibility, the extension instruction data S132a indicating a logical value "0" and the logical value "1".
And the compatibility instruction data S132b indicating NOR
The circuit 135 generates data S135 which is an inverted logical sum of the data S131 and the data S132b, and outputs this to the reset terminal of the compatible bit register 123.

The mask circuit 127 has an AND circuit 133.
Has 134. The AND circuit 133 is a 2-bit data S11 which is a logical product of each bit of the 2-bit data S102 read from the extended function register 121 and the compatibility instruction data S102b-from the inverter circuit 130.
5a is generated and output to the selection circuit 110 shown in FIG.

The AND circuit 134 receives the compatibility instruction data S from the inverter circuit 130 and each bit of the 2-bit data S121 read from the extension bit register 122.
2-bit data S134 that is a logical product with 102b
And output it. 2-bit data S134
Is added to the uppermost bit of the 8-bit data S123 read from the compatible bit register 123,
It becomes bit data S115b and is output to the selection circuit 110 shown in FIG.

Hereinafter, an operation example of the image processing apparatus 101 shown in FIG. 9 will be described focusing on the operation of the compatibility processing circuit 115. [First Operation Example] An operation example of the image processing apparatus 101 when the image processing circuit 112 of the graphic circuit 103 performs the extended function processing 151 shown in FIG. 10 will be described below with reference to FIG. From the CPU 102 to the compatibility processing circuit 115 of the graphic circuit 103 shown in FIG. 13, data S102a that is 2-bit extended function setting data, compatibility instruction data S102b that indicates a low level (function extension), and address data S102c that indicates an extended address. Is output.

The decoding circuit 132 of the compatibility processing circuit 115 shown in FIG. 13 generates the extension instruction data S132a indicating the high level based on the address data S102c and outputs it to the second input terminal of the AND circuit 131. Further, the inverter circuit 130 generates the compatibility instruction data S102b indicating the high level, and the AND instruction circuit 133 generates the compatibility instruction data S102b.
To the first input terminal of the AND circuit 134 and the first input terminal of the AND circuit 131. Then, the AND circuit 131 generates high-level data S131, which is the extended function register 1
21, extension bit register 122 and NOR circuit 13
5 is output to the first input terminal. As a result, the extended function register 121 and the extended bit register 122 are
It becomes operational. Then, the NOR circuit 135 outputs the high level data S135 to the reset terminal of the compatible bit register 123. As a result, the compatible bit register 123 is activated.

In parallel with the above operation, the 2-bit data S102a, which is the extended function setting data, is temporarily stored in the input register 120 of the compatibility processing circuit 115 shown in FIG. 13 and then read out. Are written in the extended function register 121. Then, the 2-bit data S102a is read from the extended function register 121 and output as the data S121 to the first input terminal of the AND circuit 133. Then, in the AND circuit 133, the data S1 which is the logical product of the 2-bit data S121 and the compatibility instruction data S102b
15a (S121) is generated and output to the selection circuit 110 shown in FIG. The data S115a is selected by the selection circuit 110 and written in the function setting register 111. The image processing circuit 112 accesses the function setting register 111 and executes, for example, multiple texture processing, which is an extended function, based on the data S115a.

[Second Operation Example] An operation example of the image processing apparatus 101 when the graphic circuit 103 uses both the expansion storage area 155 and the compatibility storage area 156 of the DRAM 113 shown in FIG. 11 will be described below with reference to FIG. Will be described with reference to. The CPU 102 outputs the data S102a, which is 10-bit address data, the compatibility instruction data S102b, which is a low level (function extension), and the address data S102c, which is an extension address, to the compatibility processing circuit 115 of the graphic circuit 103 shown in FIG. It Here, the data S102a and the address data S10
2c is, for example, the same data.

The decoding circuit 132 of the compatibility processing circuit 115 shown in FIG. 14 generates expansion instruction data S132a indicating a high level based on the address data S102c and outputs it to the second input terminal of the AND circuit 131, and The compatibility instruction data S132b indicating low level is generated and output to the second input terminal of the NOR circuit 135. Further, the inverter circuit 130 generates the compatibility instruction data S102b indicating the high level, and the AND instruction circuit 133 generates this.
To the first input terminal of the AND circuit 134 and the first input terminal of the AND circuit 131. Then, the AND circuit 131 generates high-level data S131, which is the extended function register 1
21, extension bit register 122 and NOR circuit 13
5 is output to the first input terminal. Then, the NOR circuit 135 outputs the high level data S135 to the compatible bit register 123. As a result, the extended function register 121, the extended bit register 122, and the compatible bit register 123 are in the operating state.

In parallel with the above operation, the input register 120 of the compatibility processing circuit 115 shown in FIG.
The data S102a, which is bit address data, is temporarily stored and then read, the upper 2 bits of the data S102a are written to the extension bit register 122, and the lower 8 bits are written to the compatible bit register 123. Then, the data of the upper 2 bits of the data S102a is read from the extension bit register 122 and output as the data S122 to the second input terminal of the AND circuit 134. Then, in the AND circuit 134, 2
Data S134 (S that is the logical product of bit data S122 and compatibility instruction data S102b
122) is generated and output. Further, the lower 8-bit data of the data S102a is read as the data S123 from the compatible bit register 123. Then, on the most significant bit of the 8-bit data S123,
The 10-bit data S115b obtained by adding the 2-bit data S134 is the selection circuit 110 shown in FIG.
Is output to.

The 10-bit data S115b is output to the memory access circuit 114 via the selection circuit 110. The memory access circuit 114 uses the 10-bit data S115b to access the entire storage area including the expanded storage area.

[Third operation example] Hereinafter, the image processing apparatus 101 when the graphic circuit 103 performs only the compatible function processing 152 without performing the extended function processing 151 shown in FIG.
An example of the operation will be described with reference to FIG. Compatible processing circuit 1 from CPU 102 to graphic circuit 103 shown in FIG.
The data S102a, which is 2-bit extended function setting data, and the compatibility instruction data S102b indicating high level (compatibility) are output to 15. Then, the inverter circuit 13
0 generates compatibility instruction data S102b-indicating a low level, which is the second input terminal of the AND circuit 133, A
First input terminal of ND circuit 134 and AND circuit 1
It outputs to the 1st input terminal of 31. As a result, the extended function register 121 and the extended bit register 122 are
It goes into a reset state.

Further, in the input register 120 of the compatibility processing circuit 115 shown in FIG.
After being temporarily stored in the bit data S102a,
It is read and written in the extended function register 121.
At this time, the extended function register 121 is in the reset state as described above. Further, as described above, since the compatibility instruction data S102b_ indicates a low level, the data S115a output from the AND circuit 133 is
Goes low. As a result, the function setting bit of the function setting register 111 shown in FIG. 9 becomes low level, and the image processing circuit 112 does not perform the extended function processing 151 shown in FIG. That is, the image processing circuit 112
Performs only the compatible function processing 152 shown in FIG.

[Fourth Operation Example] Hereinafter, an operation example of the image processing apparatus 101 when the graphic circuit 103 uses only the compatibility storage area 156 without using the extension storage area 155 of the DRAM 113 shown in FIG. Will be described with reference to FIG. From the CPU 102 to the compatibility processing circuit 115 of the graphic circuit 103 shown in FIG. 16, data S102a which is 10-bit address data, compatibility instruction data S102b indicating high level, and address data S10.
2c is output. Here, the data S102a and the address data S102c may be the same data, for example.

Then, in the inverter circuit 130,
A compatibility instruction signal S102b-indicating a low level is generated, and this is the second input terminal of the AND circuit 133, AND
The signal is output to the first input terminal of the circuit 134 and the first input terminal of the AND circuit 131. As a result, the AND circuit 1
From 34, data S134 in which both 2 bits are low level (masked) is output.

The decoding circuit 132 of the compatibility processing circuit 115 shown in FIG. 16 generates the extension instruction data S132a indicating the low level based on the address data S102c and outputs it to the second input terminal of the AND circuit 131. The compatibility instruction data S132b indicating high level is generated and output to the second input terminal of the NOR circuit 135. As a result, the NOR circuit 135 outputs the data S135 indicating a high level to the reset terminal of the compatible bit register 123, and the compatible bit register 123 is put into an operating state.

In parallel with the above operation, the input register 120 of the compatibility processing circuit 115 shown in FIG.
The data S102a, which is bit address data, is temporarily stored and then read, and the lower 8 bits of the data S102a are written to the compatible bit register 123. Then, from the compatible bit register 123, the data S
The lower 8-bit data of 102a is read as the data S123, the 2-bit data S134 indicating the low level is added to the most significant bit of the data S123, and the obtained data S115b is the selection circuit 110 shown in FIG.
Is output to the memory access circuit 114 via. The memory access circuit 114 accesses the compatible storage area 156 shown in FIG. 11 by using the data S115b which is the address data in which the upper 2 bits are masked. In this case, the expansion storage area 155 is not accessed.

As described above, the image processing apparatus 101
According to this, by using the compatibility processing circuit 115 having the configuration shown in FIG. 12, when the program (lower-level program) described on the assumption that the extended function is not used is executed, the function setting register The masked low-level data S115a is written in 111, and the address data S115b masked by the upper 2 bits of the 10-bit address data S102a is output to the memory access circuit 114. Therefore, the image processing circuit 112 shown in FIG. 9 can be made to execute only the compatible function processing 152 without executing the extended function processing 151. Further, the memory access circuit 114 shown in FIG. 9 can be made to access only the compatibility storage area 156 without accessing the expansion storage area 155 of the DRAM 113 shown in FIG.

Further, according to the image processing apparatus 101, as shown in FIG.
By using the compatibility processing circuit 115 having the configuration shown in FIG. 2, if a program (upper program) described on the assumption that an extended function or an extended storage area is used is being executed, the function setting Data S1 in the register 111
02a is written as it is as the data S115a, and 10-bit address data S102a is outputted as it is to the memory access circuit 114 as the data S115b. Therefore, the image processing circuit 112 shown in FIG.
Both the extended function processing 151 and the compatible function processing 152 can be executed. Further, the memory access circuit 114 shown in FIG. 9 can be made to access both the expansion storage area 155 and the compatibility storage area 156 of the DRAM 113 shown in FIG. That is, according to the image processing apparatus 101, it is possible to perform processing using both the lower program and the upper program.

Further, in the image processing apparatus 101, the configuration of the compatibility processing circuit 115 shown in FIG. 12 is simpler and smaller than that of the compatibility processing circuit 15 shown in FIG. it can. That is, the compatibility processing circuit 115
In, in place of the two compatible bit registers 23 and 24 in the compatible processing circuit 15, one compatible bit register 123 can be used to realize the same function.

[0079]

As described above, according to the present invention,
It is possible to provide a compatible processing circuit and a data processing device capable of expanding memory and functions with a small-scale configuration.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining processing performed by the image processing circuit shown in FIG.

FIG. 3 is a diagram for explaining a storage area of the DRAM shown in FIG.

FIG. 4 is a configuration diagram of a compatibility processing circuit shown in FIG.

5 is a diagram for explaining an operation example of the compatible processing circuit shown in FIG. 4 when the image processing circuit shown in FIG. 1 performs extended function processing.

FIG. 6 is a diagram showing a DR of the memory access circuit shown in FIG.
FIG. 4 when accessing the expanded storage area of the AM
FIG. 7 is a diagram for explaining an operation example of the compatibility processing circuit shown in FIG.

FIG. 7 is a diagram for explaining an operation example of the compatible processing circuit shown in FIG. 4 when the image processing circuit shown in FIG. 1 performs only compatible function processing.

FIG. 8 is a diagram showing a case where the memory access circuit shown in FIG.
FIG. 5 is a diagram for explaining an operation example of the compatible processing circuit shown in FIG. 4 when accessing only the compatible storage area of AM.

FIG. 9 is an overall configuration diagram of an image processing apparatus according to a second embodiment of the present invention.

FIG. 10 is a diagram for explaining processing performed by the image processing circuit shown in FIG. 9.

FIG. 11 is a diagram for explaining a storage area of the DRAM shown in FIG. 9.

12 is a block diagram of the compatibility processing circuit shown in FIG. 9;

13 is a diagram for explaining an operation example of the compatible processing circuit shown in FIG. 12 when the image processing circuit shown in FIG. 9 performs extended function processing.

FIG. 14 is a diagram for explaining an operation example of the compatibility processing circuit shown in FIG. 12 when the memory access circuit shown in FIG. 9 accesses an extended storage area of a DRAM.

FIG. 15 is a diagram for explaining an operation example of the compatible processing circuit shown in FIG. 12 when the image processing circuit shown in FIG. 9 performs only compatible function processing.

16 is a diagram for explaining an operation example of the compatible processing circuit shown in FIG. 12 when the memory access circuit shown in FIG. 9 accesses only the compatible storage area of the DRAM.

[Explanation of symbols]

1, 101 ... Image processing device, 2, 102 ... CPU, 3,
103 ... Graphic circuit, 10, 110 ... Selection circuit,
11, 111 ... Function setting register, 12, 112 ... Image processing circuit, 13, 113 ... DRAM, 14, 114 ...
Memory access circuit

Claims (11)

[Claims] 1. A high-level device, which has a function and a memory storage area expanded for a low-level device, performs compatibility processing according to a program created based on the function and the storage area of the low-level device. A compatible processing circuit used, wherein an input circuit to which extended function setting data or address data is input, a first register for storing the extended function setting data input by the input circuit, and the input circuit A second register for storing the upper predetermined bits of the input address data; a third register for storing the lower predetermined bits of the address data input by the input circuit; and a third register for storing the address data input by the input circuit. Based on a fourth register that stores lower predetermined bits and a compatibility instruction signal that indicates whether or not to perform compatibility processing,
A first mask circuit for deciding whether to mask and output the data read from the first register or to output the data as it is; and to read the data from the second register based on the compatibility instruction data. A second mask circuit for deciding whether to mask the data and output it, or to output it as it is, and from the second mask circuit as an upper bit of the most significant bit of the data read from the third register. A compatibility processing circuit having a selection circuit that selects and outputs one of the data added with the output data and the data read from the fourth register based on the compatibility instruction data. 2. Controlling whether or not the first register, the second register, and the third register are set to either one of a reset state and an operating state based on the compatibility instruction data. The compatible processing circuit according to claim 1, further comprising a control circuit. 3. When the extended function setting data is stored in the first register, the first mask circuit, when the compatibility instruction data indicates that compatibility processing is not performed. , The data read from the first register is output to the outside of the compatibility processing circuit as it is, and the compatibility instruction data is read from the first register when the compatibility instruction data indicates that the compatibility processing is performed. The compatibility processing circuit according to claim 1, wherein the data is masked and output to the outside of the compatibility processing circuit. 4. The compatibility instruction data indicates that compatibility processing is not performed, and when the address data is stored in the first register, the second mask circuit causes the second mask circuit to perform the second processing. The data read from the register is output as it is, and the selection circuit adds the data output from the second mask circuit as an upper bit of the most significant bit of the data read from the third register. The compatibility processing circuit according to claim 1, wherein data is selected and output to the outside of the compatibility processing circuit. 5. The compatibility instruction data indicates that compatibility processing is performed, and when the address data is stored in the first register, the selection circuit reads from the fourth register. The compatibility processing circuit according to claim 1, wherein the selected data is selected and output to the outside of the compatibility processing circuit. 6. A high-level device, which has a function and a memory storage area expanded for a low-level device, performs compatibility processing according to a program created based on the function and the storage area of the low-level device. A compatible processing circuit used, wherein an input circuit to which extended function setting data or address data is input, a first register for storing the extended function setting data input by the input circuit, and the input circuit A second register that stores the upper predetermined bits of the input address data, a third register that stores the lower predetermined bits of the address data input by the input circuit, and indicates whether or not to perform compatibility processing. A first for deciding whether to mask the data read from the first register and to output it as it is or to output it as it is, based on the compatibility instruction data.
And a second mask circuit for deciding whether to mask and output the data read from the second register based on the compatibility instruction data, or to output the data as it is. A compatibility processing circuit for outputting the data obtained by adding the data output from the second mask circuit as an upper bit of the most significant bit of the data read from the register to the outside of the compatibility processing circuit. 7. A control for controlling whether the first register, the second register, and the third register are set to one of a reset state and an operating state based on the compatibility instruction data. The compatible processing circuit according to claim 6, further comprising a control circuit. 8. The first mask circuit, when the extended function setting data is stored in the first register, when the compatibility instruction data indicates that compatibility processing is not performed. , The data read from the first register is output to the outside of the compatibility processing circuit as it is, and the compatibility instruction data is read from the first register when the compatibility instruction data indicates that the compatibility processing is performed. The compatibility processing circuit according to claim 6, wherein the data is masked and output to the outside of the compatibility processing circuit. 9. The compatibility instruction data indicates that compatibility processing is not performed, and when the address data is stored in the first register, the second mask circuit causes the second mask circuit to perform the second processing. The compatibility processing circuit according to claim 6, wherein the data read from the register is output as it is. 10. A data processing device, which is a higher-level device having expanded functions and memory storage areas for a lower-level device, the data processing circuit and the data processing circuit performing the expanded function. A function setting register for storing data indicating whether or not the memory circuit, an access circuit for accessing the memory circuit, and a compatibility process according to a program created based on the function and the memory area, the data. A compatible processing circuit that causes the memory access circuit to perform the processing, and the compatible processing circuit includes an input circuit to which extended function setting data or address data is input, and the extended function input to the input circuit. A first register for storing setting data; and a second register for storing upper predetermined bits of the address data input by the input circuit. A register, a third register for storing a lower predetermined bit of the address data input by the input circuit, a fourth register for storing a lower predetermined bit of the address data input by the input circuit, and a compatibility process. Based on the compatibility instruction signal indicating whether to perform,
As the data written in the function setting register,
A mask circuit for deciding whether to mask and output the data read from the first register, or to output the mask data as it is, and the data read from the second register based on the compatibility instruction data. A second mask circuit for deciding whether to output by masking or as it is, and as an upper bit of the most significant bit of the data read from the third register, output from the second mask circuit. A data processing device having a selection circuit that selects one of data added with data and data read from the fourth register based on the compatibility instruction data and outputs the selected data to the memory access circuit. 11. A data processing device, which is an upper device in which a storage area of a function and a memory is expanded with respect to a lower device, and a data processing circuit and whether the data processing circuit executes the expanded function. A function setting register for storing data indicating whether or not the memory circuit, an access circuit for accessing the memory circuit, and a compatibility process according to a program created based on the function and the memory area, the data. A compatible processing circuit that causes the memory access circuit to perform the processing, and the compatible processing circuit includes an input circuit to which extended function setting data or address data is input, and the extended function input to the input circuit. A first register for storing setting data; and a second register for storing upper predetermined bits of the address data input by the input circuit. A register, a third register for storing a lower predetermined bit of the address data input by the input circuit, and a function setting register stored on the basis of compatibility instruction data indicating whether or not a compatibility process is performed. The first data for deciding whether to mask and output the data read from the first register as the data to be output or to output the data as it is.
And a second mask circuit for deciding whether to mask and output the data read from the second register based on the compatibility instruction data, or to output the data as it is. A data processor that outputs the data obtained by adding the data output from the second mask circuit as the upper bits of the most significant bit of the data read from the register to the access circuit.