JPS63148363A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce a ROM capacity and to shorten a processing time, by providing a circuit and an instruction which set a mode register value on a ROM directly in a mode register at the time of resetting and instructing the setting of the mode register. CONSTITUTION:The initial value of the mode register 4 is set in advance at a specific address on the ROM3. Next, when a reset signal 101 is outputted from a reset circuit 1, a control signal is outputted from a control signal generation circuit 9, and a PC selection circuit 10 selects a mode register setting PC11, and the PC (program counter) of the mode register setting PC11 is set on a leading address whose initial value is stipulated on the ROM3, and also, a mode transfer circuit 12 is opened, and the mode value of the ROM3 outputted via a bus 102 is transferred to the register 4. According to reset cancel, the mode transfer circuit 12 is closed, and the mode register 4 is set at a readout mode, and the mode is transmitted to a peripheral circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to the setting of its mode register.

[Conventional technology]

Conventionally, this type of microcomputer has a mode register for setting the operating state of peripheral circuits and setting the terminal state in order to cope with diversification of functions. A method of setting this mode register will be explained using the example shown in FIG. In the initial operation, a reset signal 101 is input to the reset circuit 1, and the CPU 2 starts operating. ROM3
An instruction for setting a mode data value in the mode register 4 is predefined in an arbitrary area. Reset signal 1
After 01 release, the program is executed and bus 102.103
, the initial value is transferred from the ROM 3 to the mode register 4 via the processor (CPU) 2, and the operating mode of the peripheral circuit 5 is set. Similarly, when changing mode register 4, RO
The program stored in M3 defines an instruction to set mode register 4, and when the program is executed, C
The setting value was transferred to the mode register 4 via the PU 2 and set therein. Note that the reading address of the ROM 3 is determined by a program counter (PC) 6, and the PC 6 is controlled by the output of an instruction decoder 7 that interprets input instructions. Also CPU
When executing 2, the RAM 8 is used for data processing via the bus 104.

[Problem that the invention seeks to solve]

Conventionally, setting and changing the mode register involved a program, so when setting the initial value, the C
It cannot be executed immediately with the initial state of the PU set,
Furthermore, changing the settings requires a long program, which increases the ROM capacity and takes a long time to process.

[Means for solving problems]

The microcomputer of the present invention is a microcomputer that executes a program stored in a ROM and transfers mode information stored in the ROM to a mode register that sets the operating state of peripheral circuits as a program counter advances. a reset circuit that outputs a reset signal, an instruction decoder that decodes a mode register setting instruction from an input instruction and outputs a mode setting signal, a program counter that outputs an address signal to the ROM, and the mode register and the ROM. a program counter for setting a mode register that outputs an address signal to the mode register, and a control signal generation circuit that receives the reset signal and the mode setting signal and generates a control signal when either the reset signal or the mode setting signal is generated. , a program counter select circuit that inputs the control signal and generates an address signal at the output of the mode register setting program counter when the control signal is generated, and generates an address signal at the output of the program counter at other times; , a mode transfer circuit that inputs the control signal and transfers mode information from the ROM to the mode register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is an operation timing chart of the present invention. FIG. 3 is a conceptual diagram showing the storage state on R and OM B. First, an initial value of the mode register 4 is defined in advance at a specific address on the ROMB. Next, a reset signal 101 is output from the reset circuit 1. A control signal is output by the control signal generation circuit 9 which receives this reset signal 101. The PC select circuit 10 that receives this control signal selects the mode register setting PC 11, and sets the PC (program counter) of the mode register setting PCII to the top of the ROMB where the initial value (B in Figure 3) is defined. At the same time as the address is set, the mode transfer circuit 12 opens and transfers the mode value of the ROM 3 output via the bus 102 to the mode register 4.

Specifically, the mode register 4 is set to write mode, and the ROM is set by the operation of the mode register setting PCII.
The initial value (B) defined on B is sequentially transferred from the bus 102 to the mode register 4 through the mode transfer circuit 12 to the CPU 2.
(period 201 in FIG. 2). Upon release of the reset, the mode transfer circuit 12 is closed, the mode register enters the read mode, and the mode is transmitted to the peripheral circuit 5. After that, the mode is transferred to the peripheral circuit 5. The PC (program counter) 6 operates, the CPU 2 operates, and the program is executed (period 202 in Figure 2).Furthermore, the program progresses and the next mode register setting command (A in Figure 3) is executed. ) is decoded by the instruction decoder 7 and a mode setting signal is output, and the control signal generation circuit 9 outputs a signal similar to the reset signal 101, and the control signal generation circuit 9 operates in the same way as when setting the initial value to select the PC. circuit 1
0 selects the mode register setting PC 11, sets the mode register setting PC II PC to the start address where the mode register value is defined (C in Figure 3), opens the mode transfer circuit 12, and selects the mode register setting PC II. 4 is the write mode. PC11 for mode register setting
As a result of the operation, the defined mode register value on ROM B is newly transferred to mode register 4 via bus 102 (period 203 in FIG. 2). The subsequent operation is the same as that at reset. After that, the CPU operates again and executes the program. If there is a next mode register setting command, the same process is repeated. In addition, in the example,
Although one mode register 4 is shown, it goes without saying that a case in which a plurality of mode registers 4 are provided can be treated in the same manner.

〔Effect of the invention〕

As explained above, compared to conventional microcomputers in which the mode register is set by a program via the CPU, the present invention allows the mode register value on the ROM to be directly set in the mode register at the time of reset and mode register setting command. By providing a circuit and instructions for setting, the ROM capacity can be reduced and the processing time can be further reduced. Particularly in recent years, as microcomputers have become multi-functional, they have come to have many mode registers, and it can be said that the above-mentioned effects of the present invention greatly contribute to improving the productivity of program development and improving the functionality of programs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the microcomputer of the present invention, FIG. 2 is a timing chart at the time of reset and when executing a mode register setting command, and FIG. 3 is a ROM
FIG. 4 is a block diagram showing an example of a conventional microcomputer. 1...Reset circuit, 2...CPU, 3...RO
M, 4...Mode register, 5...Peripheral circuit, 6.
...PC17...Instruction decoder, 8...RAM, 9
. . . Control signal generation circuit, 10. . . PC select circuit, 11. . . Mode register setting PC 112 . . . Mode transfer circuit. yfi2 Figure 3 Shoulder Figure 4

Claims (1)

[Claims] A reset circuit that outputs a reset signal in a microcomputer that executes a program stored in a ROM and transfers mode information stored in the ROM to a mode register that sets the operating state of peripheral circuits as the program counter progresses. an instruction decoder that decodes a mode register setting instruction from an input instruction and outputs a mode setting signal; a program counter that outputs an address signal to the ROM; and an instruction decoder that outputs an address signal to the mode register and the ROM. a program counter for setting a mode register; a control signal generation circuit that receives the reset signal and the mode setting signal and generates a control signal when either the reset signal or the mode setting signal is generated; When the control signal is generated, generating an address signal at the output of the mode register setting program counter;
At other times, the program counter select circuit generates an address signal at the output of the program counter, and the mode transfer circuit inputs the control signal and transfers mode information from the ROM to the mode register. Features a microcomputer.