JPS63317864A - Diagnosing system for image memory - Google Patents

Abstract

PURPOSE:To shorten the diagnosing time of an image memory by using an image display address as a memory address at the time of diagnosis. CONSTITUTION:At the time of diagnosis, diagnosing data is set at an image memory 4 and a diagnosing circuit 10 as memory write data. Then a picture display address is converted into a memory address and a memory control signal is converted into a write timing signal by a memory control signal converting circuit 8. The memory 4 writes the diagnosing data as the memory write data by a memory address converted from the picture display address and the write timing signal. Then the memory control signal is converted into a read timing signal and the memory 4 reads the memory read data by the read timing signal and the memory address. The circuit 10 compares the memory read data with the diagnosing data and decides the occurrence of some errors if no coincidence is obtained between both data and then outputs a deciding signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image memory diagnostic method for diagnosing the operation of an image memory in a display device that displays characters, figures, etc.

[Conventional technology]

Figure 4 shows the document title IB M Technical Re.
terenceOptions and Adapte
1 is a block diagram showing the configuration of a conventional display device configured based on the display device shown in rs Volume 2. In the figure, 1 is the system bus,
1a is a system data bus connected to system bus 1, 1b is a system address bus connected to system bus 1, and IC is a command bus connected to system bus 1. 2 is a CRT controller that generates each control signal to be described later; 2a is a CRT address bus to which a CRT address from the CRT controller 2 is sent; 2b is a memory control line to which a memory control signal from the CRT controller 2 is sent; 2C
is a video control line to which video control signals from the CRT controller are sent. 3 is a selector for selecting between the system address bus 1b and the CRT address bus 2b, and 3a is a memory address bus to which the selected signal is sent. 4 is an image memory in which video data is stored; 4a is a memory read data bus to which memory read data from the image memory 4 is sent; 5 is a parallel/serial conversion circuit that converts parallel memory read data into serial data; 5a; 6 is a video data line to which data from the parallel/serial converter circuit 5 is sent, and 6 is a video control circuit 1, 6a that creates a video signal for displaying an image on a display means (not shown, such as a CRT or liquid crystal display). A video signal line for sending a video signal to display means.

Next, the operation of this conventional display device will be explained. A memory control signal created in the CRT controller 2 based on a command inputted from the command bus 1c is outputted to the memory control line 2b, and the selector 3 is thereby connected to the system address bus 1.
The system address b is selected and outputted to the memory address bus 3a as a memory address. The image memory 4 writes the system data from the system data bus 1a to the address specified by this system address. Next, the CRT controller 2
Based on the command signal from the command bus 1c, CR
A CRT address is output to the T address bus 2a, a memory control signal is output to the memory control line 2b, and a video control signal is output to the video control line 2c. The selector 3 then selects the CRT by the memory control signal on the memory control line 2b.
The CRT address on the address bus 2a is selected and the memory address is output on the memory address bus 3a. The image memory 4 stores parallel video data (
memory read data) is output to the memory read data bus 4a. The parallel/serial conversion circuit 5 converts the memory read data into serial data and supplies it to the video control circuit 6 via the video data line 5a. The video control circuit 6 creates a video signal using the video control signal from the video control line 2C and the data from the video data line 5a, and supplies it to a display means (not shown) via the video signal line 6a. As a result, one line of images corresponding to the video data applied via the system data bus 1a is displayed on the display means. Thereafter, similar operations are performed for all lines in the display area of the display means to display one screen. By repeating and continuously performing this operation for one screen, the image continues to be displayed on the display means.

FIG. 5 is a timing chart showing the relationship among memory address signals, memory control signals, and memory read data according to this conventional method. In FIG. 5, the memory address signal indicates a CRT address signal or a system address signal output to the memory address bus 3a by the selection operation of the selector 3 in FIG. The memory control signal indicates each signal output from the CRT controller 2 to the memory control line 2b, and RAS is low.
Address select signal, CAS is column address select signal, OB is out enable signal, WE is write enable signal, and *1 is a signal from system bus 1, which is an out enable signal that becomes valid when memory 4 is accessed. and a write enable signal. Memory read data indicates a signal output from the image memory 4 to the memory read data bus 4a. For this memory read data, the CRT address signal is the CRT address bus 3.
a, and when the RAS signal, CAS signal, and OE signal are each at a low level and W E (8) is at a high level, it is output to the read data bus 4a.

[Problem that the invention seeks to solve]

By the way, in order to perform a failure diagnosis of the image memory in a display device having the above configuration, a diagnostic program of the processing system is repeatedly executed, and a system address is entered from the processing system side in order to write test data to the image memory. It is also necessary to read data from the image memory and compare this read data with test data on the processing system side. Therefore, such a conventional image memory diagnosis method has problems in that it takes a long time to diagnose and the load on the processing system increases for failure diagnosis.

This invention has been made to solve the above-mentioned problems, and aims to provide an image memory diagnosis method that can shorten the image memory diagnosis time and reduce the load on the processing system. purpose.

[Means for solving problems]

The image memory diagnosis method according to the present invention includes a step of setting for image processing (step S2), converting the screen display address of the display means into a memory address corresponding to the image memory 4, and setting this memory address. a step (step S3), and a step (steps S, 4.S5) of writing memory write data into the image memory 4 using a write timing signal obtained by converting a predetermined memory control signal for controlling the image memory 4 and a memory address; A step of reading the memory write data written to the image memory 4 as memory read data using the read timing signal obtained by converting the memory control signal and the memory address (step 36 S7), and reading this memory read data to the diagnostic circuit 10. and compares the memory read data with the diagnostic data, and if they do not match, outputs a determination signal for performing a predetermined fault diagnosis process (step S
8).

[Effect]

First, diagnostic data is set, then a screen display address is converted to a memory address, and a memory control signal is converted to a write timing signal. Image memory 4
writes the diagnostic data as memory write data using the memory address obtained by converting the screen display address and the write timing signal. Thereafter, the memory control signal is converted into a read timing signal, and the image memo I74 reads memory read data using the read timing signal obtained by converting the memory control signal and the memory address. The diagnostic circuit 10 compares the memory read data and diagnostic data, and outputs a determination signal if they do not match. A predetermined failure diagnosis process is performed based on this determination signal.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment of the invention. In FIG. 1, components corresponding to those shown in FIG. 4 are given the same reference numerals,
The explanation will be omitted.

In FIG. 1, a command decoder 7 decodes a diagnostic command sent from a processing system via a system bus 1 in order to perform a diagnostic operation on this device, and outputs a diagnostic control signal based on the decoded result to a diagnostic control line 7a. It is something to do. The memory control signal conversion circuit 8 converts the memory control signal created by the CRT controller 2 in response to the diagnostic control signal input via the memory control line 2b, and converts the memory control signal into the converted memory control line 8a. The data conversion circuit 9 outputs a control signal (write timing signal or read timing signal).The data conversion circuit 9 converts the system data from the system data bus 1a during diagnosis to create memory write data. The data is supplied to the image memory 4 via the memory write data bus 9a.The diagnostic circuit 10 compares the memory read data from the memory read data bus 4a and the memory write data from the memory write data bus 9a and determines whether they match. If not, a determination signal for performing a predetermined failure diagnosis process is output to the determination signal line 10a.

Next, referring to the flowchart shown in FIG. 2, during the operation of the image memory diagnostic method in this embodiment, diagnostic data is sent from the processing system to the system bus 1, whereby the command decoder 7 decodes the diagnostic command. death,
A diagnostic control signal is output to the diagnostic control line 7a. In step S2, diagnostic data is set in the data conversion circuit 9 via the system data bus 1a. This diagnostic data can be arbitrarily set via the system data bus 1a. The validity/invalidity of the output of this data conversion circuit 9 is controlled by a diagnostic control signal from a command decoder 7 that recognizes commands from the system bus 1. In the process at this point, the data conversion circuit 9 remains in its initial state and its output is disabled.

In step S3, the CRT address (screen display address of the display means) output to the CRT address bus 2a is Or 1+ L '-'* ny "'-'
+ Set the CRT controller 2 to operate from 0 to M. This CRT address is converted into a memory address by the selector 3 and set. Since the CRT address and the memory address of the image memory 4 correspond, the entire capacity of the image memory 4 can be accessed by accessing using the CRT address. Note that the value set in the CRT controller 2 so as to output up to M addresses varies depending on the attached memory capacity.

In this state that the CRT address can access the entire memory capacity of the image memory 4, a memory diagnostic write enable command is issued from the processing system via the system bus 1 in step S4.

This valid command is decoded by the command decoder 7 and is sent to the diagnostic control line 7a as a diagnostic control signal.
is output from. This diagnostic control signal is applied to a memory control signal conversion circuit 8 and a data conversion circuit 9. The memory control signal conversion circuit 8 converts the setting WE of the memory control signals from the CRT controller 2 based on the control of the above-mentioned diagnostic control signals.
(write enable) signal and outputs a conversion memory control signal (write timing signal) to the conversion memory control line 8a. The data conversion circuit 9 is
The output is enabled and controlled by the above diagnostic control signal.
The diagnostic data input from the system data bus 1a (set in step S2 described above) is output to the memory write data bus 9a as memory write data. Since the CRT address is used as a memory address in this way, that is, the memory address on the memory address bus 3a which is the output of the selector 3 is the CRT address selected by the control of the conversion memory control signal on the conversion memory control signal line 8a. Since it corresponds to the CRT address on the address bus 2a, diagnostic data is written to the entire memory area of the image memory 4 by accessing addresses 0 to M in step S5.

After the write is completed in this way, a memory diagnostic read valid command is generated from the processing system to the system bus 1 in step S6. This read valid command is sent to the command decoder 7.
The memory control signal conversion circuit 8. decodes the diagnostic control signal through the diagnostic control line 7a. Provided to data conversion circuit 9 and diagnostic circuit 10. As a result, the memory control signal conversion circuit 8 reconverts the above-mentioned WE multiplied signal included in the memory control signal from the CRT controller 2, that is, a converted memory control signal (read timing signal)
This conversion memory control signal is output to the conversion memory control line 8a. Further, at this time, the output of the data conversion circuit 9 is disabled by the above diagnostic control signal, and no memory write data is output to the memory write data bus 9a. Therefore, step S
At 7, the data in the image memory 4 is read by the conversion memory control signal on the conversion memory control signal line 8a and the memory address (address corresponding to the CRT address) on the memory address bus 3a. In step S8, since the diagnostic circuit 10 is effectively controlled for diagnosis by the diagnostic control signal in step S6, the memory read data (signal of the memory address bus 4a) read in step S7 and the diagnostic data (
When the output of the data conversion circuit 9 is valid, the signal is input from the memory write data bus 9a and stored, and corresponds to the memory read data to be compared. A determination signal indicating the failure of No. 4 is sent to the system bus 1 via the determination signal line 10a. Thereby, the processing system performs predetermined error handling.

On the other hand, if it is determined in step S8 that the memory read data of the read result matches the diagnostic data, the process moves to step S10 and the memory address is incremented by "1". If the increased address value is less than or equal to the maximum rMJ, the process returns from step Sll to step S7 and the same process is performed. If the address value becomes larger than rMJ, the process moves to step S12 and the system processes the memory diagnostic invalidation instruction. The diagnostic circuit 10 is controlled to disable diagnostics, and the memory diagnostic process ends in step 313.

As described above, all addresses in the image memory 4 (addresses up to CRT address M) are compared in step S8, and if all the results are the same, it is determined that there is no abnormality in the memory failure diagnosis, and the memory control signal conversion circuit 8, the processing system sends a signal to enable the memory control signal output from the CRT controller 2, and to the data conversion circuit 9, a signal is sent to enable the signal on the system data bus 1a. send a signal to. Through such processing, it is possible to reduce the number of processing steps for memory failure diagnosis in the processing system. Also, C
Since the RT address is used as a memory address, diagnosis time can be shortened.

FIG. 3 is a timing chart showing the relationship among memory address signals, memory control signals, and memory read data according to this image memory diagnostic method. In FIG. 3, components corresponding to those shown in FIG. 5 are given the same reference numerals, and their explanations will be omitted. In Figure 3, *
2 is enabled by the memory diagnostic read enable signal (command in step S4), and the memory diagnostic read enable signal (
This is a signal that is invalidated by a command from the steering knob S6), that is, a write enable signal (write timing signal) necessary for writing data to the image memory 4. This write enable signal causes the image memory 4 to
Write operation is possible when an address is input.

〔Effect of the invention〕

As described above, according to the present invention, there are a step of setting diagnostic data, a step of converting and setting a screen display address to a memory address, and a step of converting a write timing signal obtained by converting a predetermined memory control signal to a memory address. writing the memory write data to the image memory by
The step of reading the memory write data written to the image memory as memory read data using the read timing signal obtained by converting the memory control signal and the memory address, and the step of comparing this memory read data with the diagnostic data and checking whether they match. If not, the present invention includes a step of outputting a determination signal for performing a predetermined failure diagnosis process, so that the screen display address can be used as a memory address during diagnosis, thereby providing a display device without major improvements. Furthermore, even if the memory capacity may increase in the future as image resolution increases, the effects of shortening the memory diagnosis time and reducing the load on the processing system can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment of the present invention, FIG. 2 is a flowchart for explaining the operation of the image memory diagnosis method in this embodiment, and FIG. A timing chart showing the relationship between memory address signals, memory control signals, and memory read data, FIG. 4 is a block diagram showing the configuration of a conventional display device, and FIG. 5 shows the relationship between memory address signals, memory control signals, and memory read data in this conventional example. 3 is a timing chart showing the relationship with memory read data. 4... Image memory, 10... Diagnostic circuit. Agent Masuo Oiwa (2 idiots) 1 vine diagram 2 pieces

Claims (1)

[Claims] In a display device that creates a video signal based on data stored in an image memory and displays an image on a display means, diagnostic data for diagnosing the image memory is sent to the image memory and a diagnostic circuit as memory write data. a step of converting the screen display address of the display means into a memory address corresponding to the image memory and setting the memory address; and a step of converting a predetermined memory control signal for controlling the image memory. writing the memory write data to the image memory using the write timing signal and the memory address; and writing the memory write data written to the image memory using the read timing signal obtained by converting the memory control signal and the memory address. A stage of reading as read data, and providing this memory read data to the above-mentioned diagnostic circuit, comparing the memory read data and the above-mentioned diagnostic data, and outputting a judgment signal for performing a predetermined failure diagnosis process if they do not match. An image memory diagnostic method characterized by having stages.