JPS59191661A - Debugging device - Google Patents

Abstract

PURPOSE:To set freely a break point with small capacity cespite the increment of the address spece of a real device CPU by compressing said address space to the smaller value. CONSTITUTION:The 24-bit address information fed from a CPU1 is compressed to high-order 3 bits from the high-order 10 bits by a compression memory 8. In other words, an address space of 24 bits is compressed to 16 bits. When the CPU1 runs, the address information emerging at an address bus is supplied to compression memories 8 and 3 via a multiplexer 6. A certain RAM (chip) of the memory 3 is designated by the memory 8, and a break point detection signal is delivered to stop the operation of the CPU1 only when the data of 1 is read out of the designated RAM. Then the address information of a register 5 is read into a CPU2. Hereafter an operator performs a debugging job with reading/writing of a register of a memory of the broken CPU1.

Description

TECHNICAL FIELD OF THE INVENTION This invention relates to a debugging device for finding errors in a program and correcting them if necessary.

Description of the Prior Art A common debugging method is to set a break point at a desired location in a program to be debugged in advance, and then run this program on an actual machine (a device including a CPU for executing the program to be debugged). Run it, and when the set breakpoint is reached, press 1.
] By stopping the execution of Durham and reading/writing the contents of the printer register of the actual machine at this time, it is checked whether there are any errors in the instructions or data, and if necessary, they are corrected. That is what it is. Break points are set on the debug device side. Conventionally, a debug device has a register for setting a break point (address to break) and a comparison circuit that matches the address set in this register with the address output to the address bus of the actual machine. It was set up as follows. Then, the actual CP 3-U was stopped by a match signal output from the comparison circuit.

However, in this conventional device, the break
If you try to set a large number of points, you have to increase the number of break points.The number of break points that can be set is naturally limited due to the hardware configuration. Conventionally, a range break that causes a break at each step has been set by setting the upper and lower address limits of the break range in a register, but there is also a problem in that there is a limit to the number of settings that can be made.

Prior invention Therefore, the applicant has already proposed a debugging device in which there is no limit to the number of break points and ranges that can be set, and which can be easily set.

The debugging device according to the prior invention includes a memory for storing data indicating whether or not each address is a break point, corresponding to the address space of the CPU that executes the program to be debugged; means for reading said data from said memory by address information outputted to an address bus during said CP;
The present invention is characterized by having a means for determining whether or not to cause U to break.

According to this prior invention, data representing whether or not it is a break point corresponds to each address in the address space of the CPLI of the actual machine; Each 5- = 4- Since break points or break ranges can be set simply by storing them in the memory above, setting break points, etc. is easy, and there is no limit to the number of break points and ranges. It disappears completely.

This invention of the prior application will be explained in more detail according to its embodiments. In FIG. 1, there is a CPU (1) in the actual machine that executes the program to be debugged. Only the address bus is shown in FIG. 1 for simplicity. Cl for debugging also for debugging equipment:
) U(2) is provided. The debug equipment also includes memory (3) for setting break points and/or ranges (break zones), and gate circuits (4).
, a register (5), a multiplexer +1 (6) and a break point control circuit (7).

The multiplexer (6) is for selecting either the address information from the CPU (1) or the address information from the CPLJ (2>), and is controlled by the CPU (2) (control line diagram path). The input side of the multiplexer includes the address bus of CPU (1) and the address bus of CPU (2).
The output side is connected to the memory (3) by the address bus.

Each storage location (1 bit) of the memory (3) is addressed by the output of the multiplexer (6).

Memory (3) is a 1-bit memory having a bit length corresponding to the address space of CPU (1). In each storage location of this memory (3), data representing whether or not the address is a break point is stored, corresponding to the execution address of the program to be debugged or an address referenced by the program.

For example, a break point is represented by "1", and anything other than the break point is represented by OII. CPU (1) is 16
In the case of a CPU, this memory (3) is, for example, 64K x 1 bit RAM.
It is. C to the write control terminal (W) of this memory (3).
A write command from the PU (2) is input to the input terminal (IN), and data indicating whether or not it is a break point is input from the CPU (2) to the input terminal (IN).

A signal read from the output terminal (OUT) of the memory (3) is input to one input terminal of the AND circuit (4). The actual execution signal of the CPU (1) is input to the other 1/- input terminal of the AND circuit (4). The output of the AND circuit (I!l) is CP(J(2>
register (5) as a break point detection signal.
as a latch control signal, and as a control circuit (7
) as a break point detection signal. The control circuit (7) determines whether or not to stop the CPU (1) when the break point detection signal is input, and outputs a command for stopping the CPU (1) if the CPU (1) is to be stopped. The register (5) reads and temporarily stores the output (indicating the break point address) of the multiplexer (6) when the latch control signal is input from the AND circuit (4). Address information in register (5) is read into CPU (2) by the data bus.

FIG. 2 shows the debugging operation, the operation of the debugging device, and the operation of the actual machine in the order of debugging.

First, at the start of debugging, all storage locations in memory (3) are cleared to the initial state "0" (step (11)).
Address or range (zone) address (
breakpoint or range) is entered (ST
7 (12) ) o t-(7) after CPLI (2
) switches the multiplexer (6) to select the address bus of the CPU (2) and outputs a memory write command. Then, in step (12), the address specified in step (12) is output to the address bus and the data "1" is output to the input terminal (IN) of memory (3). Data "1" indicating a break point is written to the specified address or address range (step (13)).

When the CPU (1) is run (RtJN) by the operator, the CPLJ (1) executes the program to be debugged (step (14)). At this time, multiplexer (6) is set to CP by CPjJ(2).
It is configured to select the address bus of IJ(1). While the CPU (1) is running, the execution of the program to be debugged and the referenced addresses are executed by the CPU (1).
) appears on the address bus. This address information is sent through the address bus and via the multiplexer (6) to the memory (3), which memory (3) is addressed. Therefore, the data "1" or "0" stored in the addressed location of the memory (3) is read out (step (11)).
15)). Also, during the run of CPU (1), 'l-
1" level actual machine execution signal is input to the AND circuit (4), and its gate is open. Therefore, data "1" (corresponding to the "H" level signal) is read out from the memory (3). When this happens (step (16)), an "H" level break detection signal is output from the AND circuit (4).

This break detection signal is input to the control circuit (7), which causes the CPLJ (1) to stop (step (17)). The break detection signal is also input to the CPU (2), so this CPU (
2> knows that a break has occurred. The break detection signal is further sent to register (5) as a latch control signal, so
Register (5) temporarily stores address information on the address bus at that time. CPU (2) is register (5)
Read the address information stored in (step (1)
8) ).

Thereafter, in order to make the CPU (1) run again after completing the work at the register point of the broken CPU (1), the break by the control circuit (7) may be canceled by, for example, a RUN command. Then, the process returns to step (14) again. Debugging progresses by repeating steps (14) to (19).

When setting a new break point, it is sufficient to return to step (12) and write data indicating a new break point in memory (3).

As described above, in this prior invention, a break point can be set by writing 1'' to the address in the memory <3) that you want to set as a break point, and also when performing a range break, it is possible to set a break point in the address range where the break should be made. Since it is only necessary to write data ``1'''' over the area, break points or ranges can be easily set, and there are advantages in that there is no limit to the number of settings, ranges, or ranges.

Summary of the Invention However, in the debugging device of the prior invention, the actual machine CP
If the address space of U(1) becomes even larger, for example, an actual CPU with a 24-bit address space
For (1), a problem arises in that the capacity of the memory (3) must be increased accordingly.

This invention improves the above-mentioned invention of the earlier application, takes advantage of the advantages of the invention of the earlier application, and makes it possible to freely set break points with a small memory capacity even if the address space of the actual CPU becomes larger. Its purpose is to provide a debugging device.

To achieve this objective, the present invention focuses on compressing the address space of an actual CPU into a smaller address space, for example, a 24-bit address space into a 16-bit address space. In order to compress the address space, a compression circuit is provided to compress the required number of upper bits. That is, the address range to be debugged is set in advance in this compression circuit, and a break point is set in the memory for each address of the lower bits other than the above-mentioned required upper bits within the set address range, as in the earlier invention. It stores data indicating whether or not it is. If the address information output to the address bus of the real CPU is within the address range set above, the selection output will be output from the compression circuit, so at this time, the data “'1” or Ol+ will be output from the memory. is read out. When it is outside the set range, the output of the memory may be considered to be 110 I+.

That is, the debugging device according to the present invention includes a compression circuit that is provided corresponding to the address space of a CPU that executes a program to be debugged and that compresses upper required address information so as to select a required debugging range and generates a selective output. , and memory for storing data without indicating for each lower address whether it is a break point or not.
The recorded data is read from the memory using the selected output output from the compression circuit based on the address information output to the address bus during execution of the program by the CPU and the lower address of the address information. The CPLI is characterized by comprising means for reading the data, and means for determining whether or not to break the CPLI based on the read data.

Therefore, it is easy to set break points, etc., and has the advantages of the prior invention in that there is no limit to the number of break points and zones, and even if the address space of the actual CPU is large. This has the effect of requiring only a small amount of memory.

DESCRIPTION OF EMBODIMENTS 17-16- FIG. 4 shows an embodiment of the invention corresponding to FIG. 1, and FIG. 5 shows processing and operating procedures corresponding to FIG. 2. In these figures, the same parts and processes as those in FIGS. 1 and 2 are denoted by the same reference numerals, and explanations thereof will be omitted. However, in Figure 4, the actual CPU (1)
It is assumed that CPU (2) and the debugging device both have an address space of 24 bits 1 to 1.

FIG. 3 shows how address information is converted by compressing it. The 24-bit address information is divided into upper 10 bits and lower 14 bits, and the upper 10 bits are compressed into the upper 3 bits by the compression memory (8). That is, a 24-bit address space is compressed into a 16-bit address space. Compressed memory 1 q
- (8) is, for example, a 1×8 pit RAM.

In FIG. 4, the memory (3) consists of eight 8×1 bit RAMs (chips), and the address of each RAM is specified by the lower 14 bit address information from the multiplexer (6). The upper 10 bit address information from the multiplexer (6) selects (designates) any one of the RAMs in each column of the compressed memory (8) or does not designate any RAM (chip select, C8). ). Data "O11" or "1" at the location designated by the lower 14-bit address information is read from the RAM designated by the output data of the compressed memory (8).

The multi-directional buffer (9) has CPU (2> memory (8)
) is used to set compression settings.

Referring to FIGS. 4 and 5, in the initial setting, all areas of the compression memory (8) are cleared to O (step (21)). The range to be debugged is determined within the entire 24-bit address space, and this debug range is further expanded to 8 bits.
Divided into sections. Then, the range of upper 10 bit addresses representing these eight sections is set by the operator (step (22)). Then CPU(2)
The data that specifies which RAM in the memory <3) is specified for each set address (upper 10 bit address) is the data (for example, “oooo
oooo")19- is set (step (23)). Next, each RAM
(i.e. for each configured upper 10-bit address partition), the address representing the break point (and zone) is entered by the operator (
In step (12)), the CPU (2) writes data indicating whether or not it is a break point into all the RAMs in the memory (3) (step (13)). Step (22) The input processing in (12) can also be performed simultaneously by the operator.

When the CPU (1) runs, the address information appearing on its address bus is input to the compressed memory (8) and the memory (3) via the multiplexer (6) (step (
25) ). Compressed memory (8〉)
M is specified, and from this specified RAM 111 II
A break point detection signal is output only when data 20- is read out, and CPtJ (1) stops (step (2G)
(17) ).

When the debugging of a certain break point is finished (step (20)), generally the process returns to step (14) to run the CPU (1) again and proceeds to debugging the next break point, but within the predetermined debugging range. If you need to reset the break point, return to step (12), and if you want to change the debugging range, return to step (22) and set both memories (8) and (3).
The settings will be redone.

In the above embodiment, the memory (3) is composed of eight RAMs, but of course it can be composed of any other number of chips (including one) or divided areas. Although the compression circuit is constituted by a compression memory (8), it is also possible to use a decoder or the like.

[Brief explanation of the drawing]

Figures 1 and 2 show examples of the invention of the earlier application.
FIG. 1 is a block diagram of the debug device, FIG. 2 is a flow chart showing the flow of processing, operation, and debugging operations of the debug device, and FIG. 3 (A) is an explanatory diagram showing address space compression in this invention. , FIG. 3(B) is a diagram showing the configuration of the compressed memory, FIG. 4 is a detailed block diagram showing an embodiment of the present invention, and FIG. 5 is a diagram showing the processing, operation, and debugging operation of the debugging device shown in FIG. 4. It is a flow chart showing the flow. (1)...CPU of the actual machine, (2)...CPU1 of the debug device (3)...Memory, (4)...AND
Circuit, (5)...Register, (6)...Multiplexer, (7)...Break point control circuit, (8)...Compressed memory. that's all

Claims (2)

[Claims] (1) A compression circuit that compresses the upper required address information to select the desired debugging range and generates a selective output, which is provided corresponding to the address space of the CPU that executes the program to be debugged, and a break point. A memo 1 for storing data indicating whether or not there is a memory for each lower address; A debugging device comprising: means for reading the following data from the memory according to a lower address of the address information; and means for determining whether to cause the cPU to break based on successively read data. (2) The debugging device according to claim (1), further comprising a register that temporarily stores the address information when data indicating a break point is read.