JPS61115147A - Batch system of program - Google Patents

Abstract

PURPOSE:To eliminate a defective contact and to improve reliability by writing and checking table data for converting an address and a batch program in an address converting RAM and in a batch RAM, respectively, and executing a main program after no error is recognized. CONSTITUTION:Where an address signal from a CPU1 specifies a batch address, the address converting RAM8 sets the batch RAM7 to the enable state through an AND circuit 12 and an address decoder 2 to the disable state, and inhibits data output from a program ROM3. As a result, the high order bit of the address signal is transmitted from the address converting RAM8 according to the converting table data, and a corresponding block area in the batch RAM7 is selected. The CPU1 reads a batch program in a batch ROM6, and writes its contents at a batch address. The data on the read-out program is written in the batch RAM1. Thus reliability can be improved compared with a conventional system which loads a program directly from a batch ROM mounted by an IC socket, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program patching method for correcting six errors in a program using temporary means.

[Conventional technology]

Conventionally, as a method for correcting such program errors9, that is, bugs, the fixed memory IJ that stores the program
Either replace the (ROM) chip itself with a corrected one, or, if the program is in variable memory (RAM), jump at the part immediately before the bug.
) instruction, etc., but if the ROM chip is soldered, the complicated work of removing the solder, removing the old chip, replacing it with a new chip, and soldering it is very rare. While it becomes necessary,
If an IC socket is used, a large-capacity ROM will operate with it attached to the socket, which is unfavorable in terms of reliability.
Moreover, in the latter case, there is a loss in executing unnecessary jump instructions and the like.

Therefore, as a highly reliable patch method that allows the CPU to automatically modify the patch information without being aware of the patch information, it is possible to patch each part of the main program stored in the main memory, including bugs. When a patch ROM containing a 7'C hatch program is used and the area in main memory containing the above bug is addressed, the main address decoder is disabled and data is read from the main program memory. In addition to prohibiting data output,
CPU that specifies the memory area 2) Stores the address signal sound of ≧, the corresponding patch program, and converts it into an address signal that specifies a specific area on the friend patch ROM so that the patch program is read. A method has been proposed (Japanese Unexamined Patent Publication No. 1607/1983).

[Problems to be Solved by the Invention] According to such a method, one punch ROM and a corresponding address conversion ROM are required for multiple bugs spread over many memory chips for program storage. It can be dealt with simply by using ', and we can certainly expect a certain degree of effectiveness compared to the previous method.

However, with this method, if the number of batches of programs is large, it becomes necessary to replace the Hatch ROM many times, and in this case, from the viewpoint of workability, it is usually necessary to replace the
As a result of using the socket for convenience, reliability problems still remain due to the need for contact.

[Problem t-Next means to solve]

In order to solve such problems, the present invention is provided with a patch RAM and an address conversion RAM k, which are fixedly connected and are composed of memory chips, and a removable patch memory chip (ROM or RAM). In the corresponding other storage device), all portions of the main program memory including bugs are stored in advance, address 5 of friend area is stored, table data is converted to the address of a specific area on patch RAM, and the patch program is stored. If the patch memory is installed when the program is released, write the table data for address conversion mentioned above to the address conversion RAM, write the patch program to each corresponding area on the patch RAM, and write those data. Check for errors, and after confirming that there are no errors, start running the raw program.

[For production]

If an address in the 0% area containing a bug in the memory is specified, the RA for address conversion is applied to the address signal.
Punch RA corresponding to the address on M's table
The address on M is converted into an address signal corresponding to seven fingers, and instead of the program data containing the bug in the raw memory, the correctness-checked Hatch program is loaded from the connection's random patch RAM.

[*Example]

FIG. 1 is a block diagram showing an example of the present invention. In the figure, 1 is the CPU, 2 is the address decoder, and 3 is the program ROM that stores the main program.9, usually 1 CPU 1
Address signals A1 to A16 are sent from address bus 4 to address signals A1 to A16.
When the address decoder 2 sends the chip enable signal CE' to one of the chips in the program ROM 3 according to its upper bits A12 to A16. As a result, 9, the next program ROM 3 is selected, and the lower pin of the address signal is selected. A specific area designated by A1 to All is selected, and the program data stored there is output to the data bus 5 when a read signal is applied to a control signal line (not shown).

On the other hand, 6 is a patch ROM consisting of FROM configured as a removable memory chip that can be attached to an IC socket.
, 7 is fixedly connected to R for the next patch by soldering etc.
AM, 8 is also a RAM for address conversion, 9 is an address selection circuit, 10 is a flip 7a knob for mode setting, 11
is an OR circuit, 12 is an AND circuit, and 13 is an inverter.

In the above configuration, the program ROM3t! , as shown in FIG. 2, each chip contains bits A7 to A of the address signal.
It is constituted by a plurality of block areas 3A specified by ll, and each block area is further constituted by a memory area in units of 1 word, which is further specified by the lower bits of the address signal (Al-A6). Finally, in this example, each block is composed of 64 words, but such blocks can be allocated arbitrarily.

For example, if program data Y stored in the block area specified by block address B2 contains program data X stored in the block area indicated by block address B1, a bug is included. Patch program data X', Y't- whose bugs have been corrected in advance, and block address B1' in the patch RAMT.

While writing to the block area 7A specified by B2', the above program RO is written to the address conversion RAM 8.
Block addresses Bl, B2t on M3 - corresponding block 7 addresses Bl', 8 on patch RAMr
2', patch program data X', in patch RAMT instead of program data X, Y in program ROM3.
Let Y' be read. Next, this operation will be explained in detail.

First, if there is a bug in the main program stored in the program ROM 3 and a patch is required, the patch ROM 6t is loaded when the power is turned off.

The patch ROM6 contains 7' program ROMa in advance.
The address of each block area containing the above bug in,
Table data for address conversion that makes each Ku19 patch address correspond to a specific block address on the patch RAMT, patch program data corresponding to each block data including a bug, and keywords to be described later are stored in respective predetermined memory areas. It's stored in. Note that each patch address is arbitrarily allocated on the patch RAM 7. Of course, if you don't need a patch, you don't need to wear anything.

Next, when the power is turned on, a master clear signal CLR is output from an initial reset circuit (not shown). This signal is inverted and applied to the reset terminal R of the seven-rib flip-flop 10 for mode setting, and this signal is released and the mode setting flip-flop 10 is reset in the initial state. Once the Q output was used for address conversion
AM 8, and on the other hand, when the select signal S is "0" to the address selection circuit 9, the lower bits Al-Al0 t- of the input address signal are outputted.
The address conversion RAM 8 can be used as a normal RAM. Finally, if a signal of 10 is passed through the Atsys decoder 2 and sent to the logic circuit 11, the output of the WaS summation circuit 11 becomes 0, and the address conversion RAM 8 is selected.

In this state, the CPUI performs initialization processing as shown in FIG. That is, the CPU 1σ first reads a keyword from the patch ROM 6 (step 1ot). In order to confirm the existence of the patch ROM, a predetermined keyword, for example, if all bits are "1.1
Step 102)
Steps 103-1 only if the correct keyword appears
09 'i Execute.

If the keyword is not correct, it is further determined whether all bits of the data are sO'' (step 110).
), if 'o'' is 6, it means that the patch ROM & is not installed, so the initialization process will be finished.If all bits are not %O#, but it may not be the correct keyword, it will perform error processing and stop. (Step 1ll).

So, if you rarely use the correct keyword, you can
Read all the address conversion table data for converting the address information in the U patch ROM, that is, the block address containing the bug in the program ROM 3 to a predetermined address in the patch RAMT (Step 103), and save the contents to the address conversion RAM 8. Write (step 104
). Next, CPol is sent to the set terminal of the mode setting flip-flop 10 via the address decoder 2t.
j signal and set it (step 105
).

As a result, the Q output of rlJ is applied to the select terminal S of the address selection circuit 9, and the upper bits A7 to A16 of the address signal from the CPU 1 are output to the address conversion RAM 8. Q of rOJ
If the output is seen at one input of the AND circuit 12, and rOJ is added from the address conversion RAM 8 to the other input, the chip enable signal of rOJ can be sent to the patch RAM 7, and the address conversion RAM 8 now functions as an address decoder. Arrival 9, CPU
When the F-patch address is specified in the address signal from 1, the address conversion RAM 8 enables the patch RAM 7t through the AND circuit 12, and disables the address decoder 2 through the inverter 13. , prohibits data output from program ROM 3. As a result, the upper bits A'7 to A'11 of the address signal are sent out from the address conversion RAM 8 in accordance with the conversion table data, and the corresponding block area in the L batch RAM T is selected. Address If'i in block area, CPU1
The lower bit A of the address signal given 1iri from
Designated by 1 to A6K.

Next, to CPU1, to the patch program in patch ROM5! including (step 106), -'t17)
Write the contents to the bunch address (step 107).

As explained above, this data is
Written to M1.

Next, CPU1 i writes the data written to this patch address. The friend patch program stored in the patch RAM 7 is read and compared with the original written data (step 108). This is to check the validity of the next data stored in the RAM 7 for the core patch. If both data match (step 109), the initialization process is completed and the execution of the E7' elgram is started. If both data do not match, error processing is performed and the process is stopped (step 111).

To execute the main program, the program RO in FIG.
This is carried out sequentially from the PI in M3, but an address signal specifying the block area where the block data Xt containing the bug is stored is sent.
If the batch program data X' in the same block data Yt-is sent and the address signal designating the stored block area is sent, then the patch program data Y'
is loaded.

In this way, the soldering is fixedly connected by etc.
The patch program is stored in the patch RAM 7 to check its validity, and thereafter the patch program is executed from this patch RAM 7. Reliability is improved compared to the conventional method of directly loading a 10-gram tl-1 patch from the ROM.

Note that the patch programs X' and Y'i stored in each block area in the batch RAMT may be dedicated programs that directly replace program data X and Y containing bugs in the king program, or It is also possible to include all jump instructions and jump to any address.

Batch information such as memories, patch addresses, and patch programs may be stored in another storage device, such as the floppy disk 2, instead of being stored in the patch ROM 6, and written to a predetermined RAM from there.

Furthermore, the validity of the data written to the patch RAM 7 can be checked by any method, such as a checksum (ch
ecksum), parity check (parft7
Other checking methods such as check) may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, a fixedly connected patch RAM 'Z' is used, and a patch program is first written to it as mere data, its validity is checked, and thereafter Executing the patch program from this patch RAM improves reliability compared to the conventional method of directly loading the patch ROM from the patch ROM attached via an IC socket or the like. In that case, the work is to store batch information in advance in fc, ROMt.
The t*cPU itself retains the advantage of being able to use patch programs without being aware of the existence of patch memory while running the main program. Ru.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, the second figure is a diagram showing the structure of the memory space of the program ROM and patch RAM, and FIG. 3 is a flow chart showing the initialization processing operation in the CPU. 1... CPU, 2... SO address decoder, 3... program ROM, 4-Φ/φ address bus, 5-... data bus, 6... Φ buff-? ROM for use, 7...RAM for patching, 8...RAM for address conversion, 9...address selection circuit, 10...
...Flip-flop for mode setting. Patent Applicant Yamatake Honeywell Co., Ltd. Chi, Osamu Hachi Masaki Yamakawa (and 2 others) Figure 1 Procedural Amendment (Voluntary) 1. Display of the case 1982 Patent Application No. 236693 2, Name of the invention Program batch method 3, Person making the amendment Relationship with the case Patent Applicant name (name)
(666) Yamatake Newell Co., Ltd. 5, Subject of amendment (1) Amend "load" on page 5, line 18 of the specification to "execute". (2) "Load" in line 17 of page 14 of the Ministry of the Ministry of Finance is corrected to "execute". that's all

Claims (1)

[Claims] The address of each area in the main memory that stores the part containing the bug in the main program is stored in the removable patch memory, which is equipped with a fixedly connected variable patch memory and a variable memory for address conversion. Store table data and patch programs that correspond to the addresses of each area in the variable memory for address conversion, and if the patch memory is installed when the main program is executed, write the above table data to the variable memory for address conversion in advance. And after writing the patch program to the corresponding area of the patch variable memory and checking the validity of these data, the execution of the main program is started, and each area in the main memory that stores the part containing the above bug is When an address is specified, the main address decoder is disabled to prohibit data output from the main memory, and the address signal is sent to each address in the corresponding patch variable memory on the table in the address translation variable memory. 9. A program patching method characterized in that by converting an address signal into an address signal specifying an area, a corresponding patch program is executed.