JPH04155535A - Fault detecting system for information processor - Google Patents

Abstract

PURPOSE:To suppress the number of check signal lines, and to detect a fault before the address and data on a bus disagree by transmitting a check signal to a central processing unit on the other side by each central processing unit, and detecting a noncoincidence between the self-check signal and the check signal inputted from the other side. CONSTITUTION:A check signal preparing circuit 13 of a central processing unit 1-1 at a master side prepares the check signal from the values of the data of both plural inside registers 11a - 11n and a state display flip flop 12. The check signal preparing circuit 13 of a central processing unit 1-2 at a slave side prepares the check signal from the values of the data of both plural inside registers 11a - 11n and the state display flip flop 12. A noncoincidence detecting circuit 14 checks whether or not this check signal is coincident with the check signal outputted from the central processing unit 1-1 at the master side. Thus, when the noncoincidence is detected, a fault detection signal is transmitted through a fault detection signal line 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure detection method for an information processing apparatus composed of dual central processing units.

[Conventional technology]

Conventionally, this type of failure detection method uses a standby redundant configuration in which one of the two central processing units is a mask and the other is a slave, and the slave middle processing unit uses the address output from the masked central processing unit on the bus. , there was a method of comparing the data with the address and data calculated by the slave central processing unit itself.

[Problem to be solved by the invention]

The conventional failure detection method described above only compares signals output from the central processing unit to the bus, such as addresses and data, so the signals are stored in registers inside the central processing unit and flip-flops that display the status. Even if the data stored in the mask central processing unit and the slave central processing unit are different, the fault cannot be detected unless there is a difference in the address or data output to the outside.

Furthermore, even if a fault is detected, it may take some time from the time a difference occurs between the mask central processing unit and the slave central processing unit until it is actually detected as a failure, and malfunctions may be allowed during that time. It has the disadvantage of being stored away.

On the other hand, if all the data of the registers inside the central processing unit and the flip-flops that display the status are monitored between the mask central processing unit and the slave central processing unit, the above problem will disappear, but the signal line connecting the central processing units , which is impossible due to implementation constraints.

[Means to solve the problem]

The failure detection method of the present invention is a failure detection method for an information processing device configured with duplicated central processing units, in which each central processing unit of the duplicated central processing units is a self-central processing unit. check signal generation means for generating a check signal from data stored in internal registers and flip-flops that display the state and outputting it to the partner central processing unit; the check signal generated by the own central processing unit and the partner processing unit; and a discrepancy detection means for comparing the check signal input from the controller and detecting a discrepancy.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Note that FIG. 1 shows only the portions related to failure detection.

Each of the central processing units 1-1.1-2 includes registers lla to lln, a status display flip-flop 12,
A check signal generation circuit 13 that generates a check signal from the data stored in the plurality of registers lla to lln and the status display flip-flop 12 compares the check signals of the own and partner central processing units 1-1.1-2. and a mismatch detection circuit 14 that detects mismatch. In addition, each central processing unit 1-1.1-2 has an output side of its own check signal generation circuit 13 and an input side of the other party's discrepancy detection circuit 14 connected to each other via a buffer circuit 15 and a check signal line 2. The output sides of both mismatch detection circuits 14 are connected to the failure detection signal line 3 via the gate buffer circuit 16.

The central processing units 1-1, 1-2 are interconnected by an address bus and a data bus (not shown), and have a redundant standby configuration.

Next, the operation will be explained.

The two central processing units 1-1, 1-2 are switched between mask and slave by switching the external master/slave switching signal to "H" level or "L" level. An example will be explained in which the CPU 1 is set as the master (H level) and the central processing unit 1-2 is set as the slave (L level).

The mask-side central processing unit 1-1 is performing actual processing, and the slave-side central processing unit 1-2 is performing the same processing while monitoring the operation of the mask-side central processing unit 1-1. The central processing units 1 to 1 on the mask side have a plurality of internal registers l by the check signal generation circuit 13.
A check signal is created from the data values of la to 11n and the status display flip-flop 12. A specific example of the check signal generation circuit 13 may be one that performs an exclusive OR of all data values. Also, the check signal is 1
It is not limited to a book, and it is also possible to use a plurality of books.

The slave-side central processing unit 1-2 has the same internal operation as the mask-side central processing unit 1-1, and the check signal generation circuit 13 has internal registers lla-ll.
A check signal is created from the value of n and the data of the status display flip-flop 12. The mismatch detection circuit 14 checks whether this check signal matches the check signal output from the mask side central processing unit 1-1, and if a mismatch is detected at the check timing, the gate buffer circuit 16 and sends a fault detection signal to the outside via the fault detection signal line 3. Note that the gate buffer circuit 16 on the mask side does not operate because the master/slave switching signal is at the "H" level, and the failure detection signal is output only from the slave side central processing unit 1-2.

〔Effect of the invention〕

As explained above, in the present invention, each central processing unit
A check signal is generated from the data values stored in the registers inside the own central processing unit and the flip-flops that display the status, and sent to the other party's central processing unit, and the discrepancy between the own check signal and the check signal input from the other party is detected. By detecting this, the number of check signal lines between duplicated central processing units can be kept within a feasible range, and failures can be detected before addresses and data on the bus become inconsistent. There is an effect that there is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1-1.1-2...Central processing unit, 2...Check signal line, 3...Fault detection signal line, lla to 11n
...Register, 12.. Status display flip-flop, 13.. Check signal generation circuit, 14.. Mismatch detection circuit, 15.. Buffer circuit, 16.. Gate buffer circuit.

Claims (1)

[Claims] In a failure detection method for an information processing device configured with duplicated central processing units, each central processing unit of the duplicated central processing units displays registers and states inside its own central processing unit. check signal generation means for generating a check signal from data stored in a flip-flop and outputting it to a partner central processing unit; 1. A fault detection method for an information processing device, comprising a discrepancy detection means for comparing and detecting a discrepancy.