JPS62160539A - Multiplexing check system for central processing unit - Google Patents

Abstract

PURPOSE:To shorten the propagation delay of an output signal and to improve the module capacity by obtaining the output signal sent to a bus from a CPU selected by a selecting signal and obtaining an error signal from the other CPU. CONSTITUTION:A main CPU 1 closes an AND gate 17 not to perform error detection because the value of a CPU selecting signal 10 is '1'; and when a strobe signal 11 goes to '1', data is outputted to a bus 4, and the CPU 1 is operated similarly to a general CPU. Though a CPU 2 for check is operated similarly to the main CPU 1, its output is not transmitted to the bus 4 and duplex comparison error is detected. Since the selecting signal 10 passes an inverter 16 to be '1', the AND gate 17 is opened when the strobe signal 11 goes to '1'. If dissidence is detected in a comparator 15 at this time, the output signal is '1', and an error signal 18 goes to '1' through the AND gate 17 to report the error. When the duplex comparison error is detected, the faulty CPU is discriminated by an error check circuit and a diagnostic program, which are omitted in the figure, in the CPU to disconnect the faulty CPU.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a multiplexing check method for a central processing unit (hereinafter abbreviated as CPU) used to improve reliability in data processing equipment, etc. .

[Conventional technology]

Multiplexed checking schemes are often used to increase the reliability of data processing equipment. Note that most of the cases are usually duplexed, so the discussion below will be based on duplexing. The duplication check method is to duplicate a part of the device and compare the processing results to confirm that they are equal. If the comparison results do not match, it means that an error has been detected.

There are various levels of duplication (for example, duplication of computing units), but the present invention relates to CPUs, and in this case,
This is a clock synchronous type CPU duplication check method.

That is, the two CPUs operate in exactly the same way on a clock-by-clock basis, and the comparison results are checked to be equal on a clock-by-clock basis.

FIG. 4 shows an example of a conventional clock synchronous CPU duplication check system. In Figure 4, (21), (
22) are the same type of CPU, cpul and cpu2, respectively.
shall be. An input signal group (23) is commonly input to these CPUs. (24) is a group of output signals of cpul, and (25) is a group of output signals of cpu2. (26) is 2
This is a TO1 selector, and the CPU selection signal (27) selects one of the two CPUs, and the output signal is sent to the outside as the CPU output signal (28), that is, on a bus connected to a main memory (not shown), etc. Sent out. Note that the value of the CPU selection signal (28) is set semi-fixed until an error occurs. (29) is a comparator, and the output signal groups (24) and (25) of the two CPUs are compared every clock. (30) is an error signal indicating that a comparison mismatch error has occurred.

Next, the operation of the above conventional system will be explained based on FIG. Note that the input signal group (23) to each CPU includes a clock signal, a reset signal, a start signal, etc., and the two CPUs operate with the same clock and are reset in the same way by a common reset signal. , are similarly started by a common start signal.

First, an initialization microprogram is started in each CPU, and parts such as registers and RAM that are not reset by a reset signal are initialized. When this is finished, there will be two c
The internal states of the PUs will be exactly the same, and from then on the two CPUs will perform exactly the same operations every clock. After this,
Two CPU output signal groups (24) and (25) constantly
are compared every clock in the comparator (29). If a mismatch is detected in even one signal line among the output signal group, the error signal (30) becomes "1" and a duplication comparison error is reported. After this, it is checked which CPU is bad by diagnosis using the error detection logic value 1 diagnostic program that each CPU has internally, the CPU selection signal (27) is reset, and the bad CPU is selected by the 2TO1 selector. It is separated by (26).

[Problem that the invention seeks to solve]

However, the above conventional method has the following problems. First of all, the output signal of the CPU is 27O1
Since it is selected by the selector (26) and transmitted to the outside, a propagation delay occurs there, which causes a drop in performance. Second, the mechanism for duplication check, that is, the 2T01 selector 26
Since the comparator (29) and the comparator (29) are attached to the outside of each CPU, modularity is lacking. For example, one CPU in implementation
If this is mounted on one card (printed circuit board), two of these cards and another card equipped with a duplication check mechanism are required to configure the device shown in Figure 4. . Furthermore, in this card, the duplication check mechanism consumes a large number of signal pins.

The present invention has been made to solve these problems, and aims to provide a CPU multiplexing check system that reduces the above-mentioned propagation delay and has excellent modularity.

[Means for solving problems]

In the CPU multiplexing check method according to the present invention, each CPU
a first signal output control means for controlling sending of the output signal to the bus based on the selection signal; and a comparison means for comparing the input signal from the bus with the output signal and generating an error signal when they do not match. , second signal output control means for controlling the output of the error signal in the opposite direction to the first signal output control means based on the selection signal, the output being sent from the CPU selected by the selection signal to the bus; In addition to obtaining signals, it also obtains error signals from other CPUs.

[Operation] In the present invention, the CPU selected by the selection signal becomes the main CPU that outputs the output signal to the bus, and other CPUs
serves as a checking CPU that detects errors. The check CPU is originally a clock that tries to output a signal to the bus, but it doesn't actually output it to the path (the main CPU is outputting it), but instead takes in the value of the bus and outputs it to the bus. Errors are checked by comparing the expected value with the value fetched from this bus.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a clock synchronous type cp that is an embodiment of the present invention.
FIG. 2 is a block diagram showing a duplication check method of u. 1st
In the figure, (1) and (2) are the same type of cp according to the present application.
u and cpul respectively.

Let it be CPU2. (3) is a group of basic input signals such as a clock signal, a reset signal, and a start signal, which are commonly input to each of the CPUs. With these, as in the case of FIG. 4, each CPU is initialized in the same way and set to operate in exactly the same way every clock. (4) is a bus to which each of the CPUs is connected, and this bus (4) is composed of, for example, 16 data signal lines, and is a bidirectional bus. (5) and (6) are the main memory device and input/output control device connected to the bus (4), respectively;
7) and (8) are input/output devices. For example, cpul
When transferring data to the input/output device (7), it first puts the device address of the input/output device (7) on the bus (4) and transfers it to the input/output control device (6). The data is then transferred to the bus (4
) and transfer it to the input/output control device (6). This causes the input/output control device (6) to transfer this data to the input/output device (7).

FIG. 2 is a configuration diagram showing the main parts inside each of the CPUs, and cpul and CPU2 in FIG. 1 have the same configuration. In Figure 2, (9) is an output circuit that outputs an output signal and Fg data to bus (4), and (10) is a CPU
cpul and CPU shown in FIG.
2 is supplied with a signal of a different polarity from the outside. for example,
If the value of the CPU selection signal (10) of cpul is "1", then the value of the CPU selection signal (10) of CPU2 is "0", and in this case, cpul is the main CPU S
CPU2 will be the checking CPU. (1
1) is a strobe signal for outputting data to the bus (4), and (12) is an AND gate. In the main CPU, that is, the CPU whose selection signal (10) has a value of "1", the strobe signal is "1". 1'', the data from the output circuit 9 is output to the bus (4) through the AND game (12).

(13) is an input cover sofa, which transmits the input signal from the bus (4) to the input circuit (14). (15) is a comparator that compares the output signal of the input buffer (13) with the output circuit (9).
), and only when they do not match, the output signal becomes "1". (I6) is an inverter that inverts the selection signal (10), and (17) is a strobe signal (1
1) and the selection signal (1) via the inverter (16).
0) and AN for detecting duplication comparison errors by
It is a D gate, and its output signal 18 is an error signal. In addition, between the output circuit (9) and the comparator (15) or
The signal line that connects the bus (4) via the gate (12) and the signal line that connects the bus (4) and the input circuit (14) or comparator (15) via the input cover sofa (13) are Although it is shown as one signal line in the diagram, there are three bus lines (4).
If it is made up of, for example, 16 signal lines, it is also made up of 16 signal lines.

In addition, in the above, an AND gate (12) whose opening and closing are controlled by a selection signal (10), and an AND gate whose opening and closing are controlled by a selection signal (10) via an inverter (16).
The game) (17) and the comparator (15) constitute the first signal output control means, the second signal output control means, and the comparison means, respectively, in the present application.

Next, the operation of this embodiment configured as above will be explained.

Now, in the main CPU, the value of the CPU selection signal (10) is "1", so the AND gate (17) is closed and error detection is not performed, and the strobe signal (11)
When becomes "1", data is output to the bus (4) and the CPU operates like a normal CPU. The check CPU operates in the same way as the main CPU, but its output is connected to the bus (4
) and that the duplication comparison error 〇 is detected is different. That is, in the check CPU, since the value of the CPU selection signal (10) is "0", the AND gate (12) is not opened and no data is output to the bus (4).

On the other hand, since the selection signal (10) of the AND gate (17) is set to "1" via the inverter (16), when the strobe signal (11) becomes "1" (that is, the AND gate (17) is connected to the bus (4) When you try to output data) it will open. Therefore, if a mismatch is detected in the comparator (15) at this time, its output signal will become "1" and the error signal (18) will become "1" after passing through the AND gate (17), and an error will be reported. That will happen. When the main CPU sets the strobe signal (11) to rlJ and outputs data to the bus (4), the check CPU also sets the strobe signal (11) to "1" and outputs the same data to the bus (4).
4), and at this timing, inside the check CPU, the data output by the main CPU (the output of the input cover sofa (13)) and the data that it was trying to output to the bus (4) (the output circuit ( 9) are compared. When a duplication comparison error is detected, as in the case of Fig. 4, it is determined which CPU is at fault based on the contents of another error check circuit (not shown) inside each CPU, a diagnostic program, etc. , the CPU selection signal (10) is reset and the bad CPU is disconnected.

FIG. 3 shows a time chart of the duplication comparison operation. This shows how data is stored in the main memory device (5). At clock n, the strobe signal (11) of the main CPU becomes "1", and the main memory address is output from the main CPU onto the bus 4, and the main memory device (5)
will be forwarded to. At this time, the strobe signal (11) of the checking CPU also becomes "1", and the address on the bus (4) is compared with the address that the checking CPU attempts to output. Similarly, at clock n+l, the main CPU sends store data onto the bus (4), and the checking CPU compares and checks this with the store data that it intended to output.

In addition, in the conventional method shown in FIG. 4, a comparison is made for each clock, and in this embodiment, the strobe signal (11) is "1".
Although only the clocks that will be compared will be compared, this difference does not really matter.

As shown in FIG. 2, in this embodiment, the output of the output circuit (9) is transmitted to the bus (4) through only the AND gate (12), so as shown in FIG.
), the propagation delay time is reduced compared to when passing through

Furthermore, since a duplication check mechanism is provided inside each CPU, for example, if each CPU is mounted on one card, two CPUs and a duplication check mechanism can be realized with two cards. This means that in the conventional method shown in Figure 4, three cards had to be designed and manufactured: two CPU cards and a card equipped with a redundancy check mechanism, but in this embodiment, two CPU cards are required. Design/M
All you have to do is build it. Naturally, this also saves on the number of signal pins. Also, in the case of this method,
It is clear that if one more CPU is connected to the bus, a checking system with triple CPUs can be easily implemented. (In the case of FIG. 4, the external checking mechanism must be redesigned in order to change duplexing to triplexing.) Similarly, a general multiplexing check system can be easily realized.

All of these indicate improved modularity.

〔Effect of the invention〕

As described above, according to the present invention, each CPU includes a first signal output control means for controlling the sending of an output signal to the bus based on a selection signal, and compares the human input signal from the bus with the output signal. and a second signal output control means for controlling the output of the error signal in the opposite direction to the first signal output control means based on the selection signal. cpu selected by signal
to get the output signal to be sent to the bus from the other cp
Since the error signal is obtained from u, it is possible to reduce the propagation delay of the output signal and improve modularity.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a configuration diagram showing the inside of the CPU of the embodiment, Fig. 3 is a time chart showing the timing of comparison operations in the embodiment, and Fig. 4 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a conventional duplication check method. (1), (2)...cpul, cpu2 (central processing unit), (4)... bus, (5)...
・Main memory device, (10)... CPU selection signal, (11)... Strobe signal, (12)...
...AND gate (first signal output control means), (
15)... Comparator (comparison means), (16)...
...Inverter, (17) ...AND gate (second signal output control means), (18) ...
・Error signal. Note that the same reference numerals are used for the middle part of the figure or corresponding parts. Agent Masuo Ohone (and 2 others) Collection 1 Figure 423, Su
8 2nd figure +5: l'U comparator

Claims (1)

[Claims] Central processing units that operate in the same way are multiplexed, one central processing unit is selected based on a selection signal to obtain an output signal to be sent to the bus, and the output signals of each central processing unit are compared and a signal is obtained when there is a discrepancy. In the central processing unit multiplexing check method, each central processing unit is diagnosed based on an error signal generated by the central processing unit, the selection signal is controlled, and a normally operating central processing unit is selected. a first signal output control means for controlling sending of the output signal to the bus based on the selection signal; and a comparison means for comparing the input signal from the bus with the output signal and generating an error signal when they do not match. and second signal output control means for controlling the output of the error signal in a manner opposite to that of the first signal output control means based on the selection signal, the error signal being sent to the bus from the central processing unit selected by the selection signal. 1. A multiplexing check method for a central processing unit, characterized in that it obtains an output signal from another central processing unit and also obtains an error signal from another central processing unit.