JPH04111144A - Coincidence control system for multiplex device - Google Patents

Abstract

PURPOSE:To improve the reliability of a highly reliable system with use of a multiplex system storage by performing the coincidence processing for the equivalent restoration with a cluster to which an interruption is reported. CONSTITUTION:A system storage SSUO stores the data given from a cluster and then reads out this data via a control circuit. An equivalent damage error detection circuit EDaO detects an equivalent damage error when no write is carried out to the write request given from a cluster CLEO. This detecting result of the EDaO is applied to an equivalent damage error transmission circuit ETC. An equivalent damage error report circuit ERbO is connected to the ETC and receives the detecting result of the EDaO. The ERbO receives the output signal (error report) given from an ETC' via an ERb'2 and also receives the output signal given from C and outputs these signals to the CLEO. Mean while an ERb'1 outputs the output signal applied to the ETC and C' via an ERb'3 to a cluster CLE1. So is with the clusters 2 and 3.

Description

[Detailed Description of the Invention] [Summary] Regarding a coincidence control method for a multiplexed storage device in which system storage devices are multiplexed to guarantee stored data, this paper aims to improve the reliability of a high-multiplying system using multiplexed SSUs. In order to further improve the coherence control method of multiplexed storage devices, in a complex system consisting of a plurality of clusters each having at least a central processing unit, and a multiplexed system storage device shared by the clusters, an equipartite damage detection means for detecting a loss of equivalence of a system storage device that has been standardized; and an equipartite damage report for sending a detection result of the equivalence damage detection means to at least one cluster of the plurality of clusters. and means.

[Industrial application field]

The present invention relates to a complex system in which system storage devices are provided for a plurality of clusters, and more particularly to a consistency control method for multiplexed storage devices in which system storage devices are multiplexed to ensure stored data.

[Prior art] With the development of computer processing technology, central processing units (C
PU), a channel processing unit (CHP) that controls channel data transfer, a main memory unit (MSU), a main memory control unit (MCU) that controls main memory access of the processing unit and the interface with the channel processing unit, etc. SCMP consists of multiple clusters and a system storage unit (SSU) that can be accessed arbitrarily from the multiple clusters.
(System Coupled Multi Pro
cessor) has been put into practical use. In this SCMP, data is multiplexed to ensure system data. FIGS. 8 and 9 are configuration diagrams of SCMP having multiplexed SSUs.

In Figures 8 and 9, four clusters (CLEO-
ClF3) shares two SSUs (SSUO3SUI) to form a high reliability redundant storage system.

In the A type shown in FIG. 8, the cluster CLEO,
For writing from CLEI, the same data is written to 5SUO and the same data is written to SSU 1 via that interface.

Also, cluster CLE2. CLE3 stores the same data in 5SUI and also stores the same data in 5SUO via its interface.

In the B type shown in FIG. 9, each cluster C
LEO-CL3 has two ports connected to 5SLIO and 5SUI, and when storing data, it outputs from each port and stores the same content in 5SUO and 5SUI.

In order to obtain high reliability, it is common practice to multiplex storage areas, but multiplexing within a single storage device does not prevent the failure of that device due to other factors. can't deal with it. For this reason, as mentioned above (in the current SCMP, two SS
U (SSUO.

5SUI) are duplicated as storage areas that hold the same contents, and the system is configured to continue operating even if one SSU is disconnected due to a failure or the like.

[Problems to be Solved by the Invention] As described above, the reliability of the system is increased by duplication using two SSUs. However, due to this duplication, writing is possible on both 5SU (SSUO, 5SUI).
), and high-speed processing cannot be expected. For this reason, in the current SCMP, hardware supports an instruction for writing to two SSUs at the same time with one instruction to increase the speed.

In the SCMP configuration diagrams shown in FIGS. 8 and 9, high speed is similarly enhanced by hardware. In other words, in type A, when a write command is issued from a cluster, both SSUs are
The SU is accepted and the same content is written to both SSUs. In addition, in type B, with the dual write command, the cluster side issues a double write command to both SSUs, respectively, and writes the same data to both SSUs. In addition, SSU reading is performed using the control table (SSU) in each cluster.
(includes a flag indicating readability for each)
SU is specified and read.

In the above-mentioned SCMP, a mismatch may occur in the storage contents between both SSUs despite duplication. For example, (1) If a failure occurs in the cluster itself or in the SSU, data in which an error is detected in the SSU is not written to the SSU, and the error is reported to the cluster.

■ A cluster that is in the process of double writing is sent to SC by another cluster.
When disconnected from the MP, the SSU stops processing at that point and reports an address exception to the cluster.

In the above-mentioned cases ■ and ■, since one instruction writes to both SSUs, each SSU processes independently according to its own priority until the end of that instruction. When this occurs, there is a problem in that the equivalence of the stored contents between the two SSUs collapses. The state in which there is a discrepancy in the memory contents between the two SSUs due to reasons such as The problem is that it interferes with It is SCMP
This is because if a cluster is separated due to a failure or the like, another cluster will take over the processing of that cluster. This will be explained in more detail below.

When a cluster is separated for some reason, the processing of the separated cluster is taken over by another cluster, and the taken over cluster reads out the inherited data from one SSU according to the read flag within the cluster.

For example, if it specifies 5SUO, the content is read from 5SUO and processing is performed using that content. On the other hand, 5suo may be separated from SCMP due to some reason such as maintenance. When this takeover cluster is performing its processing with the contents of 5SUO, this 5S
When a UO detachment occurs, the cluster is separated from the other 5
It attempts to rewrite the read flag and continue processing with the content read from 5sui, assuming that the SUI has the same information. However, as mentioned above, the inherited contents are
■ Due to the reason, equal personality damage occurs and the data is 5SUO and 5
There is a mismatch with SU1, and it becomes impossible to continue the process.

In other words, in the multiplexing system for high reliability mentioned above, in order to take over processing between clusters, it is necessary to ensure equivalence that the memory contents are always the same among 350 clusters, but equivalence is not guaranteed. was damaged and the process had to be stopped.

Furthermore, if ■ and ■ occur, for example, there is a mismatch in the stored contents between 350, so some kind of process must be performed to restore equivalence.

However, in SCMP, SS
Even if the above-mentioned ■ and ■ occur when writing to U at the same time, it is not possible to determine whether it is a double write instruction using the error report, and the current interface cannot report that the equivalence has been broken. had.

The object of the present invention is to provide a matching control method for multiplexed storage devices that further improves the reliability of a high-reliability system using multiplexed SSUs.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The present invention relates to a decoding system comprising a plurality of clusters each having at least a central processing unit, and a multiplexed system storage shared by the clusters.

The equivalence damage detection means 3 detects that the equivalence of the multiplexed system storage devices 2 has been lost.

The equivalent damage reporting means 4 sends the detection result of the equivalent damage detecting means 3 to at least one cluster of the plurality of clusters. For example, this equivalence damage reporting means 4 sends the detection results to all clusters.

(Function) When one of the multiplexed system storage devices 2 becomes defective in writing due to, for example, a failure, the equivalence damage detection means 3 detects that the equivalence of the system storage devices 2 has been lost. The equivalence damage reporting means 4 sends the detection result to at least one cluster of the plurality of clusters.
Send to all clusters. This report allows the cluster to recognize the damage to equivalence, so it can, for example, disconnect one of the multiplexed system storage devices 2, or perform processing to ensure the restoration of equivalence.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram of the A type of SCMP according to the embodiment of the present invention, and FIG. 3 is a block diagram of the SCMPOB type according to the embodiment of the present invention. The system storage device 5SUO has a memory circuit that stores data from the cluster and a control circuit (both not shown) that controls it. Basically, data from the cluster is stored in this memory circuit under the control of the control circuit. remember,
Furthermore, when reading data, it is read out via a control circuit. In addition to these circuits, the system storage ssu.

5SUI includes equivalence damage error propagation circuits c, c' and equivalence damage error detection circuits ao-a3. a'0 to a'3
and equivalent damage error reporting circuit bo-b3b'0~b'
It has 3. In addition, the equivalence damage error propagation circuit c, c
', which will be described later, is composed of circuits divided into circuits corresponding to each cluster. These equivalence damage error detection circuits ao-a3 a' 0 to a' 3 are provided corresponding to the clusters CLEO to CLE3, respectively, and respond to requests such as write from each cluster CLEO-CLE3. An equivalence damage error is detected when a write is not performed. Equivalence damage error detection circuits aO to a3. The results detected by a' O to a3 are applied to the equivalence damage error propagation circuits c and c'.

Equivalence damage error reporting circuits bO-b3. b'0~b'
3 are connected to the equivalence damage error propagation circuits c, c', and the equivalence damage error detection circuits aO to a3. a'
The detection results of O to a'3 are applied to the corresponding equivalence damage error reporting circuit. In addition, the equivalence damage error reporting circuit bo
, bi, b' o, b' ■ is cluster CLEO~C
Connected to LE3, equivalence damage error reporting circuit bO
The output signal (error report) from the equivalence damage error propagation circuit C' is passed through the equivalence damage error report circuit b'2, and the output signal from the equivalence damage error propagation circuit C is added and output to the cluster CLEO. . Furthermore, the equivalence damage error reporting circuit b'1 outputs output signals applied from the equivalence damage error propagation circuit C and the equivalence damage error propagation circuit C' via the equivalence damage error reporting circuit b'3 to the cluster CLE1. . Further, signals are outputted to clusters 2 and 3 in a similar manner.

In the case of FIG. 3, the equivalence damage error detection circuits aO to a3. a' O to a' 3 are similarly provided,
Equivalence damage error reporting circuit blo~b13. b' 1
0-b' 13 is connected to the equivalent damage propagation circuits c and c' and corresponds to the equivalent damage propagation circuits c and c', respectively.
Add error reports from to the cluster separately. Cluster CLEIO has equivalence damage error reporting circuits blo, b'
12 outputs are added. The cluster 11 also includes an equivalence damage error reporting circuit bll, b' 13. The cluster CLE12 includes an equivalence damage error reporting circuit b12. b'
10. The cluster CLE13 has an equivalence damage error reporting circuit b13. The output of b'11 is added. In type A, clusters CLEO to CLE3 detect that an equivalence damage error has occurred by one error report,
For this purpose, the equivalence damage error reporting circuits bO, bl, b'
0. b' 1 combines two errors and reports them to the cluster in one line.

On the other hand, in type B, clusters CLEIO to CLE
13 has two ports, inputs information from each of the equivalence damage error reporting circuits, and collectively recognizes that an equivalence damage error has occurred within the cluster.

In the past, since there was no such report, it was not possible to determine the equivalent damage error, but the equivalent damage error detection circuits aO to a3. a'0 to a'3 and equivalence damage error reporting circuits bO to b3, b' O to b' 3.
blo~b13. The equivalent damage errors are reported by b'10 to b'13.

FIG. 4 shows an equivalence damage error detection circuit a according to an embodiment of the present invention.
o-a3. It is a circuit diagram of a'0 to a'3 and equivalent damage error propagation circuits c and c'. The equivalence damage error detection circuit aO has a plurality of error detection circuits 30, and no matter which error detection circuit 30 detects an error, the OR gate 3
1 to output that an error has occurred. The output of this OR gate 31 is added to the AND gate 32 and outputs an error when it is a double write instruction, but does not output an error when it is not a double write instruction. The embodiment of the present invention is for multiplexing (duplexing), and since the equivalence damage error detection signal is output only during duplication, the gate is turned off by the AND gate 32 when it is not a double write command, and the detection signal is output. I'm trying not to output it.

On the other hand, an online signal is applied to the determination input of the C latch 33 and the AND gate 34 by the cluster CLEO. Also, a double write command is added to the AND gate 34, an online signal is added from the cluster CLEO to the AND gate 34, and when it is a double write command, the AND gate 34 outputs a pulse, and this pulse causes the AND gate 34 to output a pulse. It is stored in the C latch 35. That is, when an error occurs in a double write instruction, the C latch 35
Outputs an equivalence damage error detection signal corresponding to EO.

The above-mentioned equivalence damage error detection circuits a1 to a3a'
1 to a'3 are similar to the equivalent damage error detection circuits aO, and are provided corresponding to the clusters CLE1, CLE2, and CLEa, respectively. Note that errors are reported to the corresponding cluster in the same way as before.

The equivalence damage error detection signal is a signal that reports that equiindividuation is lost due to signal damage, and in the equivalence damage error propagation circuit C for CLEI, the equivalence damage error detection signal
3 excluding the output of the equivalence damage error detection circuit a1 for I
i.e. for cluster CLEO, for CLE2, for CL
The output for Ea is added to the equivalence damage error propagation circuit CLEI.

The aforementioned three signals, ie, the three signals excluding the equivalence damage error detection signal of the corresponding equivalence damage error detection circuit, are added to the OR game) 41 and OR-added. and,
It is applied to AND gate 42 along with the ON LINE signal of cluster CLEI. Cluster CLE1
The gate is turned on by the on-line signal, and the above-mentioned equivalence damage error detection signal is applied to the clock synchronization circuit H via the OR gate 41 and the AND gate 42.

Clock synchronization circuit H includes C latch 43 . to which the output of AND gate 42 is applied. C latch 44. It is added to the series circuit of C latch 45, and the outputs of C latch 43 to G latch 45 are applied to C latch 47 via OR gate 46. The C latch 47 is connected to the AND gate 4 by the output of the OR gate 46.
The level of the second output is captured and stored. In the circuit according to the embodiment of the present invention, two types of clocks CLOCKG and CLOCKG are used.
LOCKC, the C latch takes in input data with the clock CLOCKG, and the C latch takes in input data with the clock CLOCKC. The C latch 33 mentioned above has one clock CLO.
This is a register for generating a bus with a width of CKG, and C
Latches 43, 44, 45 and OR gate 46 are delay circuits for enabling C latch 47 when three clocks CLOCKG time equivalent damage error detection signals are applied.

The output of C latch 47 is applied to OR gate 48.

In addition, a cluster CLE1 equivalence damage error detection signal (added from the equivalence damage error detection circuit CLEI) is added to the OR gate 48, and when one of these signals goes to H level, the other three is stored and the signal is set to H level after an error occurs via an OR gate. The output of the OR gate 48 is 2
It is applied to the AND gate 51 via the C-latches 49 and 50 of the stage.

This latch has G clock CLOCKG as clock CLO
This is a circuit for converting a clock to CKC.

The output of a C latch 55, which will be described later, is applied to the inverting input terminal of the AND gate 51. When the output of the C latch is at L level, the AND gate 51 is turned on, and the C latch 52 is turned on.
Import the results into . Then, an equivalence damage report for the SSU is output to another circuit, for example, the second 5SUI. Further, the second output of the C latch 52 is the AND gate 5
It has joined 3. And Gate 53 and C Ranch 55
The AND gate 53 outputs the input signal until this signal becomes H level, and the C latch 55 stores it through the AND gate 54 through this loop, so it is equivalent. Stores sexual injury report data (H level).

Further, the output of C latch 52 is applied to AND gate 54. The other inverting input of AND gate 54 has cluster C.
The busy signal J of EL 1 and the stored data of the local SSU error storage circuit M of the equivalence damage error reporting circuit B are added, and its output becomes the output of the C latch 52 when the cluster CLEI is not busy and there is no local SSU error. It will be at the same level. The C latch 55 takes in this signal and outputs it to the equivalent damage error reporting circuit B. That is, the next clock CLO when the C latch 52 becomes H level
CKC causes C latch 55 to memorize its level, and as a result, C launch outputs an equivalence damage report during one clock pulse.

These AND gates 55 and 56 are turned on by the L level output from the C latch 63 in the equivalence damage error reporting circuit, which will be described later. When error reporting circuit B stores that signal, it turns off. This and gate 54
, 56 are turned off, the output of the C latch 55 is set to L level and the data is cleared.

Further, the equivalence damage error reporting circuit B is supplied with the busy signal of cluster 1.

Through the above-described operation, the C latch 52 stores an equivalence damage report to other SSUs, and the C latch 55 stores an equivalence damage error signal.

Through the above operations, the signal detected by the equivalence damage error detection circuit a is applied to the equivalence damage error propagation circuit C, is stored, and is applied to the equivalence damage error reporting circuit B.

FIG. 5 is a circuit diagram of the equivalence damage error reporting circuit and its peripheral circuits. Equivalence damage error reporting circuit B is local S
It has an SU error storage circuit M and a remote SSU error storage circuit N. These memory circuits M and N include AND gates 61 and 62, a C latch 63, an AND gate 64,
Consisting of 65 and C Ranch 66. and gate 61, 62
The RELET-LSSU-ERROR signal is input to the inverting input of AND gates 64 and 65, and the RESET-LSSU-ERROR signal is input to the inverting input of
Since the R3SU-ERROR signal is added and these signals are at L level when not being reset, AND gates 61, 62, and 64.65 are turned on. An equivalence damage error signal is applied to the inverting input of the AND gate 61, and since the AND gate 61 is on at this time, the signal is applied to the C latch 63, and its output is input again via the AND gate 62. This stores the equivalence damage error signal. Also, the AND gate 64 has 5S
An equivalence damage report from the UI is added, and when it is not a reset, the output is also added to the C latch 66, and the C
The output of latch 66 is also applied to the input via AND gate 65 and is consequently stored in this C latch 66.

Incidentally, the AND gates 64 and 65 have a signal n representing the type.
1 is added to each, and when it is type A, it becomes 1 and 5
Store equivalence damage reports from SUI. In case of type B, this level nl is 0, so ant gate 64.
65 are turned off and they are not stored. As mentioned above, the C latch 6 is connected to the inverting inputs of the AND gates 54 and 56.
3 is added, and when the C latch 63 stores the H level of the equivalence damage error signal, it becomes H level, turns off the AND gates 54 and 56, and outputs the
Reset the contents of.

The outputs of C latches 63 and 66 are applied to AND gate 68 via OR gate 67. Also, and gate 68
The output of the NOR gate 69 is added to the other input. This Noah Gate 69 has cluster CLEI's BUSY
The signal and the output of the C latch 7071 are added. C latches 70 and 71 store O, that is, output H level when VALID1 and VALID2 are both at L level and not BUSY. In other words, the AND gate 67 is turned on when BUS Y (and neither error is stored), and the error from the local and remote SSU error storage circuits M and N added via the OR gate 67 is output. .

By outputting this error, the error can be detected by C launch 70.
71 shifts. The output of the C latch 70.71 is applied to the selector 72.73, which selects one of them by 5SC-ID and outputs the RESET-LSSU-ERR signal, R
Output as ESET-R3SU-ERR signal.

In addition to this, the output of the AND gate 68 is added to the OR gate 73, and if any of the signals added is an error, it is applied to the C latch 75. The C latch 75 stores this error and outputs the cluster C as an equivalence damage error signal.
Output to LE 1.

Although the above-mentioned operation has been described for cluster CLEI, signals are outputted to other clusters by similar circuits.

The above-mentioned operation will be explained in more detail.

For example, as shown in Fig. 4, when an instruction from cluster CLEO causes an error in SSU from which side, for example, 5suo, it is detected by each error detection circuit in SSU, and the error is OR-added to other equivalence damage error propagation circuits. join. In addition, for disconnection by other clusters, each cluster uses SCMP
This is done by detecting the fall of an online signal in the request control unit of each cluster in the SSU, which indicates whether or not it is incorporated into the system.

During CLEO's double write command, when at least one of the above errors is detected, the error detection signal of the equivalence damage error detection circuit a turns on, and all the equivalence damage error propagation circuits other than the one corresponding to it are turned on. Report the error to C. A signal obtained by ORing the detection signals of other clusters is synchronized by the clock synchronization circuit H with the clock of the cluster example in which an error is to be reported. The SSU has a latch circuit that operates with its own clock. The C latch mentioned above is G
The clock is CLOCKG, and the C latch is CLOCKG.
This is a launch circuit that operates with LOCKC. or gate 4
The clock of the launch 47 is inhibited and controlled by the output h1 of 6 to synchronize its detection signal.

In the figure, the BUSY signal J exists corresponding to a cluster and is a signal indicating that an operation between the clusters is being executed. In the embodiment of the present invention, equivalence damage occurs only when this signal is off (L level). Report the error to the cluster,
This synchronized detection signal at L is temporarily held at the output of the C latch 52,55. In addition, in the case of type A,
The output of the latch 52 is connected to another SSU (5S in the figure).
U1). This is because in type A, unlike type B, each cluster is directly connected to only one SSU.

The C launch 66 of the remote SSU error storage circuit N in FIG. 5 is a circuit that holds the output K from another SSU. In addition, in type B, the error is not accepted by the control line n1.

In this way, the equivalence damage error stored in the local SSU error storage circuit M and the remote SSC error storage circuit N is timed by logic P, and is reported as an equidistinction damage interrupt to cluster CLE 1 through the equivalence damage error interface. Ru.

FIG. 6 is a timing chart of equivalence damage error reporting. When this report is received by each cluster as an equal-individuality damage interrupt, the cluster performs a recovery process to make the SSUs consistent in order to eliminate the inconsistency that causes a contradiction due to the collapse of the equal-individuality between SSUs. A cluster within SCMP determines one representative through inter-cluster communication, and performs one of the following processes.

(b) If the cause is an SSU failure, and only one SSU error in FIG. 5 is on, the cluster performs processing to disconnect that SSU from the SCMP. In addition, the separated SSU is inspected and parts are replaced, and then reincorporated into the system.

(b) When the cause is a cluster failure or cluster separation during a double write instruction by another cluster, this is the case when both SSU errors in Figure 5 are on, and the SSU
Since the error itself is not a failure, the cluster performs processing to restore and guarantee equivalence.

Then, the representative cluster is first of all, for example, 5SU.
Prohibit reading of I. Next, read the contents of 5SUO and transfer the contents to both SSUs (SSUO, 5SUI)
Write to with a double write command. After this is completed, 5SU
Remove the prohibition on reading I. This restores SSU equivalence.

FIG. 7 is a processing flowchart summarizing the processing at the time of the above-mentioned equivalence damage error. Equivalence damage error occurs,
When an equal damage interrupt occurs, it is determined whether the cause is a cluster or an SSU (SL). If the cause is an SSU, first determine the representative cluster and select the SSU where the failure occurred.
Disconnect the SU from the SCMP system (S2). Then, maintenance work such as inspection and replacement of parts (S3) and re-installation of the CPM system (S4) are performed. If the cause is a cluster in the determination (Sl), or after processing S4, a representative cluster is determined and reading of one 5SLI is prohibited. For example, 5SUI is prohibited (S5).

Then, the representative cluster sequentially reads the contents of the 5SLIs and writes the same data to both SSUs using a double write command (S6). Then, the read prohibition of the 5SUI is canceled and the equivalence is restored.

By configuring the logic as in the embodiment of the present invention in this way, the equivalence of the contents in the duplicated storage devices can be maintained, and a highly reliable system can be constructed.

〔Effect of the invention〕

As described above, according to the present invention, a cluster can accurately recognize an equal individual damage state, and based on the report, an equal individual damage interrupt can be generated, and the matching process for restoring equivalence can be performed based on the cluster that has received the interrupt report. By doing this, S
The reliability of the reliable system can be improved by multiplexing SUs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a configuration diagram of SCMP (type A) according to an embodiment of the present invention. FIG. 3 is a configuration diagram of SCMP (type B) according to an embodiment of the present invention. Fig. 4 is a circuit diagram of an equivalence damage error detection circuit and an equivalence damage error propagation circuit according to an embodiment of the present invention, Fig. 5 is a circuit diagram of an equivalence damage error reporting circuit and its peripheral circuits, and Fig. 6 is an equivalence damage error detection circuit and an equivalence damage error propagation circuit. Timing chart for damage error reporting, Figure 7 is a processing flowchart for equivalent damage error, Figure 8 is a configuration diagram of SCMP (A type), Figure 9 is S
It is a block diagram of CMP (B type). 1-1-1.1-1-2...Central processing unit, 1-1.1
-2...Cluster, 2...System storage device, 3...Equivalent damage detection means, 4...Equivalent damage reporting means.

Claims (1)

[Claims] 1) At least the central processing unit (1-1-1, 1-1-2
), each having a plurality of clusters (1-1, 1-2)
and a multiplexed system storage device (2) shared by the clusters, an equivalence damage for detecting loss of equivalence of the multiplexed system storage device (2). A multiplex system characterized by comprising a detecting means (3) and an equivalent damage reporting means (4) for sending the detection result of the equivalent damage detecting means (3) to at least one cluster of the plurality of clusters. Coordination control method for conversion equipment. 2) The matching control method for a multiplexing device according to claim 1, wherein the equivalence damage reporting means (4) sends the detection results to all of the plurality of clusters. 3) At least one cluster of the plurality of clusters (1-1, 1-2) guarantees separation of one of the multiplexed system storage devices (2) or restoration of equivalence when the detection result is added. 3. The matching control method for a multiplexing device according to claim 2, wherein one of the processing is performed.