JPH10187202A - Microprocessor controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the continuous control against occurrence of a fault and also to improve a working rate and the reliability by writing the new data obtained via the processing that is carried out by a microprocessor based on the contents of a selected storage means into plural storage means at a time. SOLUTION: The control programs and data are stored in the 1st and 2nd RAM 7 and 8, and a RAM write control circuit 30 simultaneously writes the new data into both RAM 7 and 8. Thus, the control programs and data can be stored in the normal one of both RAM 7 and 8 even if one of both RAM 7 and 8 has a fault. Therefore, the normal RAM 7 or 8 can be selected by a RAM read selection circuit 25 while a short break of execution of the control program is minimized. As a result, it is possible to restore the storage contents and to perform the continuous control without using a restart system applying a resetting operation against occurrence of a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a motor drive control device for a steel rolling plant, a motor drive control device for a cooling water circulating pump in nuclear power generation, a motor drive control device for a railway vehicle, a protection relay relay control device in a power system, The present invention relates to a microprocessor control device such as a power conversion control device that requires high reliability and continuous control.

[0002]

2. Description of the Related Art Motor drive control devices for steel rolling plants, motor drive control devices for cooling water circulation pumps in nuclear power generation, motor drive control devices for railway vehicles, protection relay relay control devices in power systems, power conversion control devices, etc. Since high reliability and continuous control are required in a microprocessor control device, it is important to avoid a failure when an abnormality occurs in the microprocessor.

In recent years, the speed of microprocessors in microprocessor control devices has been increased, and it is essential to increase the speed of storage means such as a RAM in order to exhibit this high speed. This type of RAM that can operate at high speed includes a static RAM (hereinafter referred to as SRAM) and a dynamic RAM.
AM (hereinafter, referred to as DRAM) is used.

FIG. 8 is a schematic diagram showing an example of processing by such a microprocessor control device. FIG.
1A, a microprocessor 1 mounted on the microprocessor control device reads a control program from a ROM 2 and data from a RAM 3, and executes a process based on the program and the data. That is, in the microprocessor control device, the ROM 2 is applied to the control program storage area, and the RAM 3 is applied to the data storage area. The process or resulting data is RA
Written to M3.

Here, an SRAM or a DRAM is used for the RAM 3, and a transient error called a software error may occur in each of the SRAM and the DRAM. This error is caused by α rays due to α decay of uranium and thorium contained in the package material of the RAM device, and noise received from signal lines for driving the RAM.

However, a software error has nothing to do with the deterioration of the RAM. When data is written again after the error occurs, the data is erased and the RAM is restored to normal. As a method for detecting such a software error, a parity bit check method and an ECC (Error Checking &
Correction) method. The parity bit check method can detect an odd bit error. The ECC depends on the number of error corrections and the number of added detection bits.
Bit error correction and 2-bit error detection are possible.

Usually, in a microprocessor control device,
Since the RAM 3 has a small capacity and the probability of occurrence of a 2-bit error is extremely low, a parity bit check method is employed.

On the other hand, as shown in FIG.
In some cases, a high-speed RAM 4 is applied to the control program storage area instead of the ROM 2 in FIG.

When the above-described microprocessor control apparatus is applied to the above-described continuous control, the RAM 3, 4
Avoiding error failures is an important factor in improving reliability.

Therefore, in the field of continuous control, a configuration in which microprocessor controllers are multiplexed prevents failure of the entire control system when one microprocessor controller fails, thereby improving reliability. ing. In the multiplexed microprocessor controller, when detecting a software error in the RAMs 3 and 4, a parity bit check method or a sum check for determining the sum of data and determining whether the sum is in a normal state is performed. Various health check methods by the control program itself such as the above are used, and errors in the RAMs 3 and 4 are detected early.

When a software error in the RAM 3, 4 is detected, the RAM 3, 4
As a method of restoring, a restart method by reset is used, and by resetting, a microprocessor 1, which is a basic component of the microprocessor control device, a RAM,
3, 4, peripheral circuit sections and the like are initialized, and the control program is restarted.

Here, in the multiplexing, for example, in a microprocessor control device having a duplicated configuration, the microprocessor controller must be operated before the restart.
Although there is a difference depending on the program capacity and the access speed of the RAM, a time of several seconds or more is generally required.

Therefore, if a failure occurs before the restart, there is a possibility that the whole system will fail. Although this probability is extremely low, it is necessary to triple the microprocessor controller to avoid total failure.
However, such a triple configuration increases the cost of investing in the system, and therefore, there are few examples of adopting it in a system generally having a high risk.

On the other hand, when a single non-multiplexed microprocessor control device is used for a motor drive device or the like,
Since the control cycle is set to about 1 ms, abnormal data may be written to the data storage area even if resetting is performed by the restart method when an error occurs.

For this reason, there is a possibility that a failure of the entire control system or a down of the system is caused.
Also, in a single microprocessor controller, RAM
When a failure occurs in the data storage areas 3 and 4, the RAM
Since there is no way to recover the error, it is necessary to stop the operation of a single microprocessor controller in order to prevent the failure from spreading to the entire system.

Normally, the entire control system is configured to minimize damage even if the operation of a single microprocessor controller in which a failure is detected is stopped. For example, in a vehicle equipped with a single microprocessor controller 1 of four wheels that is not extremely multiplexed, even if one of the microprocessor controllers 1 stops operating due to a failure, the remaining normal microprocessors 1 The whole vehicle can be run by wheels equipped with a processor control device. However, even in a single microprocessor control device that is not multiplexed, continuous control can be performed as long as an abnormality due to a failure in the RAM can be avoided, and the operation rate and reliability can be improved.

[0017]

As described above, the conventional microprocessor control apparatus has a problem that the operation is stopped when a fault is continuously detected in a short time. Further, when multiplexing is performed more than duplication, there is a problem that cost and hardware mounting space increase.

The present invention has been made in view of the above circumstances, and has a microprocessor control that can continuously control a failure and improve the operation rate and reliability even with a single microprocessor configuration. It is intended to provide a device.

A second object of the present invention is to provide a microprocessor control device which can reduce the cost and the space for mounting hardware by using a single microprocessor.

[0020]

According to a first aspect of the present invention, there is provided a microprocessor control apparatus for controlling an object to be controlled based on processing by a microprocessor. A first storage unit in which a control program to be executed is stored, a second storage unit in which a control program in the first storage unit and data obtained as a result of executing processing by the microprocessor are stored; A third storage unit in which the contents of the second storage unit are stored, a selection unit that selects the second storage unit or the third storage unit when the microprocessor executes processing, and a selection unit that is selected by the selection unit. Writing new data obtained as a result of the processing performed by the microprocessor based on the contents of the storage means into the second storage means and the third storage means at the same time. A microprocessor controller having a write control unit.

Therefore, the invention corresponding to claim 1 is the second invention.
The control program and data are stored in the storage means and the third storage means, and the write control means stores new data in the second storage means.
The control program and data are stored in the normal storage unit even if a failure occurs in one of the second storage unit and the third storage unit because the data is simultaneously written into the storage unit and the third storage unit. Since the instantaneous interruption of the execution of the control program can be minimized, the other normal storage unit can be selected by the selection unit.

Therefore, when a failure occurs, the stored contents can be restored and continuous control can be performed without using the restarting method by resetting, so that the operation rate and reliability can be improved.

In addition, the provision of the second storage means and the third storage means enables the whole to be realized without multiplexing.
Cost and hardware mounting space can be reduced.

According to a second aspect of the present invention, in the microprocessor control apparatus according to the first aspect, when the control program in the first storage is read out, the writing control means executes the control program. Is simultaneously written into the second storage means and the third storage means.

Therefore, the invention according to claim 2 has the same effects as those of claim 1, and furthermore, when the control program in the first storage means is read, the control program is directly stored in the second storage means. Since the data is written to both the third storage means at the same time, the rewrite operation to the second and third storage means is unnecessary.

Therefore, even when the failure is recovered by using the restart method by resetting, the restart can be performed at high speed, so that the operation rate and the reliability can be improved. Further, the invention according to claim 3 is a microprocessor control device according to claim 1 or 2, wherein when an abnormality is detected in the second storage means or the third storage means, the abnormality is detected. The abnormal area in the storage means
Is a microprocessor control device provided with data recovery means for recovering based on the contents of the storage means.

Therefore, the invention according to claim 3 provides the first effect when the abnormality area of the storage means in which the abnormality is detected is small, in addition to the operation and effect according to claim 1 or 2.
Since the different area is restored based on the contents stored in the storage means, continuous control can be realized, and the operation rate and reliability can be further improved.

Further, the invention corresponding to claim 4 is:
4. The microprocessor control device according to claim 1, wherein the selection unit selects a normal third storage unit when an abnormality is detected in the second storage unit. It is a control device.

Therefore, the invention corresponding to claim 4 is the second invention.
When an abnormality is detected in the storage means, the selection means stops selecting the abnormal second storage means and selects the normal third storage means, so that the microprocessor refers to the normal control program and data. Process can be executed.

Therefore, continuous control can be realized, and the operation rate and reliability can be improved in the same manner as the operation and effect according to any one of the first to third aspects. in addition,
According to a fifth aspect of the present invention, in the microprocessor control device according to any one of the first to fourth aspects, the data recovery unit operates normally when an abnormality is detected in the second storage unit. A microprocessor control device for periodically and sequentially restoring the contents of the second storage means based on the contents of the first and third storage means during the idle time of the processing of the microprocessor by the third storage means. .

Therefore, the invention corresponding to claim 5 is the second invention.
When an abnormality is detected in the storage unit, the storage contents of the second storage unit are periodically updated based on the normal storage contents of the third and first storage units using the idle time of the processing of the microprocessor. Claims 1 to 3 for sequentially recovering
In addition to the operation and effect corresponding to any one of the above, continuous control is possible even when the abnormal region is large or when the abnormal region cannot be specified. Similarly, continuous control is possible even if abnormality is detected again. is there. Therefore, the operation rate and the reliability can be improved.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit block diagram showing a configuration of a microprocessor control device according to an embodiment of the present invention. The same parts as those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted. Is described only.

That is, as shown in FIG. 1, the microprocessor control device according to the present embodiment has a configuration in which only the RAMs 7 and 8 are duplicated without multiplexing the entirety, thereby maintaining continuous control even when a failure occurs. In order to reduce cost and mounting space, a single microprocessor 1 is provided.

The microprocessor 1 includes a ROM 6, a first RAM 7, and a second RAM via an external data bus 5.
8, the read IO register 9 and the write IO register 10 are connected to access the stored contents stored therein and execute a program. That is, the microprocessor 1 has a memory space and an IO as an external data space.
Space. Here, the memory space is ROM 6,
The first and second RAMs 7 and 8 hold information necessary for the operation of the microprocessor 1 as shown in FIG.

As shown in FIG. 2A, the ROM 6 stores an initial execution program 6a, a control program 6b, and an abnormality processing program 6c. First RAM 7
Is the control program storage area 7 as shown in FIG.
a and a data storage area 7b. Similarly, the second RAM 8 is provided with a program storage area 8a and a data storage area 8b as shown in FIG.

The initial execution program 6a is executed when the microprocessor 1 is started. Control program 6b
Describes a main control process executed by the microprocessor 1. The abnormality processing program 6c is executed when an abnormality is detected.

The IO space comprises read and write IO registers 9 and 10. The microprocessor 1
When the external data bus 5 is accessed, a bus access signal 11 and a memory / IO signal 12 are output to an address decode circuit 15, and a write / read signal 13 is output to a read / write IO register 9, 10, a RAM read selection circuit. 25, and outputs the address signal 14 to the address decode circuit 15, the ROM 6, and the first and second RAMs 7 and 8. The bus access signal 11 is a signal indicating the start of access, and the memory / IO signal 12 is a signal for determining which of memory space or IO space to access. The write / read signal is a signal indicating whether the access content is read or written, and the address signal 14 is a signal indicating the address of the read target or the write target.

The microprocessor 1 terminates the access to the external data bus 5 by inputting the bus access response signal 16 output from the address decode circuit 15.

When the bus access signal 11, the memory / IO signal 12, and the address signal 14 are input from the microprocessor 1, the address decode circuit 15 decodes the address signal 14, and operates from the decoded address and the address map stored in advance. Select the target external data space. When the ROM 6 is selected, the ROM selection signal 17
Is output to the ROM 6 and the RAM write control circuit 30, and when the first or second RAM 7, 8 is selected, the RAM selection signal 18 is output to the first and second RAM 7, 8, the RAM read selection circuit 25, the RAM write The read IO register selection signal 19 is output to the first AND circuit 21 when the read IO register 9 is selected, and is written when the write IO register 10 is selected. The IO register selection signal 20 is output to the second AND circuit 23.

The read IO register 9 is provided at an output stage of a first AND circuit 21 to which a write / read signal 13 from the microprocessor 1 and a read IO register selection signal 19 from the address decode circuit 15 are input. , A first RAM based on the output of the first AND circuit 21.
7 or the second RAM 8 to read the stored contents, and outputs a RAM read selection signal 22 indicating the selection result to the RA.
Output to the M read selection circuit 25.

The write IO register 10 is connected to an output stage of a second AND circuit 23 for inputting a write / read signal 13 from the microprocessor 1 and a write IO register selection signal 20 from the address decode circuit 15. Equipped,
When the storage contents of the ROM 6 are read, a simultaneous write instruction signal 24 for instructing the storage contents to be simultaneously written to the first and second RAMs 7 and 8 is output to the RAM write control circuit 30 and the address decode circuit 15. I do.

It should be noted that the address decode circuit 15
When reading M6, the ROM selection signal 17
Although the signal is output to the M write control circuit 30, the RAM selection signal 18 is also output by receiving the simultaneous write instruction signal 24 from the write IO register 10. This gives R
The stored contents read from OM6 are directly stored in the first and second R
AM 7 and 8.

The RAM read selection circuit 25 includes a RAM selection signal 18 from the address decode circuit 15, a write / read signal 13 from the microprocessor 1, and a read I / O signal.
The RAM read selection signal 22 from the O register 9 is input, and based on these signals 18, 13, 22, the first R
Whether to output the AM output permission signal 26 to the first RAM 7,
Alternatively, the second RAM output permission signal 27 is transmitted to the second RAM 8
Output to

The first RAM output enable signal 26 is the first RA
The reading of the storage content of M7 is permitted, and the second RAM output permission signal 27 permits the reading of the storage content of the second RAM 8.
The first and second RAM output permission signals 26 and 27 are not in the same state as each other, and when one is in the permission state, the other is in the non-permission state.

Here, the RAM read selecting circuit 25
And fourth AND circuits 28 and 29, and a third AND circuit
The circuit 28 performs a logical negation of the RAM selection signal 18 from the address decode circuit 15 and the write / read signal 13 from the microprocessor 1 and an R signal from the read IO register 9.
The logical product of the AM read selection signal 22 and the logical negation is calculated by the first RA
The signal is output to the first RAM 7 as an M output permission signal 26.
The fourth AND circuit 29 outputs the logical product of the RAM selection signal 18, the logical negation of the write / read signal 13, and the RAM read selection signal 22 to the second RAM 8 as a second RAM output permission signal 27.

On the other hand, the RAM write control circuit 30 outputs the ROM selection signal 17 from the address decode circuit 15 and R
An AM selection signal 18, a write / read signal 13 from the microprocessor 1, and a simultaneous write instruction signal 24 from the write IO register 10 are input.
The RAM write signal 31 is output to the first and second RAMs 7 and 8 based on 18, 13 and 24, respectively.

Specifically, the RAM write control circuit 30
The fifth AND circuit 32 includes fifth and sixth AND circuits 32 and 33 and an OR circuit 34. The fifth AND circuit 32 performs a logical AND operation on the logical negation of the ROM selection signal 17 and the write / read signal 13 and the simultaneous write selection signal 24. As the fifth AND circuit output signal 35 to the OR circuit 34. The sixth AND circuit 33 outputs R
The logical product of the AM selection signal 18, the write / read signal 13, and the logical negation of the simultaneous write selection signal 24 is output to the OR circuit 34 as a sixth AND circuit output signal 36. The OR circuit 34 outputs fifth and sixth AND circuit output signals 35 and 36.
As the RAM write signal 31 for the first and second R
Output to AM7,8.

Next, the operation of the microprocessor control device configured as described above will be described with reference to FIGS. Now, when the microprocessor 1 starts operating,
The initial execution program 6a of the ROM 6 is executed as shown in FIG.

First, the initial execution program 6a
The control program 6b of M6 is copied to the control program storage area 7a of the first RAM 7 and the control program storage area 8a of the second RAM 8 (s1), and the data storage area 7b of the first RAM 7 and the data of the second RAM 8 are copied. Storage area 8b
Is initialized (cleared) (s2). Here, the read R
As described above, the control program 6b of the OM 6 is directly stored in the control program storage area 7 of the first and second RAMs 7, 8.
a and 8a.

Next, the control program 6b of the ROM 6 is read (s3), the control program 6b stored in the control program storage area 7a of the first RAM 7 is read (s4), and the sum of the control program 6b is read. A check is performed (s5).

Thereafter, the execution result of this sum check is judged (s6), and when the judgment result indicates normal, the processing is shifted to the control program 6b in the first RAM 7 (s6).
7) If abnormal, an abnormal process is executed (s8), and the initial execution program 6a ends the process.

After the end of the initial execution program 6a, the control program 6b is executed. At the first stage in which the control program 6b is executed, the RAM read selection signal 22 output from the read IO register 9 indicates that data is to be read from the first RAM 7, and the microprocessor 1 controls the first RAM 7 The processing is executed based on the control program 6b stored in the program storage area 7a.

Variable data and subroutine execution data generated by the execution of the control program 6b are stored in the first R
When both the AM 7 and the second RAM 8 receive the RAM write signal 31, the data is simultaneously written into both the data storage area 7b of the first RAM 7 and the data storage area 8b of the second RAM 8. Thereby, the data storage area 7b of the first RAM 7 and the data storage area 8 of the second RAM 8
The same data exists in b.

If the microprocessor 1 detects an abnormality during the execution of the control program 6b,
The processing is shifted to the abnormality processing program 6c stored in the program 6. Table 1 shows an example of an abnormal state that can be detected by the microprocessor 1.

[0055]

[Table 1]

When the abnormality processing program 6c in the ROM 6 is executed, its execution speed is reduced, but the abnormality processing program 6c has certainty because its contents are not destroyed. FIG. 4 is a flowchart showing the flow of processing by the abnormality processing program 6c.

The abnormality processing program 6c first traces the abnormality information (s11). If the abnormality area is the control program storage area 7a of the first RAM 7 (s12), the contents of the area 7a indicating this abnormality and the ROM 6 Is compared with the contents of the same address of the control program 6b in (s1).
3).

As a result of the comparison, a mismatch area is confirmed and if the area is small (s14), the mismatch area is set to RO
It is restored by copying the contents of M6 (s15). If the abnormality is not the control program storage area 7a of the first RAM 7 but the data storage area 7b, or if the mismatch area is large or the mismatch area is not specified, the read IO register 9 immediately stores the RAM in the RAM. The read selection signal 22 is changed so as to indicate the second RAM 8, and the processing is switched so that the processing is executed by the control program 6b in the program storage area 8a of the second RAM 8 (s1).
6).

Thereafter, the control program 6b is executed again from the address indicating the abnormality (s17). If an anomaly is detected, unless the mismatch area is small,
The restoration of the first RAM 7 is executed during the idle time of the control program 6b. Specifically, the area from the control program storage area 7a to the data storage area 7b of the first RAM 7 is
The RAM 7 is restored by sequentially copying from the upper address to the lower address. The control program 6b in the ROM 6 is copied to the control program storage area 7a of the first RAM 7, and the contents of the data storage area 8b of the second RAM 8 are copied to the data storage area 7b of the first RAM 7. .

When the control program 6b stored in the control program storage area 8a of the second RAM 8 is executed and the data is stored in the data storage area 8b of the second RAM 8, this data is simultaneously stored in the first program. It is also stored in the data storage area 7b of the RAM 7.

The processing by the second RAM 8 is continued until the next abnormality is detected. FIG. 5 is a timing chart showing signal states when the control program 6b of the ROM 6 is written into the first RAM 7 and the second RAM 8.
When the control program 6b of the ROM 6 is read by the microprocessor 1, the first RAM 7 and the second R
Written to AM8.

The clock 37 is input to the microprocessor 1 and the control program 6b of the ROM 6 is stored in the first
When writing to the RAM 7 and the second RAM 8, the external data bus 5 is accessed.
Becomes the “L (low)” level (time t1).

The address signal 14 indicating the address output from the microprocessor 1 is stored in the ROM 6 and the first RAM.
7, the second RAM 8 and the address decode circuit 15.

The address decode circuit 15 operates the ROM 6 on the basis of the address signal 14 to perform the read operation by reading the ROM select signal 1 at the "H (high)" level.
7 is output.

The ROM 6 receives the "H" ROM selection signal 17
Upon receiving the data, the storage content of the address specified by the address signal 14 is read out to the external data bus 5. The microprocessor 1 outputs a "L" write / read signal 13 indicating a read operation.

The write IO register 10 outputs the first
"H" indicating that data is written to both the second RAM 7 and the second RAM 8.
Is output to the address decode circuit 15 and the RAM write control circuit 30.

Therefore, the fifth in the RAM write control circuit 30
AND circuit 32 from "L" due to logical negation
H "write / read signal 13 and" H "RO
Since the M selection signal 17 and the simultaneous write control signal 24 of “H” are input, the fifth AND circuit output signal 35 becomes “H”.
Thus, regardless of the state of the sixth AND circuit output signal 36, the RAM write signal 31 indicates "H" indicating write.
Becomes

In the first RAM 7 and the second RAM 8, "
When the RAM write signal 31 of "H" is received, the contents stored in the ROM 6 read from the external data bus 5 are stored in the address signal 1
4 (time t2).

Finally, an "L" bus access response signal 16 indicating the end of access to the external data bus 5 is output from the address decode circuit 15 to the microprocessor 1 (time t3).

FIG. 6 is a timing chart showing the states of signals when writing is instructed by the write / read signal 13 output from the microprocessor 1. This is because, for example, the microprocessor 1 controls the control program 6b.
Is executed, and a signal state in a case where data is simultaneously written to the first RAM 7 and the second RAM 8 is shown.

The clock 37 is input to the microprocessor 1, and the bus access signal 11 becomes "L" (time t4). The external data bus 5 has a first RAM 7
And a signal indicating data to be written to the second RAM 8.

The address signal 14 output from the microprocessor 1 is stored in the ROM 6, the first RAM 7, and the second RA.
M8 is input to the address decode circuit 15. The address decode circuit 15 outputs an "H" RAM selection signal 18 indicating that the RAM is operated based on the address signal 14.

Here, for example, the simultaneous write designation signal 24 output from the write IO register 10 is not “H” indicating writing to both the first RAM 7 and the second RAM 8, but the first RAM 7 And "L" which does not specify writing to both the second RAM 8 and the second RAM 8.

Then, from the microprocessor 1, "
The write / read signal 13 of H ″ is output. In this case, the sixth AND in the RAM write control circuit 30 is output.
The circuit 33 includes a RAM selection signal 18 of “H” and an “H”
And the simultaneous write control signal 24, which has been changed from "L" to "H" by logical negation, is input, so that the sixth AND circuit output signal 36 becomes "H".
As a result, the RAM write signal 31 becomes "H" indicating write regardless of the state of the fifth AND circuit output signal 35.

In the first RAM 7 and the second RAM 8, "
Upon receiving the H "RAM write signal 31, the data signal on the external data bus 5 is stored at the address indicated by the address signal 14 (time t5).

Finally, an "L" bus access response signal 16 indicating the end of access to the external data bus 5 is output from the address decode circuit 15 to the microprocessor 1 (time t6).

FIG. 7 shows the first RAM 7 or the second RAM 8
5 is a timing chart showing signal states when any one of the stored contents is read out to the external data bus 5. The clock 37 is input to the microprocessor 1, and the bus access signal becomes "L" (time t7).

The address signal 14 output from the microprocessor 1 is stored in the ROM 6, the first RAM 7, and the second RA.
M8 is input to the address decode circuit 15. The address decode circuit 15 outputs an "H" RAM selection signal 18 indicating that the RAM is operated based on the address signal 14.

The microprocessor 1 indicates a read operation.
It outputs a write / read signal 13 of "L". Here, for example, the RAM read selection signal 22 output from the read IO register 9 is "L" indicating that the first RAM 7 is selected. I do.

In this case, the third AND circuit 28 in the RAM read / select circuit 25 supplies the RAM select signal 18 of “H” and the write / read that has changed from “L” to “H” due to logical negation. Since the signal 13 and the RAM read selection signal 22 that has been changed from “L” to “H” by logical negation are input, the first RAM output enable signal 26 becomes “H”.

The fourth AND circuit 29 has "H"
RAM selection signal 18 and "L" due to logical negation
H / write / read signal 13 and “L” RA
Since the M read selection signal 22 is input, the second RAM output permission signal 27 becomes “L”.

Therefore, the first RAM 7 receiving the "H" first RAM output permission signal 26 stores the address signal 14
Is stored in the external data bus 5
(Time t8).

Finally, an "L" bus access response signal 16 indicating that access to the external data bus 5 is terminated is output from the address decode circuit 15 to the microprocessor 1 (time t9).

However, when an abnormality occurs in the first RAM 7, for example, the RAM read selection signal 22 output from the read IO register 9 is "H" indicating that the second RAM 8 is selected. Changes to

As a result, the third AND circuit 28 outputs the "L" first RAM output permission signal 26, and the fourth AND circuit 29 outputs the "H" second RAM output permission signal 27. The second RAM 8 receiving the “H” second RAM output enable signal 27 stores the address signal 14
Is stored in the external data bus 5
Output to

As described above, according to this embodiment, the control program 6b and data are stored in the first and second RAMs 7 and 8, and the RAM write control circuit 30 stores new data in the first and second RAMs. Since the data is simultaneously written into the second RAMs 7 and 8, even if a failure occurs in one of the first and second RAMs 7 and 8, the normal first RAM 7 or the second RAM 8
Since the control program 6b and the data can be stored in the RAM, the RAM read-selection circuit 25 minimizes the instantaneous interruption of the execution of the control program 6b, and the normal first R
AM 7 or the second RAM 8 can be selected.

Therefore, when a failure occurs, the storage contents can be restored and continuous control can be performed without using the restarting method by resetting, so that the operation rate and reliability can be improved. In addition, since the first and second RAMs 7 and 8 are provided, the entirety can be realized without multiplexing, cost and hardware mounting space can be reduced.

When the control program 6b in the ROM 6 is read, the control program 6b is directly written into both the first and second RAMs 7 and 8 simultaneously. All the rewriting operations are unnecessary.

Therefore, even when a failure is detected in both the first and second RAMs 7 and 8 and the failure is recovered by using the restart method by resetting, the system can be restarted at high speed. And reliability can be improved.

Further, when the abnormal area of the first or second RAM 7, 8 in which an abnormality is detected is small, the ROM 6
Since the different area is restored based on the stored contents, continuous control can be realized, and the operation rate and reliability can be further improved.

Further, the first or second RAM 7, 8
Is detected, the RAM read selection circuit 25 stops selecting the abnormal first or second RAM 7, 8 and selects the normal first or second RAM 7, 8, so that the microprocessor 1 Processing can be executed with reference to the normal control program 6b and data.

In addition, when an abnormality is detected in the first or second RAM 7, 8, the normal first or second RAM 7, 8 and the storage in the ROM 6 are utilized by utilizing the idle time of the processing of the microprocessor 1. Abnormal first or second based on content
Since the storage contents of the RAMs 7 and 8 are periodically and sequentially restored, continuous control is possible even when the abnormal area is large or when the abnormal area cannot be specified. Is possible. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0093]

As described above, according to the present invention,
Even with a single microprocessor configuration, it is possible to provide a microprocessor control device that can continuously control when a failure occurs, can improve the operation rate and reliability, and can reduce the cost and the hardware mounting space.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of a microprocessor control device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a state of a memory space in the embodiment.

FIG. 3 is a flowchart showing a flow of processing by an initial execution program in the embodiment.

FIG. 4 is an exemplary flowchart showing the flow of processing by the abnormality processing program according to the embodiment.

FIG. 5 is a timing chart showing states of signals when a control program in the ROM is written into first and second RAMs according to the embodiment;

FIG. 6 is a timing chart showing a state of a signal when writing is instructed by a write / read signal output from the microprocessor according to the embodiment;

FIG. 7 is a timing chart showing a state of a signal when reading the storage content of the first or second RAM to the external data bus in the embodiment.

FIG. 8 is a schematic diagram showing an example of processing by a conventional microprocessor control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Microprocessor 6 ... ROM 7, 8 ... RAM 5 ... External data bus 9, 10 ... IO register 11 ... Bus access signal 12 ... Memory / IO signal 13 ... Write / read signal 14 ... Address signal 15 ... Address decode circuit 16 ... Bus access response signal 17 ... ROM selection signal 18 ... RAM selection signal 19 ... IO register selection signal for reading 20 ... IO register selection signal for writing 21,23,28,29,32,33 ... AND circuit 22 ... RAM reading Select signal 24 Simultaneous write instruction signal 25 RAM read select circuit 26 First RAM output enable signal 27 Second RAM output enable signal 30 RAM write control circuit 31 RAM write signal 34 OR circuit 35 fifth AND circuit output signal 36 ... Sixth AND circuit output signal 37 ... Clock

Claims (5)

[Claims] 1. A microprocessor control device for controlling a control target based on processing by a microprocessor, wherein the first storage means stores a control program for executing processing by the microprocessor; A second storage unit in which a control program in the first storage unit and data obtained as a result of executing processing by the microprocessor are stored; a third storage unit in which the contents of the second storage unit are stored; When the microprocessor executes a process, a selection unit that selects the second storage unit or the third storage unit; and the microprocessor performs a process based on the content of the storage unit selected by the selection unit. And writing control means for simultaneously writing new data obtained as a result of the execution into the second and third storage means. Microprocessor controller, characterized in that was e. 2. The microprocessor control device according to claim 1, wherein said write control means, when a control program in said first storage means is read, stores said control program in said second storage means. And writing to the third storage means at the same time. 3. The microprocessor control device according to claim 1, wherein when an abnormality is detected in the second storage unit or the third storage unit, the storage unit in which the abnormality is detected. A data recovery unit for recovering an abnormal area in the storage unit based on the contents of the first storage unit. 4. The microprocessor control device according to claim 1, wherein the selection unit is configured to determine whether the second storage unit is normal when an abnormality is detected in the second storage unit. A microprocessor control device for selecting a storage means. 5. The microprocessor control device according to claim 1, wherein the data recovery unit is configured to execute a third normal operation when an abnormality is detected in the second storage unit. Wherein the contents of the second storage means are periodically and sequentially restored based on the contents of the first and third storage means during the idle time of the processing of the microprocessor by the storage means. Processor control unit.