KR100922409B1 - Information processing device and memory anomaly monitoring method - Google Patents

Abstract

The present invention relates to a CPU executing an OS and firmware, a plurality of memory controllers connected to the CPU, a plurality of memory controllers for controlling the writing and reading into a plurality of memories, monitoring of errors, and a plurality of memory controllers, respectively. It is an object of the present invention to provide an information processing apparatus having a memory. The memory controller sequentially reads memory regions of a plurality of memories connected to the memory controller and monitors the error regions. The firmware converts the address identified by the memory controller corresponding to the error region into a logical address determined by the OS. It is characterized by supplying to the OS.

Description

Information processing device and memory error monitoring method {INFORMATION PROCESSING DEVICE AND MEMORY ANOMALY MONITORING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus using a memory controller, and more particularly, to an information processing apparatus that performs abnormal monitoring of a memory regardless of a mounting capacity of the memory.

In recent years, as the size of a system increases, the amount of memory to be mounted increases, and high reliability is required. Detecting a memory failure point quickly is essential for maintaining high reliability with a large memory capacity. Therefore, diagnosis and monitoring of the memory are indispensable.

1 is a diagram illustrating a conventional memory monitoring. The operating system (hereinafter OS) is operating in the CPU 3. In addition, the memory 2i-2l is connected to the CPU 3.

In the conventional abnormal monitoring of the memory, the CPU monitors all the memory areas in the memory 2i-2l by an instruction from the OS. In this case, the OS performs read processing through the CPU 3 for all the regions in the mounted memory 2i-2l. The area where the read was impossible was diagnosed as an error area, and a degenerate process for excluding from the usable area is performed.

The OS maintains information of the area in which the OS itself degenerates, thereby ensuring continuity of logical addresses. In addition, the OS knows in advance the amount of memory mounted and the hardware configuration.

In such a technique in which the CPU monitors the entire memory area by the instruction from the OS, the load at the time of operation is too large in a large-scale system with a large memory capacity. Moreover, there also existed a problem that monitoring process took too much time. In order to reduce the load on the CPU, a memory monitoring in which hardware other than the CPU reads the memory area can be considered. The CPU load can be reduced by reading out the memory area and confirming whether there is an error in the read data by hardware other than the CPU.

2 is an example of memory monitoring in which hardware other than the CPU performs access to a memory area. The OS is operating in the CPU 3. The CPU 3 is connected to controllers C1 to C3 which are hardware for controlling and monitoring the memory. In addition, memories 2m and 2n are connected to the controller C1, memories 2o and 2p to the controller C2, and memories 2q and 2r are respectively connected to the controller C3.

The controllers C1 to C3 control access to the connected memory in response to a request from the OS during normal access. However, the controller C1 to C3 reads data from the memory during memory monitoring, and retains the registers when an error is detected. Notify the OS by changing a specific bit of.

Also in this case, the OS knows in advance the amount of mounting of the memory and the hardware configuration. In addition, the OS itself retains the information of the previously degenerate area, and secures the continuity of logical addresses by itself.

Here, as the hardware monitoring system for reducing the burden on the CPU, there is a technique described in Patent Document 1. This technique is to reduce the burden on the CPU by suppressing frequent interruption of the application due to the error by performing the error handling in the firmware. However, the technique described in Patent Document 1 relates to overall hardware and does not monitor the memory.

Patent Document 1: Japanese Patent Application Laid-Open No. 2000-57016

Problems to be Solved by the Invention

As shown in Fig. 2, even when abnormality monitoring of the memory is performed by hardware other than the CPU, there is a possibility that the address of the memory is changed from the address of the conventional architecture due to the expansion of the memory. In order to cope with the expansion of the memory, translation to a corresponding logical address must be performed for each architecture. However, if the OS is executed, the common OS cannot cope with all the architectures. In addition, in response to the change of the architecture by hardware, it is necessary to mount additional hardware for each architecture, resulting in an increase in cost and an increase in the number of development processes.

It is therefore an object of the present invention to provide an information processing apparatus capable of monitoring a memory in which the CPU does not directly monitor the memory, but performs a response to another architecture by means other than the OS or hardware.

Means to solve the problem

In order to solve the above problems, according to a first aspect of the present invention, a CPU for executing an OS and firmware, and a plurality of memories connected to the CPU to control writing and reading to a plurality of memories, and to monitor errors An information processing apparatus having a controller and the plurality of memories connected to each of the plurality of memory controllers, the memory controller sequentially reading memory regions of the plurality of memories connected to the memory controller, The monitoring is performed, and the firmware converts an address grasped by the memory controller corresponding to the error area into a logical address grasped by the OS, and supplies the same to the OS.

In a first aspect of the invention, in a preferred embodiment, the firmware determines whether the error area detected by the memory controller is an area detected as an error area by a previous read and excluded from the usable area. And, if previously excluded, resuming reading of the memory area is resumed.

In a first preferred aspect of the invention, in a more preferred embodiment, the firmware determines whether data in the error area can be restored, and if the data in the error area is recoverable, the memory that detected the error area. The controller is characterized in that rewriting is performed in the error area.

In a first aspect of the invention, in a more preferred embodiment, the plurality of memory controllers each independently perform error monitoring of the memory.

Further, in the second aspect of the present invention, in a preferred embodiment, a plurality of CPUs executing an OS and firmware, a plurality of CPUs connected to the CPU, control of writing and reading to a plurality of memories, and monitoring of errors A memory abnormality monitoring method in an information processing apparatus having a memory controller and the plurality of memories connected to each of the plurality of memory controllers, the method comprising: a memory region of the plurality of memories connected to the memory controller by the memory controller Reading step sequentially and monitoring the error area, and converting the address grasped by the memory controller corresponding to the error area by the firmware into a logical address grasped by the OS and supplying the address to the OS. It characterized by including a process.

In a second aspect of the invention, in a preferred embodiment, it is determined whether the error area detected by the memory controller by the firmware is an area detected by the previous read as an error area and excluded from the usable area. And a degeneracy determination step of resuming reading of the memory area if it has been previously excluded.

In the second aspect of the present invention, in a preferred embodiment, the firmware determines whether the data in the error area can be restored, and if the data in the error area is recoverable, the error area detected. The memory controller includes a restoration determination step of rewriting the error area.

effect

In the information processing apparatus of the present invention, by changing the logical address according to the architecture change by firmware, a common OS can be applied to all architectures without introducing additional hardware and causing an increase in cost or an increase in the number of development processes. Will be.

1 is a diagram illustrating a conventional memory monitoring.

2 is a diagram showing an example of memory monitoring in which hardware other than the CPU performs access to a memory area.

3 is a configuration diagram of an information processing device according to an embodiment of the present invention.

Fig. 4 is a diagram showing the configuration of the memory controller and the operation during normal access.

Fig. 5 is a diagram showing the configuration of the memory controller and the operation during memory monitoring.

Fig. 6 is a diagram showing a simple operation flow of memory monitoring in the embodiment of the present invention.

Fig. 7 is a diagram showing a detailed operation flow of memory monitoring in the embodiment of the present invention.

Fig. 8 is a diagram showing an operation flow of memory monitoring stop in the embodiment of the present invention.

Fig. 9 is a diagram showing the operation flow of error monitoring of the OS in memory monitoring in the embodiment of the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described according to drawing. However, the technical scope of the present invention is not limited to these embodiments and extends to the matters described in the claims and their equivalents.

3 is a configuration diagram of an information processing apparatus according to the embodiment of the present invention. The information processing apparatus of this embodiment has a CPU 3 and executes instructions of the OS and firmware (Firm in the drawing). The CPU 3 is connected to a plurality of memory controllers (MA in the drawing) 1a to 1d via the system controller 4. In the normal memory access, the system controller 4 converts the logical address received from the CPU 3 into memory controller addresses used in the respective memory controllers 1a to 1d. The memory controllers 1a to 1d are hardware for performing recording and reading management of the memory 2a to 2h, and memory monitoring.

Fig. 4 is a diagram showing the configuration of the memory controller and the operation during normal access. The memory controller 1 mainly consists of the memory monitoring control unit 11, the register 12, the error diagnosis unit 13, the error correction unit 14, and the memory management unit 15. In the normal access, when the OS accesses the memory 2 via the CPU 3, first, a logical address of an area to be accessed from the CPU 3 to the system controller 4 is supplied. The system controller 4 receives the logical address and converts it into a memory controller address (MAC address in the figure) on the corresponding memory controller 1. The memory manager 15 in the memory controller 1, which has been supplied with the memory controller address, accesses data of the corresponding area on the memory 2. The memory 2 supplies the data of the corresponding area to the error diagnosis unit 13 and the error correction unit 14 in the memory controller 1.

If no error exists in the data supplied from the memory 2, the data is output from the memory controller 1 and received by the OS via the CPU 3.

If an error exists in the data supplied from the memory 2, the error diagnosis unit 13 detects the error and determines whether the error can be corrected. If the detected error is incapable of correcting, the error correction unit 14 adds information called data containing an uncorrectable error and transmits the data to the OS. At that time, the error diagnosing unit 13 records in the register 12 information such as whether to correct an error, address information of an error area, and whether the error is a normal access or an error in memory diagnosis.

If the error of the supplied data is correctable, the error correction unit 14 outputs the corrected data from the memory controller 1 and supplies it to the OS via the CPU 3. At that time, the error diagnosing unit 13 records in the register 12 information such as whether to correct an error, address information of an error area, and whether an error occurs during normal access or an error during memory monitoring.

In addition, the memory monitoring control part 11 is not used in normal operation.

5 is a diagram illustrating the configuration of a memory controller and an operation during memory monitoring. The OS instructs the firmware 3 to start memory monitoring via the CPU 3. The firmware writes to the register 12 in the memory controller 1 via the CPU 3 and starts memory monitoring. The memory monitoring control unit 11, which has confirmed the recording of the register 12 from the firmware, reads out data to the memory 2 sequentially. The memory 2 supplies data corresponding to the memory controller address supplied from the memory monitoring control unit 11 to the error diagnosis unit 13 and the error correction unit 14 in the memory controller 1.

When no error exists in the data supplied to the error diagnosis unit 13, the error diagnosis unit 13 notifies the memory monitoring control unit 11 that no error exists. Upon receiving this, the memory monitoring control unit 11 accesses the memory 2 to read the next area.

If an error exists in the data supplied to the error diagnosis unit 13, the error diagnosis unit 13 determines whether the error can be corrected. The error diagnosis unit 13 then notifies the memory monitoring control unit 11 of information such as whether an error exists, whether or not the error is corrected, address information of the error area, and whether the error is a normal access or an error in memory monitoring. do. Upon receiving it, the memory monitoring control unit 11 temporarily suspends the memory monitoring. The memory monitoring control unit 11 then records the information obtained from the error diagnosis unit 13 in the register 12.

The memory controller 1 has a register 12 for exchanging information with firmware or OS. There are three types of control registers for controlling the start and stop of monitoring, such as monitoring control register RG1, restart address register RG2, and rewrite address register RG3.

The supervisory control register RG1 includes a supervisory start bit B1, a restart address bit B2, a supervisory stop bit B3, a supervisory status bit B4, a rewrite bit B5, and a rewrite reset bit B6. , Bits such as a correctable error bit B7, an uncorrectable error bit B8, a comparison error bit B9, and the like.

In the register 12 in the memory controller 1, a log register for holding error information and the like exists. There are four types of log registers: an error address register RG4, an error log register RG5, a fixed fault address register RG6, and a fixed fault log register RG7.

6 is a simple operation flow of memory monitoring in the embodiment of the present invention. In this figure, steps are described in time series from top to bottom, and the columns delimited by dashed lines indicate steps performed in the same hardware or software. Upon receiving the instruction from the OS, the firmware writes to the registers 12 of all the memory controllers 1a to 1d, and instructs the start of memory monitoring (step W1). The memory controllers 1a to 1d which have been instructed to start the memory monitoring start reading the area of the memory 2 connected to them (steps W2a to W2d). If an error is detected in the memory controller 1b (step W3b), information such as whether or not to correct the error, address information of the error area, and whether an error during normal access or an error during memory monitoring is stored in the register in the memory controller 1b. It is recorded by the memory monitoring control unit 11 in step 12 (step W4b). After the firmware accesses the information recorded in the register 12 and performs error processing (step W5b) such as checking degenerate information and rewriting instruction, memory monitoring is resumed (step W6b).

Even when an error is detected in the other memory controller (step W3c), similarly, information such as whether or not the error is corrected, address information of the error area, and whether it is an error in normal access or an error in memory monitoring is stored in the memory controller 1c. In the register 12, the memory monitoring control unit 11 writes the data (step W4c). After the firmware accesses the information recorded in the register 12 and performs error processing (step W5c) such as checking degenerate information and instructing rewriting, memory monitoring is resumed (step W6c).

The OS accesses the registers 12 of all the memory controllers 1a to 1d at regular time intervals to check whether or not an error occurs (step W7). When the occurrence of errors is confirmed in the memory controllers 1b and 1c, the firmware requests information about these errors (step W8). The firmware for which information about the error is requested accesses the memory controllers 1b and 1c in which the error has occurred, and provides information about the error to the OS (step W9). The OS receives this information and degenerates it (step W10).

Here, a rare case will be described in which two errors are detected in the same memory controller. If another error is detected by the memory controller 1b before the OS accesses the error information in step W7, the information recorded in the register 11 in step W4b is overwritten and the OS information of the error that occurred later. Get only.

7 is a detailed operation flow of memory monitoring in the embodiment of the present invention. Initially, the OS determines to start memory monitoring (step S1). At this time, the OS sends a memory monitoring start instruction I1 to the firmware via the CPU. The firmware which has received the memory monitoring start instruction I1 sets the monitoring start bit B1 of the monitoring control register RG1 in the memory controller 1 to 1 (step S2).

After determining the start of memory monitoring, the OS starts error state checking (step U1) and ends memory monitoring (step T1). However, these processes will be described later with reference to FIGS. 8 and 9.

The memory controller 1 receives that the monitoring start bit B1 of the monitoring control register RG1 becomes 1 and starts memory monitoring (step S3). The started memory monitoring can continue until the OS sends a memory monitoring stop instruction I2 to the firmware, during which the memory controller 1 reads the area of the memory (step S4), and when the entire area ends, Reading is started again at intervals (step S3).

At that time, the error diagnosis unit 13 in the memory controller 1 checks whether no error occurs in the memory 2 (step S5), and the memory monitoring control unit 11 performs memory monitoring at the time when the error occurs. It stops (step S6). Thereafter, the memory monitoring control unit 11 sets the correctable error bit B7 or the uncorrectable error bit B8 of the monitoring control register RG1 to 1 according to the type of error (step S7). The error position information is also recorded in the error address register RG4, the error log register RG5, and the like.

Next, the firmware receives that the correctable error bit B7 or the uncorrectable error bit B8 of the monitoring control register has become 1 to confirm degeneracy. The degeneracy is to exclude the error area in the memory 2 from the usable area. The firmware determines whether or not the area is already degenerate from the information recorded in the monitoring control register RG1 of the memory controller 1 or the like (step S8).

If the error area is a degenerate area, the firmware avoids the area and resumes memory monitoring (step S9). At that time, the address information of the resuming area is set in the restart address register RG2 of the memory controller 1, and 1 is set in the restart address bit B2 of the monitoring control register RG1. Receiving the information of these registers, the memory monitoring control unit 11 resumes memory monitoring.

In the case where the error area is not degenerate, whether or not the error can be restored is checked through the register 11 (step S10). Here, what is called a recoverable error describes what kind of error it is. In the present embodiment, an ECC (Error Check and Correct Memory) memory is used to realize error detection. The recoverable error refers to a soft error that occurs randomly due to a change in data stored in the memory. The soft error does not occur due to a circuit problem, but refers to a data error that does not occur again when data is modified by the error recovery function. In the error recovery function, an error is corrected based on a correction code for the detected correctable error. The correction code is a code generated inside the MAC when processing data between the MAC and the memory.

If it is a recoverable error, since it becomes possible to specify the data to be originally recorded, the firmware sends an instruction to the memory controller 1 to record the data once more (step S11). At this time, the address of the area to be rewritten is set in the rewrite address register RG3, and 1 is set in the rewrite bit of the monitoring control register RG1. Writing to these registers 11 is processed by the memory monitoring control unit 11 in the memory controller 1, and the memory monitoring control unit 11 starts to rewrite data to be originally recorded. At that time, it is again monitored whether an error occurs (step 13), and if an error occurs, it is determined that it is a fixed failure due to hardware (step S14), and the information is stored in a fixed failure address register RG6 or a fixed failure log register. It is recorded at RG7 (step S15). If an error does not occur in step S13, it is determined as a soft error. This information is recorded in the error address register RG4 or the error log register RG5 (step S15). After writing to the register 11 in step S15, the firmware instructs the memory controller 1 to resume memory monitoring (step S16).

If it is determined in step S10 that the error cannot be restored, rewriting is not performed in the error area, and the firmware instructs the memory controller 1 to resume memory monitoring (step S16).

The memory controller 1 resumes memory monitoring (step S17) and returns to the detection of the occurrence of an error (step S5). The operation flow of this memory monitoring is repeated until the stop processing of the memory monitoring is performed.

8 is an operation flow of memory monitoring stop in the embodiment of the present invention. Initially, the OS determines to stop the memory monitoring (step T1). At this time, the OS sends a memory monitoring stop instruction I2 to the firmware via the CPU. The firmware which has received the memory monitoring start instruction I2 sets the monitoring stop bit B3 of the monitoring control register RG1 in the memory controller 1 to 1 (step T2). The memory monitoring unit 11 in the memory controller 1 receives that the monitoring stop bit B3 of the monitoring control register RG1 has become 1 and stops the memory monitoring (step T3).

Fig. 9 is an operational flow of error monitoring of the OS in memory monitoring in the embodiment of the present invention. After starting the memory monitoring, the OS starts monitoring the detection state of the error (step U1). At this time, the OS sends a memory monitoring confirmation instruction I3 to the firmware via the CPU. The firmware which has received the memory monitoring confirmation instruction I3 monitors each bit of the monitoring control register RG1 in the memory controller 1 (step U2). At this time, if no error is detected, the process returns to step U1, and the confirmation of the error detection state is started again after a certain time.

If an error is detected in the memory controller 1, the OS requests error information from the firmware (step U3). Upon receiving this, the firmware creates and notifies the error information to be notified to the OS from the information stored in the register 12 of the memory controller 1 (step U4). Here, the error information is a logical address that can be grasped by the OS, and information such as whether the error is a fixed error or a soft error. Error information is notified to the OS from the firmware, and the OS performs logical address processing and the like based on this (step U5). After step U5, the process returns to step U1, and the confirmation of the detection state of the error is started again for a certain time.

Since the firmware integrates the information from all the memory controllers 1, converts the information into logical addresses, and transmits error information to the OS, the OS does not need to convert to logical addresses. The firmware also performs address translation of the error location detected by the memory controller 1 in accordance with the architecture, and provides the OS with the logical address after processing. The OS executes error processing based on the logical address received from the firmware.

In this way, by changing the logical address according to the architecture change by firmware, it is possible to apply additional hardware to apply the common OS to all architectures without causing an increase in cost or an increase in the number of development processes.

In large systems, a large amount of memory is required and high reliability is required. Detecting the point of failure of a memory quickly is essential for maintaining high reliability with a large memory, and diagnosis and monitoring of the memory are therefore indispensable. The present invention makes it possible to monitor the memory using a common OS regardless of the difference in hardware configuration.

Claims (7)

CPU running OS and firmware, A plurality of memory controllers connected to the CPU, each of which controls writing and reading into a plurality of memories and monitors errors; The plurality of memories connected to each of the plurality of memory controllers, The memory controller sequentially reads memory areas of the plurality of memories connected to the memory controller, and includes an error diagnosis unit for detecting an error of the memory and an error correction unit for correcting a correctable error among the detected errors. And a register for storing error information relating to the detected error, and a memory monitoring control unit for controlling monitoring of the memory. And said firmware converts the address grasped by said memory controller corresponding to the error area on said memory where said error occurs into a logical address grasped by said OS and supplies it to said OS. The memory device of claim 1, wherein the firmware determines whether the error area detected by the memory controller is an area that is detected as an error area by a previous read and is excluded from the usable area. The information processing apparatus which resumes reading of an area | region. The memory controller of claim 1, wherein the firmware determines whether the data of the error area is restorable, and if the data of the error area is recoverable, the memory controller that detects the error area is the error area. An information processing apparatus characterized by rewriting to. The information processing apparatus according to claim 1, wherein the plurality of memory controllers independently monitor error of the memory. CPU running OS and firmware, A plurality of memory controllers connected to the CPU and configured to control writing and reading to a plurality of memories and to monitor errors; The plurality of memories connected to each of the plurality of memory controllers, The memory controller includes an error diagnosis unit, an error correction unit, a register, and a memory monitoring control unit. A reading step of sequentially reading memory regions of the plurality of memories connected to the memory controller by a memory monitoring control section of the memory controller; An error detecting step of detecting an error of the memory by an error diagnosis unit of the memory controller; An error correction step of correcting, by the error correction unit of the memory controller, a correctable error among the detected errors; An error storing step of storing error information relating to the detected error by a register of the memory controller; And converting, by the firmware, the address grasped by the memory controller corresponding to the error area on the memory where the error occurs into a logical address grasped by the OS, and supplying the address to the OS. How to monitor memory abnormalities. 6. The method according to claim 5, wherein the firmware determines whether the error area detected by the memory controller is an area that is detected as an error area by a previous read and excluded from the usable area, and previously excluded. And a degeneracy determination step of resuming reading of the memory area, if any. The memory controller of claim 5, wherein the firmware determines whether the data in the error area is recoverable, and if the data in the error area is recoverable, the memory controller that detects the error area rewrites the error area. And a restoration judgment step of performing a memory abnormality monitoring method.

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