JPH0883218A - Computer system - Google Patents

Abstract

PURPOSE: To increase the processing speed by deciding that a memory is normal when two parity error deciding means decide that there is no parity error. CONSTITUTION: A parity check function part 2 decides that the main memory is normal when 1st and 2nd parity error deciding functions of a parity error decision part 9 decide that there is no parity error respectively. Namely, a CPU 1 decides whether or not there is a parity error after writing is completed according to bit data A read out of a written physical address and whether or not the number of '1's of parity bits is even to decide that there is a parity error when the number of '1's is odd for even parity and registers the physical address in an abnormal address table, and inverts the bit data A when it is decided that there is no parity error and generates inverted bit data A' of '10101010', thereby selecting odd parity on the basis of the value '0' of the inverted bit of the 8th digit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system capable of performing a parity check for the presence / absence of a memory abnormality, and more particularly to a computer system capable of surely detecting a parity error with only two parity checks and improving the processing speed. Regarding

[0002]

2. Description of the Related Art Recently, in the field of processing bit data of a plurality of digits, a computer system is widely used which executes a parity check on the bit data every time the bit data is written in a memory.

In this type of computer system parity check method, the parity check criterion is fixed to either even parity or odd parity. Here, a case where the parity check is performed by using 8-digit bit data “010111001” as an even parity will be described with reference to FIG.

In the first parity check, since the number of "1" s in the bit data is an even number, the sum of the number of "1" s in the parity bits and the number of "1" s in the bit data is always an even number. Thus, a parity bit of "0" is generated.

In the second parity check, the bit data is inverted to obtain the inverted bit data "1010011".
0 "is created and the parity check is performed on the inverted bit data. That is, in the second parity check, since the number of" 1 "s in the bit data is an even number as described above,
A parity bit of "0" is generated.

Further, in the third parity check,
Always "0" regardless of the number of "1" s in bit data
In order to eliminate the possibility that the parity bit is generated, the value of the 7th digit bit data is inverted (11100110) to change the number of "1" in the bit data to an odd number, Accordingly, it is checked whether the value of the parity bit is inverted to "1".

Subsequently, this type of computer system uses the above-described parity check or ECC to
If an error is detected in the main memory, the operation is stopped as a serious hardware error.

[0008]

However, in the computer system as described above, at least three data conversions are required to check the parity of one bit data, so that the processing time is reduced. is there.

Here, if the third parity check is omitted from the viewpoint of preventing the reduction of the processing time, there is a possibility that an abnormality that a constant parity bit is always generated and the reliability of error detection is lowered. There is.

When an abnormality is detected in the main memory, the operation is stopped regardless of the size of the abnormal memory capacity. Therefore, even if only one bit in one byte is abnormal, the operation is stopped. Therefore, there is a problem that the utilization rate is unnecessarily reduced.

The present invention has been made in consideration of the above circumstances, and provides a computer system capable of improving the processing speed by reducing the number of parity checks to two while maintaining the reliability of error detection. The purpose is to

A second object of the present invention is to separate an abnormal area from a physical address of the memory and continue to use only a healthy area when an abnormality is detected in the memory.
It is to improve the operating rate.

[0013]

According to a first aspect of the present invention, there is provided a computer system capable of performing a parity check for the presence / absence of abnormality in a plurality of digit bit data stored in a memory. Odd parity or even parity is determined based on the value of the bit of a certain reference digit, and a first parity bit is generated based on the determined parity reference, and the first parity bit and the bit data are the First data writing means for writing to the memory, and the first parity bit and the bit data written by the first data writing means are read from the memory, and the bit data and the first data are written. First parity error determining means for determining the presence or absence of a parity error based on a parity bit and the parity reference, and the multi-digit Todeta the bit inversion, of the inverted bit data of a plurality of digits which are the bit inversion, together with on the basis of the value of the reference significant bits, and the parity criterion determines the inverted inverted parity reference even-odd property,
Second data writing means for generating a second parity bit based on the inversion parity standard, and writing the second parity bit and the inversion bit data in the memory; and the second data writing means. A second parity bit and an inverted bit data written by the above are read from the memory, and the presence or absence of a parity error is determined based on the inverted bit data, the second parity bit, and the inverted parity reference. And a parity check executing means for determining that the memory is normal when the first and second parity error determining means respectively determine that there is no parity error. System.

The invention according to claim 2 has an address conversion table in which the correspondence between virtual addresses and physical addresses is stored, and the virtual address assigned to bit data is referred to by the address conversion table. In a computer system that converts to a physical address and writes the bit data in the memory according to the converted physical address, the error detection logic is used for the bit data to determine whether there is an abnormality in the memory in units of physical addresses, and this determination is made. When the result indicates that there is an abnormality, an abnormal address registering means for registering a physical address indicating the abnormality, and the physical address registered by the abnormal address registering means are deleted from the address conversion table, and the erased physical address is deleted. Instead of other physical addresses in the address conversion table Is a computer system comprising an abnormality address erasing means for constant.

[0015]

Therefore, according to the invention corresponding to claim 1, since the first data writing means is provided with the above means,
Of the bit data of a plurality of digits, odd parity or even parity is determined based on the value of the bit of a certain reference digit, and a first parity bit is generated based on the determined parity reference. The parity bit and the bit data are written in the memory, and the first parity error determining means reads the first parity bit and the bit data written by the first data writing means from the memory and the bit data , The presence or absence of a parity error is determined based on the first parity bit and the parity reference, and the second data writing means bit-inverts the bit data of a plurality of digits, and the bit-inverted inverted bits of a plurality of digits. Among the data, the parity reference is determined based on the value of the bit of the reference digit, and the inverted parity reference with the evenness inverted is determined. , A second parity bit is generated based on the inversion parity reference, the second parity bit and the inversion bit data are written in the memory, and the second parity error determination means is caused by the second data writing means. The written second parity bit and inverted bit data are read from the memory, and the presence / absence of a parity error is determined based on the inverted bit data, the second parity bit and the inverted parity reference, and parity check execution means is provided. However, when it is determined by the first and second parity error determination means that there is no parity error, it is determined that the memory is normal, so that the number of parity checks can be performed while maintaining the reliability of error detection. By reducing the number to twice, the processing speed can be improved.

Further, in the invention according to claim 2, the abnormal address registration means uses the error detection logic for the bit data to determine the presence or absence of an abnormality of the memory in physical address units, and the determination result indicates that there is an abnormality. At this time, the physical address indicating the abnormality is registered, and the abnormal address erasing means erases the physical address registered by the abnormal address registering means from the address conversion table, and replaces the erased physical address with another physical address. Since the address is set in the address conversion table, when an error is detected in the memory, the abnormal area can be separated from the physical address of the memory and only the healthy area can be used continuously to improve the operation rate. it can.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a computer system according to an embodiment of the present invention. This computer system has a CPU1
Are connected to the main memory 4 via the system controller 3 having the parity check function unit 2. The system controller 3 is connected to a control target (not shown) via the system bus 5. Also, CPU1
Is connected to a program storage unit 6 that stores a hardware diagnostic program including a memory diagnostic program, and an OS (basic software) 7 that has a memory management program.

The parity check function unit 2 has a data writing unit 8 and a parity error determining unit 9. The data writing unit 8 selects the bit data of a plurality of digits from among
Odd parity or even parity is determined based on the bit value of a certain reference digit, a first parity bit is generated based on the determined parity reference, and the first parity bit and bit data are stored in the main memory. Four
And the parity reference based on the value of the bit of the reference digit among the bit-inverted bit data of the plurality of digits that has been bit-inverted. The even parity inverted reverse parity criterion is determined, and the second parity is determined based on the inverted parity criterion.
Second parity bit and a second data write function of writing the second parity bit and the inverted bit data into the main memory 4.

The parity error determination unit 9 reads the first parity bit and bit data written by the first data writing function of the data writing unit 8 from the main memory 4, and at the same time, the bit data A first parity error determination function for determining the presence / absence of a parity error based on the first parity bit and the parity reference, and a second parity bit written by the second data writing function of the data writing unit, It has a second parity error determination function of reading the inversion bit data from the main memory 4 and determining the presence or absence of a parity error based on the inversion bit data, the second parity bit, and the inversion parity standard. .

The parity check function unit 2 determines that the main memory is normal when the parity error determination unit 9 determines that there is no parity error by the first and second parity error determination functions. It has a parity check execution function.

In the main memory 4, in order to convert a virtual address into a physical address, an address conversion table 10 in which a physical address corresponding to each virtual address is described and a physical address of a portion showing an abnormality in the main memory 4 are described. A memory management area for storing the abnormal address table 11 and a data storage area for storing data are formed.

The memory diagnostic program determines whether or not there is an abnormality in the main memory 4 by using an error detection logic for the bit data in units of physical addresses, and when the result of this determination indicates that there is an abnormality, the physical address indicating the abnormality is determined. The control procedure shown in FIG. 3 is described so as to be registered in the abnormal address table 11. Here, the parity check function unit 2 is used to determine whether there is an abnormality. As the error detection logic, parity check or ECC can be used.

The memory management program erases the physical address registered in the abnormal address table 11 by the memory diagnostic program from the address translation table 10, and replaces the erased physical address with another physical address in the address translation table 10. The control procedure shown in FIG. 4 is described so that the setting is performed and the operation is continued only in the healthy memory area. Further, the memory management program describes in advance the minimum value of the memory capacity at which the system can operate in order to determine whether the operation can be continued.

Next, the operation of the computer system configured as described above will be described with reference to the flowcharts of FIGS. It is to be noted that, first, a schematic operation from power-on to inspection of the main memory 4 to operation of the system will be described with reference to FIG.
Will be described in detail with reference to. Furthermore, during operation,
Processing when an abnormality occurs in the main memory 4 will be described with reference to FIG.

Now, it is assumed that the power is turned on by the operation of the operator as shown in FIG. 2 (ST1). CPU1
Activates the hardware diagnostic program and the memory diagnostic program in the hardware diagnostic program, and inspects the main memory 4 for any abnormality (ST.
2).

After the inspection is completed, the CPU 1 judges based on the memory management program whether or not the normal memory capacity is equal to or more than the minimum for system operation (ST3). If the result of this judgment is that there is no memory capacity, the system is Is stopped (ST4), and when there is a memory capacity, the OS7 is booted (ST5) and then the OS7 is started (ST4).
6).

When the OS 7 is activated, the CPU 1 separates the abnormal physical address detected by the inspection in step ST2 from the system. Therefore, the CPU 1 separates the abnormal physical address from the address conversion table 10 according to the memory management program.
In addition to erasing from the physical address, another physical address is set in the address conversion table 10 instead of the erased physical address.

After the OS 7 is activated, the CPU 1 notifies the console or error log of an abnormal physical address (ST7) to alert the operator. After that, the computer system enters a normal operating state (ST8).

Next, the inspection of the main memory 4 in step ST2 will be described in detail. The CPU 1 sets an initial value of the physical address in the main memory 4 in an address counter (not shown) via the parity check function unit 2 (ST11). Subsequently, the CPU 1 executes the first parity check by the parity check function unit 2. In the first parity check, Fig. 5 (d)
As shown in, the 8-digit bit data A "0 for inspection
1010101 ″ is prepared, and even parity is selected based on the value “0” of the bit of the eighth digit among the digits of the bit data A, for example, using the eighth digit as a reference digit. In the check, since the number of “1” s in the bit data A is an even number, the parity bit is generated as “0”, and the bit data A and the parity bit are written in the physical address based on the setting of the address counter. (ST12).

After the writing is completed, the CPU 1 executes step ST1.
The bit data A and the parity bit are read from the physical address written by 2 (ST13), and the presence or absence of a parity error is determined based on whether the number of "1" s of the bit data A and the parity bit is an even number. Shi (ST
14) If the number of "1" is an odd number for even parity, it is determined that there is a parity error, the physical address in which the parity error has occurred is registered in the abnormal address table (ST15), and the result of the determination in step ST14 ,
When it is determined that there is no parity error, the first parity check is ended and the second parity check is started.

In this second parity check, FIG.
As shown in (e), the bit data A is inverted to create the inverted bit data A ′ “10101010”, and the odd parity is selected based on the value “0” of the inverted bit at the eighth digit. That is, in the second parity check,
Similarly to the above, the number of "1" s in the bit data A'is an even number, but since odd parity is selected, the parity bit is generated as "1". Based on the setting of the address counter as described above. Then, the bit data A ′ and the parity bit are written in the physical address (ST1
6).

After the writing is completed, the CPU 1 reads the bit data A'and the parity bit from the physical address written in step ST16 (ST17), as described above.
Whether or not there is a parity error is determined based on whether or not the number of "1" s of these bit data A'and parity bits is an odd number (ST18), and "1" for odd parity.
If the number is an even number, it is determined that there is a parity error, and the process proceeds to step ST15. If the result of determination in step ST18 is that there is no parity error, the second parity check is ended.

As described above, in the second parity check, in addition to the creation of the inversion bit data A ', odd parity is selected based on the value "0" of the inversion bit, which is different from the conventional case. It is possible to check the presence / absence of an abnormality in the main memory by performing the parity check only twice while eliminating the possibility of the abnormality that it remains "0" and does not change.

Subsequently, the CPU 1 determines whether or not all the physical addresses have undergone the parity check based on the setting of the address counter. When the parity check has not been completed, the address counter is updated to set the next physical address and the step is performed. Returning to ST12 (ST20), when the parity check of all physical addresses has been completed, the memory diagnostic inspection is ended and the process proceeds to step ST3.

Next, the abnormality processing during operation in step ST8 will be described in detail. Now, it is assumed that the computer system has completed OS7 startup and is in operation (S
T8). Here, when the CPU 1 receives the bit data to be written in the main memory 4 from the CPU 1, as described above,
The parity check function unit 2 executes the parity check twice to determine whether or not a parity error has occurred (ST21). When there is no parity error, the process returns to step ST8 to continue the normal operation state, and to check the parity error. If yes, the physical address in which the parity error has occurred is registered in the abnormal address table 11 (ST2
2).

After the registration is completed, the CPU 1 executes an error process such as a flash on the data in the data storage area separated from the system by the registration in the abnormal address table 11 (ST23), and then FIG. As shown, the physical address "A" registered in step ST22
In order to separate the BCD ”from the system, for example, assuming that the physical address“ ABCD ”is included in the physical address“ EFGH ”, the abnormal physical address“ EFGH ”in the address conversion table 10 is changed to the sound physical address“ JKLM ”.
(ST24). As a result, when the CPU 1 receives a certain virtual address, the address conversion table 10
Of the physical address “J” without converting this virtual address into the corresponding physical address “EFGH”.
Since it is converted to KLM ", the abnormal physical address can be separated from the system and the operation can be continued.

FIG. 7 shows such an address conversion table 1
It is a schematic diagram for demonstrating correction of 0 as an example in the case of paging in units of 4 KB. As shown in the figure, when the physical address in the real page “1236” area is abnormal, the CPU 1 determines that the real page “123” of the virtual address 8K.
6 "is corrected to an unused real page" 1310 "to separate the abnormal physical address area (real page 1236) from the system, while the virtual address area (8K to 12K) is normal physical address area (real page 1310). To enable the system to operate.

After correction of the physical address, the CPU 1
In the same manner as described above, it is determined whether or not the normal memory capacity is equal to or higher than the minimum system operating capacity (ST25). If the result of this determination is that there is no memory capacity, system abnormal termination processing is performed to terminate the system. Execute (ST2
6) If the memory capacity is available, the operation returns to step ST8 to continue the operating state.

As described above, according to this embodiment, the CPU
In the second parity check, in addition to the creation of the inverted bit data A ′, 1 selects odd parity based on the value “0” of the inverted bit, which is different from the conventional one, so that the parity bit is “0” for the first time. It is possible to check whether or not there is an abnormality in the main memory by performing the parity check only twice while eliminating the possibility that the abnormality does not change. That is, by reducing the number of parity checks to 2 while maintaining the certainty of error detection,
The processing speed can be improved.

Further, according to this embodiment, the CPU 11 is
According to the memory diagnostic program, the presence / absence of an abnormality in the main memory 4 is determined for each physical address by using the error detection logic for the bit data. When the determination result indicates that there is an abnormality, the physical address indicating the abnormality is displayed in the abnormal address table. 11 and further deletes the physical address registered in the abnormal address table 11 from the address conversion table 10 according to the memory management program.
Since another physical address is set in the address conversion table 10 instead of the erased physical address, when an abnormality is detected in the memory, the abnormal area is separated from the physical address of the memory and only the healthy area is continued. By using it, the operation rate can be improved. In addition, the present invention can be modified in various ways without departing from the scope of the invention.

[0041]

As described above, according to the first aspect of the present invention, the first data writing means uses the odd parity or the even parity based on the value of the bit of a certain reference digit in the bit data of a plurality of digits. The parity is determined, the first parity bit is generated based on the determined parity reference, the first parity bit and the bit data are written into the memory, and the first parity error determination means is used by the first parity error determination means. Reading the first parity bit and the bit data written by the data writing means from the memory, and determining the presence or absence of a parity error based on the bit data, the first parity bit and the parity reference, The data writing means 2 bit-inverts the bit data of a plurality of digits, and the bit of the reference digit of the bit-inverted bit data of a plurality of digits is inverted. On the basis of the value, the parity reference is determined to be an inverted parity reference having an even or odd inverted value, a second parity bit is generated based on the inverted parity reference, and the second parity bit and the inverted bit data are generated. The second parity error judgment means writes the data in the memory and reads the second parity bit and the inverted bit data written by the second data writing means from the memory. The presence or absence of a parity error is determined based on the parity bit and the inversion parity reference, and when the parity check execution means determines by the first and second parity error determination means that there is no parity error, the memory is normal. The number of parity checks is reduced to 2 while maintaining the certainty of error detection. By, it can provide a computer system capable of improving the processing speed.

According to the second aspect of the present invention, the abnormal address registration means determines whether or not there is an abnormality in the memory in units of physical addresses by using an error detection logic for the bit data,
When this determination result indicates that there is an abnormality, the physical address indicating the abnormality is registered, and the abnormal address erasing unit erases the physical address registered by the abnormal address registering unit from the address conversion table and also erases the physical address. Since another physical address is set in the address conversion table instead of the physical address, when an abnormality is detected in the memory, the abnormal area is separated from the physical address of the memory and only the healthy area is continuously used. It is possible to provide a computer system that can improve the operating rate.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system according to an embodiment of the present invention

FIG. 2 is a flow chart for explaining a startup operation in the same embodiment.

FIG. 3 is a flowchart for explaining a memory diagnosis operation in the same embodiment.

FIG. 4 is a flow chart for explaining an operation for responding to an abnormality occurrence in the embodiment.

FIG. 5 is a schematic diagram for explaining a parity check in the embodiment.

FIG. 6 is a schematic diagram for explaining an operation of separating an abnormal physical address in the embodiment.

FIG. 7 is a schematic diagram for explaining an abnormal physical address separating operation in the embodiment.

FIG. 8 is a schematic diagram for explaining a conventional parity check.

[Explanation of symbols]

1 ... CPU, 2 ... Parity check function unit, 3 ... System controller, 4 ... Main memory, 5 ... System bus, 6 ... Program storage unit, 7 ... OS, 8 ... Data writing unit, 9 ... Parity error determination unit, 10 ... Address conversion table, 11 ... Abnormal address table.

Claims (2)

[Claims] 1. A computer system capable of performing a parity check on the presence / absence of abnormality in a plurality of digits of bit data stored in a memory, wherein odd parity or parity is determined based on a value of a bit of a certain reference digit among the plurality of digits of bit data. The even parity is determined and the first parity is determined based on the determined parity criterion.
First parity writing means for generating the first parity bit and the bit data in the memory, and the first parity bit written by the first data writing means. And a first parity error determining means for reading bit data from the memory and determining the presence or absence of a parity error based on the bit data, the first parity bit, and the parity reference, and the bit data having a plurality of digits. Bit-inverted, based on the value of the bit of the reference digit among the bit-inverted bit data of a plurality of digits, the parity reference is determined to be an inverted parity reference that is even-odd inverted. A second parity bit is generated based on an inverted parity criterion, and the second parity bit and the inverted bit data are Second data writing means for writing to the memory, the second parity bit and the inverted bit data written by the second data writing means are read from the memory, and the inverted bit data, The second parity error determination means for determining the presence or absence of a parity error based on the second parity bit and the inverted parity reference, and the first and second parity error determination means respectively determine that there is no parity error. At this time, the computer system is provided with a parity check executing means for determining that the memory is normal. 2. An address translation table storing a correspondence relationship between virtual addresses and physical addresses, wherein a virtual address assigned to bit data is translated into a physical address by referring to the address translation table, and the address is translated. In the computer system that writes the bit data in the memory according to the physical address, the presence or absence of the memory abnormality is determined for each physical address by using the error detection logic for the bit data, and when the determination result indicates abnormality, Abnormal address registering means for registering a physical address indicating the abnormality, and erasing the physical address registered by the abnormal address registering means from the address conversion table, and replacing the erased physical address with another physical address. Abnormal address erasing means set in the address conversion table Computer system characterized by comprising.