JPH07244613A - Dual-memory control method - Google Patents

Abstract

PURPOSE:To minimize the influence of fault occurrence by storing an analytic program in a stand-by memory and taking a fault analysis if an error which needs to be analyzed occurs, and restoring the contents of the stand-by memory to the state before the fault occurrence after the fault analysis is taken. CONSTITUTION:It is checked whether or not there is abnormality in a device. When there is not abnormality, data are read out of an in-use memory 2a and an error of the read data is checked. When no error is found, the data are transferred to an MPU 1. Once abnormality in the device is confirmed, information is stored in an error register, a reset circuit 6 resets the MPU 1, and a data selection part 3 switches a readout destination memory from the in-use memory 2a to the stand-by memory 2b. After the MPU 1 is reset, the device is started up under the control of the stand-by memory 2b and a communication is restarted; and the fault analytic program is loaded to an analytic program storage area in the stand-by memory 2b to takes the fault analysis. After the analysis, a data selection part 3 switches the data readout destination memory to the in-use memory 2a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for recovering from a failure in a device having a dual memory.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of the prior art. In the figure, 21 is an MPU, 22 is a memory, and 23.
Is a failure detection circuit, and 24 is a reset circuit. The operation when a failure occurs in the device shown in FIG. 6 will be described below.

When an abnormality occurs in the device, the fault detection circuit 23 senses it and transfers an error signal to the reset circuit 24. The reset circuit 24 forcibly resets the MPU 21 to stop the operation. After restarting, the failure analysis program is loaded into the memory 22 and failure analysis is performed.

[0004]

In the prior art, the following problems occur due to the operation as described above. 1. When a failure occurs, the MPU is reset, so
Failure information cannot be collected. Therefore, information that may be a clue for failure analysis cannot be obtained, and failure analysis takes time. 2. By loading the failure analysis program into the memory, the original data must be erased. 3. If the memory itself is abnormal, the faulty program may not work properly and fault analysis may not be possible.

It is an object of the present invention to provide a highly reliable memory which minimizes the influence of failure occurrence.

[0006]

FIG. 1 is a flowchart of the principle of the present invention. Each process in the flowchart of FIG. 1 will be described below. 1 to 7 correspond to the processes of 1 to 7 in FIG. 1, respectively. 1: Examine the device for abnormalities. 2: If there is no abnormality in the process 1, the data is read from the active memory. 3: Check the read data for errors. 4: If there is no error in the process 3, the data is transferred to the MPU. 5: If an error occurs in the process 3, the data is read from the spare memory. 6: When an abnormality is detected in the process 1, the failure analysis is performed using the spare memory. 7: The contents of the spare memory are restored to the state before the abnormality occurred.

[0007]

In normal operation, the MPU writes data to both the working memory and the spare memory, and when reading the data, the working memory is selected as the read destination memory and the data read from the working memory is transferred to the MPU. To do. When an error is confirmed in the read data, the read destination memory is switched to the spare memory, and the data read from the spare memory 2b is transferred to the MPU.

However, when a serious abnormality that requires a failure analysis occurs inside the apparatus, the failure analysis program is loaded into the spare memory and the failure analysis is performed. This makes it possible to recognize the place and phenomenon of the abnormality. In addition, since the analysis is performed using the area of the spare memory, the failure analysis can be performed even if the abnormal place is the current memory. After the analysis is completed, the memory duplication mechanism is used to load the data in the working memory into the spare memory, whereby the contents of the spare memory can be restored to the state before the abnormality occurred.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 to 5 are explanatory views of an embodiment of the present invention. FIG. 2 is a block diagram of an apparatus having a duplicated memory as an embodiment of the present invention. FIG. 3 is a flowchart of the embodiment of the present invention.

FIG. 4 shows that after an abnormality is found inside the device,
It is a time chart until the memory is switched from the working memory 2a to the spare memory 2b. Figure 5 shows the working memory 2
It is a figure showing the information stored in a and spare memory 2b. In FIG. 2, 1 is an MPU and 2 is a memory, which is divided into a working memory 2a and a spare memory 2b.
3 is a data selection unit, 4 is a data check unit, 5 is a failure detection unit, 6 is a reset circuit, and 7 is an error register.

In the figure, a data selection unit 3 reads out data from one of the working memory 2a and the spare memory 2b and outputs it to the MPU.
Transfer to 1. The data check unit 4 performs a parity check or the like to check an error in the read data. The failure detection unit 5 monitors each unit in the device and detects a failure.

The reset circuit 6 resets the MPU 1 when the failure detecting section 5 confirms an abnormality. The error register 7 stores failure information and is referred to when the failure analysis program is executed. Below, according to the flowchart of FIG.
The control procedure of the duplicated memory in the present invention will be described. 1
To 14 correspond to the processes of 1 to 14 in FIG. 3, respectively. 1: Some abnormality may occur inside the device,
The fault detection unit monitors the device for abnormalities. 2: Normally, data is written in the working memory 2a and the spare memory 2b, and the data is set to read the data in the working memory 2a by the data selection unit 3, and an abnormality is detected in the process 1. If not, the data is read. 3: The data check unit 4 performs a check such as a parity check on the read data. 4: If it is determined in processing 4 that there is no error, it is transferred to the CPU 1. 5: If there is an error as a result of the check by the data check unit 4, the data selection unit 3 changes the data read destination to the spare memory 2b. 6: Read data from the spare memory 3b. 7: If an abnormality occurs in process 1, the fault detection circuit 5 senses it and sends an error signal to the reset circuit 6 and the data selection unit 3. 8: Error information is stored in the error register 7. 9: The reset circuit 6 resets the MPU 1 after waiting for the failure information to be stored in the error register 7. 10: The data selection unit 3 switches the data read memory to the spare memory 2b.

FIG. 4 is a time chart in steps 7 to 10. When an abnormality is confirmed, information is stored in the error register 7, the reset circuit 6 resets the MPU 1, and the data selection unit 3 uses the read destination memory. The memory 2a is switched to the spare memory 2b. 11: After reset, the device is started up by control of the spare memory 2b, communication is restarted, and the failure analysis program is loaded into the analysis program storage area of the spare memory 2b. 12: Failure analysis and the like are executed. When the analysis program is executed, referring to the contents of the error register 7,
By investigating each part in the device, we will clarify the phenomenon of the error and the place where the error occurred. 13: After the analysis is completed, the data selection unit 3 switches the data read destination memory to the working memory 2a. 14: In addition, since the analysis program was loaded, the original memory was destroyed and the spare memory 2
It is necessary to restore the failure analysis program storage area of b. The explanation will be given below.

FIG. 5A shows the working memory 2a and FIG. 5B.
Indicates the contents of the spare memory 2b. Working memory 2
a, the spare memory 2b has a common fixed area in which a memory write / read program, a save address, and a communication program are stored. Here, the save addresses are the start address α and the end address β of the area corresponding to the analysis program storage area of the active memory 2a.

The MPU 1 reads the data (address α, address β) stored in the save area of the active memory 2a and reads the data stored at addresses α to β of the active memory 2a. The read data is stored in the spare memory 2b.
Is written in the analysis program storage area of and the data before the failure is restored.

[0016]

According to the present invention, when a failure occurs,
Since failure information can be collected, failure analysis time can be shortened. Further, since the failure analysis is executed by using the area of the spare memory, the analysis can be performed even if the failure occurs in the working memory, and the occurrence location can be recognized as the working memory.
After the analysis is completed, the advantage of the memory duplication is taken advantage of and the current memory data can be loaded into the spare memory, so that the contents of the spare memory can be restored.

As described above, according to the present invention, it is possible to reduce the influence at the time of occurrence of a failure, and largely contributes to the improvement of reliability.

[Brief description of drawings]

FIG. 1 is a flowchart of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a flowchart in an embodiment of the present invention.

FIG. 4 is a diagram showing a time chart during memory switching according to the present invention.

FIG. 5 is a diagram showing the contents of a working memory and a spare memory according to the present invention.

FIG. 6 is a diagram showing a conventional example.

[Explanation of symbols]

 1 ... MPU 2 ... Memory 2a ... Working memory 2b ... Spare memory 3 ... Data selection unit 4 ... Data check unit 5 ... Fault detection unit 6 ... Reset circuit 7 ... Error register

Claims (1)

[Claims] 1. A method of controlling a redundant memory, wherein when a data error occurs, the current memory is switched to a spare memory and the memory is read out. When an error requiring failure analysis occurs, the spare memory is read. A redundant memory control method, wherein an analysis program is stored in a memory for failure analysis, and after the failure analysis is completed, the contents of the spare memory are restored to the state before the failure occurred.