JPS6213702B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system such as an electronic exchange in which a device such as a communication path control device is connected to a central processing unit via a common bus. The present invention relates to a failure handling method for handling failures.

In an electronic switching system in which a central processing unit, which has a bus cycle stop and retry function based on external input, is connected to devices such as communication line control equipment via a common bus, if a failure occurs in a device other than the central processing unit, Conventionally, a failure detection circuit detects this and stops the bus cycle, and a retry function performs a retry. If the retry fails, the failure detection circuit generates an interrupt to the central processing unit. After starting the failure handling program and saving the necessary information, processing was resumed from a fixed address.

In such conventional examples, the common bus refers to an example in which a data bus and an address bus are each commonly connected. Then, on the address bus, there is an address that forms the same address space with other devices such as the central processing unit and the communication path control device. The same address space means, for example, that the addresses used by the central processing unit are addresses 0 to 1000, addresses 1001 to 1050 are used by other devices, and addresses 1051 to 1070 are used by other devices. Tell me the way. It goes without saying that the actual address has a much larger number of digits.

Furthermore, the necessary information saved by the fault handling program includes the contents of the program counter (PC), the contents of the address register (AR), etc., both of which are information for the history of the program.
This is internal information of the central processing unit. Therefore, information about the other party where the failure occurred is not included.

Fixed address means that the jump destination is a fixed address when a failure occurs. No information is inserted into this fixed address, indicating that a failure has occurred.

An example of a document stating that the address spaces are the same is "Microcomputer Basic Technology Manual" (Showa era).
Published September 20, 1953, Radio Gijutsusha, written by Yojiro Yokoi) (page 267).

In such conventional failure handling methods, as the number of devices connected to the central processing unit increases and the number of failures in devices other than the central processing unit increases, the number of restarts from fixed addresses increases, thereby reducing online processing. The drawback was that there were frequent interruptions and the stability of the online system decreased.

An object of the present invention is to provide a fault handling method that can minimize the influence on an online system due to a fault in a device other than the central processing unit.

First, the principle of the present invention will be explained.

In the present invention, the fault detection circuit identifies and stores the cause of the fault and the faulty device, and further,
The bus cycle is retried repeatedly according to the cause of the failure and the retry counter provided for each type of device that caused the failure.

Then, when the retry fails, the failure detection circuit
The bus state is set to have the least impact, and a pseudo response is returned to the central processing unit.

In the central processing unit, the pseudo response signal allows program processing to continue as if the retry was successful.

In addition, the fault detection circuit generates an interrupt signal at the same time as the pseudo response signal, and the fault processing program reads information about the cause of the fault and the type of faulty device stored in the fault detection circuit, and removes the faulty device from the system. In the case of a device that can be separated, an unusable display is displayed to prohibit access to the faulty device, execution of the process is taken over at the point where the interrupt is interrupted, and normal processing is continued.

On the other hand, if the faulty device has a serious impact on system operation, such as a main storage device, processing is taken over to a fixed address, a restart processing program is started, and processing such as switching to a backup system is executed. do.

Furthermore, the fault detection circuit issues a command to generate simulated data, generates simulated data, and causes the central processing unit to take in this data. The central processing unit uses this pseudo data to perform the next process when the failure occurs. Since this processing is performed based on pseudo data, there is no actual processing involved. However, by setting the pseudo data to an appropriate value, it is possible to prevent the actual processing from being adversely affected. This ensures the stability of the online system, that is, even when a failure occurs, pseudo processing is performed based on pseudo data, and the online system can seemingly continue processing.

Note that the next process when a failure occurs is, assuming that the value of the program counter at the time of the failure is A, the next process is to specify the value set to the program counter value A, that is, the program counter of (A+1). Refers to a program (instruction).

The invention will be explained by examples.

In the figure, 1 is an address bus, 2 is a data bus, 3 is a central processing unit, 4 is a fault detection circuit, 5 is a main storage device, 6 is an input/output control device, 7 is a communication path system control device, and 8 is a central processing unit. A signal line 9 is a signal line for a response signal from each device 5 to 7 in response to an access from the device 3. A signal line 9 is a signal line for a response signal sent from the failure detection circuit 4 when a failure is detected, and a response signal line 8 is used during normal processing. 10 is a control line for causing the central processing unit 3 to retry the bus cycle, 11 is a control line for causing the central processing unit 3 to generate an interrupt, 12 is data for the central processing unit 3 A pseudo data control circuit for forcibly setting the bus to an arbitrary value; 13 indicates a control line for controlling the above 12 pseudo data control circuits.

Hereinafter, a description will be given of processing when a failure occurs in the communication line control apparatus 7 during a bus cycle in which the central processing unit 3 reads data existing in the communication line control apparatus 7. It is assumed that the cause of the failure is a failure in which no response signal is returned due to a failure of the communication path system control device 7.

The central processing unit 3 sets a predetermined address on the address bus 1 in order to read data from the communication line control unit 7, and takes in information on the data bus 2 when a response signal arrives from the signal line 9. do.

The failure detection circuit 4 monitors the response from the signal line 8, and if there is no response from the communication line control device 7 within a certain period of time, it captures and stores the address information of the address bus 1, and stores this stored information. From this, it is recognized that the device causing the problem is the communication line system control device 7.

Here, address information on address bus 1 will be described. As mentioned in the conventional example, address bus 1
is commonly used by all devices (central processing unit, main memory, input/output control unit, etc.). Therefore, each device has its own fixed address space on the same address space. Therefore, by looking at the address on the address bus, it should be possible to determine which device is currently being used. Therefore, in this embodiment, when a fault occurs, the address on the address bus at that time is sent to the fault detection circuit 4.
By taking in the information, it is determined that a failure has occurred in a fault-occurring device, for example, a communication path system control device.

On the other hand, since the number of retries for the communication path system control device 7 is set in advance in the corresponding retry counter provided in the fault detection circuit 4, the fault detection circuit 4 stores the contents of this retry counter. A signal is sent to the central processing unit 3 from the control line 10 that controls the retry of the bus cycle to cause it to perform the retry.

If the retry is successful, the failure detection circuit 4
initializes its own circuit and sends a response signal back to the central processing unit 3 via the signal line 9.

Furthermore, if the retry fails and a response signal cannot be received, the retry is repeated until the content of the retry counter becomes 0. When the retry counter reaches 0,
The fault detection circuit 4 forcibly sets the data bus 2 to a preset pattern (that is, sets pseudo data) by the pseudo data control circuit 12 via the control line 13, and sends it to the central processing unit 3. At the same time, a pseudo response signal is returned to the central processing unit 3 from the signal line 9. The failure detection circuit 4 sends an interrupt signal to the central processing unit 3 via the control line 11 at the same time as the pseudo response signal. That is, when the retry fails, the failure detection circuit 4 generates a pseudo response signal and an interrupt signal, and instructs generation of pseudo data.

After receiving these signals, the central processing unit 3 performs the following processing.

First, upon receiving the pseudo-response signal, the central processing unit assumes that the response to the processing up to that point has been received, and terminates the processing.

Next, receiving the interrupt signal, the central processing unit activates the fault handling program by interrupt processing. The fault processing program reads address information stored in the fault detection circuit 4 and checks the type of faulty device and the cause of the fault.

If the faulty device is the communication path system control device 7, the failure processing program is executed by the communication path system control device 7.
Disables and terminates interrupt processing.

Furthermore, after finishing the interrupt processing, the central processing unit 3
continues processing based on the pseudo data received from the fault detection circuit 4.

The process to be continued is the process following the process when the previous failure occurred, and is the process specified by adding 1 to the content of the program counter. This process is based on pseudo data,
Therefore, it is not a process based on real data. However, by appropriately selecting pseudo data, it is possible to perform processing as if it were performed using real data. That is, since the program of the central processing unit 3 is designed to perform processing with the least amount of errors when pseudo data is received in advance, the ripple effect of the failure is localized.
System stability can be maintained.

Although the failure processing of the communication path system control device 7 has been described above, the same processing can be performed even when a failure occurs in the input/output control device 6 or the main storage device 5. Note that the device that caused the failure is the main storage device 5.
In the case of a device that has a significant impact on the operation of the system, such as, the failure handling program performs restart processing such as switching to a standby device.

Further, in the embodiments described above, an example of an electronic exchange has been described, but the present invention is not limited thereto, and can be applied to data processing systems in general.

As described above, according to the present invention, when a failure occurs in a device connected to the central processing unit via a common bus, it is possible to take remedies for the failure for each individual device and the cause of the failure. In addition, by separating the device causing the failure from the system, the influence of the failure on the system can be minimized, and the stability of the system can be improved by suppressing the spread of the failure.

[Brief explanation of the drawing]

The figure shows a block diagram of a system implementing the method according to the invention. 1...address bus, 2...data bus, 3...
... Central processing unit, 4 ... Failure detection circuit, 7 ... Communication path system control device, 12 ... Pseudo data control circuit.

Claims (1)

[Scope of Claims] 1. A data processing system comprising a central processing unit, another device, and a common address bus and a common data bus that commonly connect the central processing unit and the other device, wherein the common address bus , a fault detection circuit is provided for detecting a fault in the other device mentioned above coupled to the common data bus, and the fault detection circuit detects the occurrence of a fault in the other device mentioned above, A command to retry a predetermined number of times is given to the central processing unit to make the retry, and if a fault still occurs even after the predetermined number of retries, the address on the common address bus at the time of the fault occurrence is sent to the central processing unit. It has a function of capturing and storing, sending a pseudo response signal and an interrupt signal to the central processing unit, and instructing the generation of pseudo data, and the central processing unit receives the pseudo response signal and performs the processing that requested the response. is terminated, the fault occurrence program is started in response to the interrupt signal, and the address stored at the time of the fault occurrence is loaded into the fault detection circuit to search for the type of device causing the fault and the cause of the fault. (c) A failure handling method for a data processing system, comprising a function of executing the next process when a failure occurs based on the pseudo data after the interrupt process is completed. 2. The fault handling method according to claim 1, wherein after the search, the other device in which the fault has occurred is separated from the system.