JPH05265876A - Error report processing system - Google Patents

Abstract

PURPOSE:To report a fault to an operating system by loading machine check interruption so as to instruct it a processor that error is discovered by patorol access. CONSTITUTION:When error information (5) showing that the existence of error is discovered by patorol access and a fault address (FSA) (6) generating uncorrectable error are transmitted to a processor 1, the processor 1 starts a machine check interruption operation. Namely, a machine check interruption code (MCIC), external interruption code (EDCD) and fault address (FSA) (6) are stored in the prescribed position of a main storage device 6. Next, a machine check new program status word (PSW) expressing the position of a machine check interruption processing routine is set as a current program status word (CPSW) after the CPSW is stored in a prescribed position on the main storage device 6 as a machine check old PWS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device in which a patrol mechanism checks whether the memory contents are destroyed by an intermittent or fixed fault, and an error report is distinguished from other machine check interrupts. Separately, it relates to an error report processing method for notifying the processor.

[0002]

2. Description of the Related Art FIG. 5 is an explanatory diagram for explaining a conventional error report processing method. In the figure, reference numeral 1 is a processor for advancing processing, 2 is a storage controller for controlling access to the storage device, 3 is a storage device, 4 is a service processor for managing the entire system. Reference numeral 5 represents a disk holding maintenance information (information such as the occurrence of an uncorrectable error).

In order to avoid occurrence of a read error of a correctable memory element during a program operation, patrol access is performed at predetermined intervals within a range that does not affect the execution of the program. When a patrol request is issued from the service processor (SVP) 4 (1), the contents of the storage device 3 are sequentially read and checked by a well-known error check mechanism (not shown). The patrol that performs patrol access is provided as an automatic diagnosis mechanism outside the control of the OS.

When a correctable error is detected by the patrol access, the patrol access is subsequently made again to the same address, and if the error is detected again at the same location, it is determined that the address has a fixed fault. Then, an alternative storage means such as a replacement chip prepared in advance is assigned. After that, when an address having a fixed fault is accessed, an alternative storage means such as a replacement chip is used to prevent occurrence of a read error of a storage element which occurs during a program operation. When an uncorrectable error occurs during patrol access, the address is reported to the service processor 4 as maintenance information (2) and recorded.

[0005]

When an uncorrectable error occurs in patrol access, it is reported to the service processor 4. At that time, the service processor 4 leaves the maintenance information on the disk 5. Alone
The OS is not notified of information that an uncorrectable error is detected by patrol access.

The reason for this is as follows. In other words, IBM's Enterprise Systems Archite, which defines the architecture of computer systems that are currently in wide use
cture / 370 Principles of Operation (PN SA22-7200-0)
Then, the error class indicating the type of machine check error includes system damage (SD), processing damage (PD), system recovery (SR) and external damage (ED), and SD cannot specify the affected range of damage. PD indicates that the range of influence of damage is only one instruction, and SR indicates that there was damage in the processing of that instruction, but the logical contradiction of processing is restored by the instruction retry mechanism and error correction mechanism. The instruction is successfully completed, and the last ED is defined as the damage other than the damage in the central processing unit (CPU) and the main memory.

For example, when an uncorrectable error is detected by patrol access to the shared extended storage unit (SSU), the error class reporting such damage corresponds to the ED, but indicates detailed information of the ED. There is no bit indicating the error information in the ED code, that is, no consideration is given to patrol. Therefore, it cannot be expressed that an uncorrectable error is detected by the patrol access, and the cause of the error cannot be identified, so that a countermeasure for the error cannot be taken.

Even if a replacement chip is assigned,
If an uncorrectable error occurs, the data cannot be restored and the validity of the stored contents cannot be guaranteed. In other words, even if an uncorrectable error is already detected during patrol access, the OS is not notified, and when a program attempts to reference that address, there is no storage device whose equivalence is guaranteed. ， It becomes impossible to continue the program processing.

In a system having a memory device which is multiplexed and whose equivalence is guaranteed, after the replacement chip is assigned, the equivalence is restored by copying the contents of the multiplexed storage device to the replacement chip. However, the number of replacement chips is limited, and errors cannot be remedied beyond that number.

When an uncorrectable error is detected during the execution of the program, the processing can be continued by reading the data from another storage device whose equivalence is guaranteed. However, in this case, for example, if the area is duplicated, even if one of the areas is detected to be in an unusable state by patrol access, the area cannot be allocated thereafter, so patrol access From this point to the reading during the execution of the program at the relevant point, it is equivalent to the case where there is no multiplexing.
Further, when the above error is a progressive error, it was an uncorrectable error that could be detected at the time of patrol access, but it became an undetectable error at the time of reading by the program, and garbled data could occur. There is a nature.

If the uncorrectable error found by the patrol access can be recognized and appropriate resource management can be performed, the occurrence of the uncorrectable error during the execution of the program can be avoided, and when the resources are multiplexed. Can be quickly restored to the multiplexed state.

It is an object of the present invention to enable faults discovered by patrol access to be reported to the operating system.

[0013]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, reference numeral 1 is a processor for advancing processing, 2 is a storage controller for controlling access to the storage device, 3 is a storage device, 4 is a service processor for managing the entire system. Thing, 5
Represents a disk for holding maintenance information, and 6 represents a main storage device which may be the same as the storage device 3 shown in the figure.

In the case of the present invention, when it is found that an uncorrectable error occurs when the patrol access is performed by the service processor (SVP) 4, the processor from the storage device 3 side. For 1, the machine check interrupt that indicates that an error was found by patrol access is given.

[0015]

When the patrol access is started from the service processor 4 (3) and the occurrence of an uncorrectable error is found (4), the error that the existence of the error is found by the patrol access is found. The information (5) and the fault address (FSA) (6) in which an uncorrectable error has occurred are sent to the processor 1.

When the error information is transmitted to the processor 1, the processor 1 enters a machine check interrupt operation ("transmission of machine check interrupt") (7). Machine check interrupt processing performed by the processor 1 includes (i) machine check interrupt code (MCIC), (ii) external interrupt code (EDCD), and fault address (FS).
Following the operation of storing A) and a predetermined position in the main storage device 6, the current program status word (CPSW) is stored in a predetermined position in the main storage device 6 as a machine check old PSW. The machine check new PSW indicating the position of the machine check interrupt processing routine is set as the CPSW (8). In this way, machine check interrupts are reported to software as a result of these operations (9).

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 illustrates one embodiment of the processing aspects performed after reporting a machine check interrupt. Reference numerals in the figure correspond to those in FIG. 1, and 7 indicates an address conversion table.

When a machine check interrupt is reported,
The OS uses the machine check interrupt code (MCI
C) refers to the fault address (FSA) and external interrupt code (EDCD) by (10), and finds that an uncorrectable error is detected by patrol access (11). At this time, the physical page including the uncorrectable error can be known from the fault address (FSA). Further, the logical page that the program is aware of can be known from the address conversion table 7. Furthermore, the OS
The user can also know whether or not the program has already used the faulty page from the resource management information performed by himself. If the page has not been assigned to any program yet, the OS discards the physical page in which the uncorrectable error has occurred and assigns the logical address of the failed page to the replacement page prepared in advance. Allocation (12) is performed by rewriting the conversion table to avoid the occurrence of a read error of the memory element that occurs during the program operation.

FIG. 3 is an explanatory diagram showing the processing in the case where the faulty page is already assigned to the program in the error processing. Reference numerals in the figure correspond to those in FIG. When a machine check interrupt occurs, the OS uses the previously generated machine check interrupt code (MCIC) to generate a fault address (FSA) and external interrupt code (EDCD).
Refer to and to know that an uncorrectable error was detected by patrol access. In taking measures against this, the following method is used together with the method described with reference to FIG.

It is assumed that the storage area is duplicated now. When a data write request is received, the data is written to both areas (13), and when a data read request is received, the data is read from one area (14). When a patrol request comes in, check both areas.

When an uncorrectable error occurs due to patrol access in one area from which data is read at a certain point, the area in which the uncorrectable error is detected can be specified by the fault address (FSA) (15). .. Therefore, when the error is reported, the subsequent read areas are switched so that the data is not read from the area where the error occurs when the next data read request is made.

FIG. 4 shows a processing flow from the detection of an uncorrectable error to its handling. When an uncorrectable error is detected during patrol access (17), the error information indicating that the error has occurred and the failure address (FSA)
And (18) to processor 1 and service processor 4. The processor 1 enters the machine check interrupt operation here, and the machine check interrupt code (MCI
C) and an external interrupt code (EDCD) are generated, and the service processor 4 holds them as maintenance information (1
9).

Further, the current PSW is stored as a machine check old PSW in a predetermined position in the main memory device (20), and then the machine check interrupt code (MCIC) and the external interrupt code (E) are stored in the main memory device 6.
The DCD) and the fault address (FSA) are stored in a predetermined position in the main storage device 6 (21). Then processor 1
Sets the machine check new PSW indicating the machine check interrupt processing routine to the current PSW (2
2).

When the machine check new PSW is set to the current PSW by the processor 1 (23), the software enters the machine check processing routine (24).

Next, the machine check interrupt code (MCIC) and the external interrupt code (ED
(CD) is referred to (25), and the address where the failure has occurred is known from the failed address (FSA) (26).

At this time, it is checked whether or not the faulty area is used by the program (27), and if NO, the address translation table 7 is rewritten (28), and YE.
If it is S, a process for reading from another storage area is performed as shown in FIG. 3 (29). Then, the machine check old PSW is stored as the current PSW (3
0).

[0027]

As described above, according to the present invention, it becomes possible to recognize an uncorrectable error before a program uses a faulty part, and it is possible to take a countermeasure beforehand.

Therefore, it is possible to avoid the abnormal termination of the program even when the storage device is not multiplexed, and when it is multiplexed, it is restored to the multiplexed state from the occurrence of the uncorrectable error. It is possible to shorten the time until

[Brief description of drawings]

FIG. 1 shows a principle configuration diagram of the present invention.

FIG. 2 illustrates an example processing aspect that occurs after reporting a machine check interrupt.

FIG. 3 is an explanatory diagram showing processing in a case where a faulty page has already been assigned to a program in error processing.

FIG. 4 shows a processing flow from detection of an uncorrectable error to its response.

FIG. 5 is an explanatory diagram illustrating an error report processing method in a conventional case.

[Explanation of symbols]

 1 Processor 2 Storage Controller 3 Storage Device 4 Service Processor 5 Disk 6 Main Storage Device 7 Address Conversion Table

Claims (3)

[Claims] 1. A storage device (3) and the storage device (3)
And a service processor (4) that manages the entire system, the service processor (4) is managed by the service processor (4) while accessing the In a data processing device having a patrol mechanism, which reads out the stored data of at every predetermined time and checks whether the stored contents are destroyed by an intermittent failure or a fixed failure, it is set at least according to the kind of error. A first machine check interrupt and another machine check factor which are generated by a read error of an uncorrectable storage element detected by a patrol, and a means for holding a detailed bit of the error. Machine check interrupt that can be distinguished from the second machine check interrupt caused by Over de generates an error report processing method and notifies the program a generation address and the first machine check interruption of the detected error in the patrol. 2. A logical page or a physical page including an address in which an uncorrectable error has occurred, triggered by an interrupt reported by the first machine check interrupt,
2. The error report processing method according to claim 1, wherein the error report processing method is assigned to a replacement page prepared in advance to prevent occurrence of a read error of a storage element that occurs during a program operation. 3. The storage device (3) is configured to be multiplexed so that the equivalence between the two is guaranteed, and uncorrectable upon the interruption reported by the first machine check interruption. 2. A storage device including a storage element in which an error has occurred or a storage region to be read is switched, and another storage device or storage region prepared in advance whose equivalence is guaranteed is read out. Error reporting processing method.