JPH0476733A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the generation of malfunction in a data processor by evaluating the validity of conversion from a logical address into a physical address. CONSTITUTION:In the case of storing a microprogram read out from an external storage means 1 in an overlay area of a control storage means 3, a logical address in the means 1 is converted into a physical address in the means 3 by an address conversion circuit 9. The circuit 9 is inspected by responses to the output of a logical address register 8 for the means 1 and the output of a control register 4 for temporarily storing a microinstruction accessed by the physical address of the means 3, so that the error of the physical address can be automatically corrected. Since the validity of the conversion process from the logical address into the physical address is evaluated, the generation of malfunction in the data processor can be prevented.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to control storage means for a data processing device.

〔overview〕

The present invention provides a data processing device that uses an overlay type control storage means for microprogramming, in which the output of the logical address generation means of the external storage means and the output of the storage means of the microinstruction called by the physical address of the control storage means. By responding, it is possible to verify the operation of the address translation means.

[Conventional technology]

BACKGROUND ART Conventionally, there has been a technique called dynamic microprogramming in which a computer uses a storage device that can be rewritten at high speed as a control storage means, and a microprogram is changed and used by rewriting the control storage means. By using this dynamic microprogramming, functions can be easily expanded.

In addition, overlay technology is available as a countermeasure against the expansion of the implementation space and the increase in the cost of control storage means due to the increase in the number of microprogram steps due to function expansion. (For example, there is Japanese Patent Publication No. 61-41422.) What is overlay technology?
A microprogram is divided into frequently used routines and less frequently used routines, a resident area and an overlay area are provided in the control storage means, and the frequently used microprogram routines stored in the resident area are normally executed in the same manner as before. However, if a less frequently used microprogram routine is required, the necessary microprogram steps are loaded from the external storage means into the overlay area of the control storage means. At this time, it is necessary to convert the logical address consisting of the block number and intra-block address of the microprogram routine in the overlay area of the external storage means into a physical address indicating the address of the overlay area of the control storage means. The error check of this address conversion section usually employs a parity check method.

On the other hand, the control storage means accounts for a large portion of failures in data processing apparatuses using the control storage means, and error correction code technology has been adopted as a remedy for this problem. (For example, there is Japanese Patent Publication No. 62-027417.) The conventional error correction operation is performed according to the following procedure.

■ Read the microinstruction from the control storage means and set it in the control register.

■ Check for errors using the ECC method.

■ If an error is detected, execution of the microinstruction is inhibited and a syndrome is created.

■ Errors are corrected based on the syndrome and re-execution is performed.

The ECC method in step ① is widely known from ``Application of Error Detection and Correction Codes'' (Information Processing, Vol. 23, No. 4, Page 292). With such conventional error correction techniques, the reliability of control storage means has been significantly improved.

[Problem to be solved by the invention]

In such conventional error correction technology, an FCC is generated only for the data in the control storage means to detect and detect errors.
As a result, it is not possible to check the correctness of the logical to physical address translation process in a data processing device overlaid with control storage means using dynamic microprogramming. However, the reliability of the control storage means has not been sufficiently improved.

Furthermore, although it is possible to employ a dedicated ECC to check the validity of the address translation section, adding the FCC has the disadvantage of adding a large amount of hardware and increasing machine cycles. Ta.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and to provide a data processing device that can evaluate the validity of the conversion process from a logical address to a physical address.

[Means for Solving the Problems] The present invention provides an external storage means having an overlay area for holding a microprogram routine consisting of a plurality of microinstructions to be overlayed, and an external storage means for storing a microprogram routine on the overlay area. a logical address generating means for generating a logical address consisting of a block number and an address within the block; and a microinstruction that adds an error correction code generated for data consisting of the microinstruction and the logical address to the microinstruction. In a data processing device, the data processing device includes a control storage means for storing a word, and an address conversion means for converting a logical address generated by the logical address generation means into a physical address of the control storage means. error correction comprising: micro-instruction storage means for storing the micro-instruction word that has been generated; and means for detecting an error in one of the outputs in response to the output of the logical address generation means and the output of the micro-instruction storage means. It is characterized by comprising means. Here, it is desirable that the error correction means includes means for correcting the output of the microinstruction storage means and providing it to the microinstruction storage means when an error in the output of the microinstruction storage means is detected. Furthermore, it is desirable that the error correction means includes means for stopping the operation of the logical address generation means when an error is detected in the output of the logical address generation means.

[Effect]

A microprogram from an external storage device is stored in the overlay area of the control storage device, and at this time, a logical address of the external storage device is converted into a physical address of the control storage device by an address conversion device. Verification of this address conversion means is performed by responding to the output of the logical address generation means of the external storage means and the output of the storage means of the microinstruction called with the physical address of the control storage means, and errors in physical addresses are automatically detected. Fixed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing this embodiment.

In this embodiment, as shown in FIG. 1, the generation method E
an external storage means 1 that holds a microprogram to which a CC is added in an overlay area; a data register 2 that stores data retrieved from the external storage means 1; and a microprogram to which an ECC is added that is supplied via the data register 2. A control storage means 3 that holds a program; a control register 4 that temporarily stores microinstructions read from the control storage means 3 via a switching circuit 12;
a decoder 5 that decodes the output of the microinstruction part of the decoder 5 and generates a control signal; an arithmetic circuit 6 that is controlled by the output control signal of the decoder 5; an external memory access means 7 that generates a logical The address conversion circuit 9 converts the address into a physical address that is the address of the overlay area of the control storage means 3 and supplies it to the control storage means 3, and the logical address output from the switching circuit 10 and is stored in the control register 4. A microinstruction with ECC is input, the error is corrected, and the microinstruction is corrected if the error can be corrected. The error correction circuit 11 that outputs the inhibition signal and the output value of the switching circuit 10 +1
It is composed of a 10I adder 13 that generates . That is, this embodiment includes an external storage means 1 having an overlay area for holding a microprogram routine made up of a plurality of microinstructions to be overlayed, and a block number and block information of the microprogram routine on this overlay area. The logical address register 8 and the +1 adder 13, which are logical address generating means for generating a logical address consisting of an address, and the error correction code generated for the data consisting of the above-mentioned micro-instruction and the above-mentioned logical address, are It is equipped with a control storage means 3 for storing a microinstruction word added to an instruction, and an address conversion circuit 9 which is an address conversion means for converting the logical address generated by the logical address generation means into a physical address of the control storage means 3. Furthermore, as a feature of the present invention, a control register 4 which is a micro-instruction storage means for storing the micro-instruction word read out from the control storage means 3, and the output of the logical address generation means and the micro-instruction are provided. means for detecting an error in either output in response to the output of the microinstruction storage means; and means for correcting the output of the microinstruction storage means when an error in the output of the microinstruction storage means is detected; The error correction circuit 11 is provided as an error correction means including means for supplying an instruction to the instruction storage means, and means for stopping the operation of the logical address generation means when an error is detected in the output of the logical address generation means. Here, the overlay area of the external storage means 1 and the overlay area of the control storage means 3 are divided into pages of the same size. Further, the address conversion circuit 9 includes an address conversion table. This address conversion table has the same number of pages as the number of pages into which the auto-lay area of the control storage means 3 is divided. The conversion from a logical address to a physical address uses the simple-end method.

Next, the operation of this embodiment will be explained.

The logical address stored in the logical address register 8 is sent to the address conversion circuit 9 and the error correction circuit 1 via the switching circuit 10.
1 and +1 adder 13. Address conversion circuit 9 converts the supplied logical address into a physical address. This physical address accesses the control storage means 3,
The microinstruction with ECC read out from the control storage means 3 is stored in the control register 4 via the switching circuit 12.

The output data of control register 4 is supplied to error correction circuit 11 and decoder 5.

On the other hand, the logical address supplied to the +1 adder 13 is "
1'' is added and stored in the logical address register 8 as the address to be executed next. By repeating this operation, microprograms assigned to consecutive addresses can be executed sequentially.

Further, when a microinstruction instructs a branch of the microprogram, the value of the branch destination address field of the control register 4 is supplied to the address conversion circuit 9 via the switching circuit 10 as a branch destination logical address. The address conversion circuit 9 converts this logical address into a branch target physical address and reads the branch target microinstruction from the control storage means 3.

The error correction circuit 11 performs error detection together with the supplied output data of the control register 4 and the logical address. If there is an error in the output data of the control register 4 as a result of error detection, an inhibition signal 110 is sent, the output data of the control register 4 is corrected, and an error correction signal 111 is sent to the control register 4 via the switching circuit 12. and rerun. If an error is detected in the logical address, an error detection signal is sent and the operation is stopped.

Next, details of the operation of the error correction circuit 11 will be explained based on FIG. The syndrome generation circuit 15 is the switching circuit 10
A syndrome is generated by inputting the logical address 100 which is the output data of the control register 4, the data section 40 of the output data of the control register 4, and the ECC section 41 of the output data of the control register 4. The syndrome decode circuit 16 decodes the syndrome 150 generated by the syndrome generation circuit 15. The correction circuit 17 manually inputs the data part 40 of the output data of the control register 4 and the error bit position indication signal 160 output from the syndrome decoding circuit 16, and corrects the error in the data part 40 of the output data of the control register 4 by correcting the error in the data part 40 of the output data of the control register 4. The error is corrected by inverting the 1-bit data in the data section 40 at the bit position indicated by the indication signal 160, and after the error correction, the control register 4
The data portion 170 of is output to the control register 4 via the switching circuit 12.

〔Effect of the invention〕

As explained above, the present invention provides F
CC is adopted, and by using error correction circuits to check and correct the logical addresses of microinstructions and microinstructions, it not only improves the operability of the control memory itself, but also evaluates the validity of the conversion from logical addresses to physical addresses. This has the effect of preventing malfunctions of the data processing device.

Furthermore, by using the FCC generated for the logical address and microinstruction during microprogram execution, and checking and correcting the logical address and microinstruction in the error correction circuit, there is no need to provide a dedicated FCC for the address translation circuit. Therefore, it is possible to reduce the amount of hardware and realize a means for verifying the validity of the conversion from a logical address to a physical address without increasing the number of machine cycles.

1... External storage means, 2... Data register, 3.
・Control storage means, 4: Control register, 5: Decoder, 6: Arithmetic circuit, 7: External storage access means, Logical address register, 9: Address conversion circuit, 10 .12...Switching circuit, 11...Error correction circuit, 13...÷1 adder, 15...Ndrome generation circuit, 16...Syndrome decoding circuit, 1
7... Correction circuit.

Claims (1)

[Scope of Claims] 1. External storage means having an overlay area that holds a microprogram routine consisting of a plurality of microinstructions to be overlayed, and a block number and block information of the microprogram routine on this overlay area. logical address generation means for generating a logical address consisting of an address; and control for storing a microinstruction word in which an error correction code generated for data consisting of the microinstruction and the logical address is added to the microinstruction. In a data processing device comprising a storage means and an address conversion means for converting a logical address generated by the logical address generation means into a physical address of the control storage means, the microinstruction read from the control storage means. microinstruction storage means for storing a word, and error correction means including means for detecting an error in one of the outputs in response to the output of the logical address generation means and the output of the microinstruction storage means. A data processing device characterized by: 2. The data according to claim 1, wherein the error correction means includes means for correcting the output of the microinstruction storage means and providing it to the microinstruction storage means when an error in the output of the microinstruction storage means is detected. Processing equipment. 3. The data processing apparatus according to claim 2, wherein the error correction means includes means for stopping the operation of the logical address generation means when an error is detected in the output of the logical address generation means.