JP2020165802A - Semiconductor device and method for testing semiconductor device - Google Patents

Abstract

To reduce the cost of manufacturing a semiconductor device by reducing the size of an additional circuit while maintaining the function of an LBIST test.SOLUTION: The semiconductor device according to the present invention runs a self-test, and includes: a plurality of circuit blocks 50 for receiving an input of a pattern; and a comparator 302 for acquiring a test response based on a response that each circuit block outputs in response to the input of the pattern and obtaining the result of the self-test of the circuit block by comparing with the reference value. The plurality of circuit blocks share the pattern input.SELECTED DRAWING: Figure 5

Description

The present invention relates to a semiconductor device that performs self-testing, and a method for testing the semiconductor device.

There is a possibility that defects will be incorporated into logic circuits during the design and manufacturing processes. In addition, even if the logic circuit has no defects at the time of shipment, malfunction may occur later due to deterioration over time or the influence of natural radiation. Therefore, from the viewpoint of functional safety, it is desirable that the semiconductor device performs self-diagnosis not only at the time of shipment but also during operation to promptly detect a defect.

An embedded self-test (BIST: Built-In Self-Test) is known in which a semiconductor device itself performs a self-test by incorporating a test function for a logic circuit or a storage device into the semiconductor device. Of these, the BIST performed on the logic circuit is called an L (Logic) BIST (Patent Document 1). Since LBIST does not use an external test device, it can be executed on a verification board, a system, or in an actual operating environment. On the other hand, since it is necessary to provide a test circuit inside the semiconductor device, the scale of the semiconductor device becomes large.

On the other hand, with the progress of parallel computing technology such as image processing and machine learning, semiconductor devices equipped with a large number of the same arithmetic units are becoming widespread.

Japanese Unexamined Patent Publication No. 2013-253840

An object of the present invention is to reduce the manufacturing cost of a semiconductor device by reducing the scale of additional circuits while maintaining the function of the LBIST test.

The present invention employs the following technical means to solve the above problems. The scope of claims and the reference numerals in parentheses described in this section are examples showing the correspondence with the specific means described in the embodiments described later as one embodiment, and limit the technical scope of the present invention. It is not something to do.

The semiconductor device (10) of the present invention is a semiconductor device (10) that performs a self-test, and each of a plurality of circuit blocks (50) that accept pattern inputs and the plurality of circuit blocks with respect to the pattern input A comparator (302, 303) for obtaining a test response originating from an output response and comparing it with a reference value to obtain the result of the self-test of the circuit block, and the pattern input is provided in the plurality. Circuit block is shared.

With this configuration, it is not necessary to provide a circuit for generating a pattern input for each circuit block, so that the LBIST function can be added to the semiconductor device with a small circuit area.

Further, the semiconductor device further includes a code compressor (60) that compresses the response to generate a compressed value, and the comparator can compare the compressed value with the reference value as the test response.

With this configuration, the expected value of the test response can be held in the semiconductor device in advance, and the comparison can be performed efficiently.

Further, in the present semiconductor device, the code compressor can be shared by the plurality of circuit blocks.

With this configuration, the number of code compressors can be reduced, so that the circuit area for testing can be reduced and the manufacturing cost can be reduced.

Further, in the present semiconductor device, the reference value can be an expected value prepared according to the pattern input.

By preparing a valid expected value in advance, the operating state of the circuit block can be accurately determined.

Further, in the present semiconductor device, the plurality of circuit blocks have the same function as each other.
The reference value of each of the plurality of circuit blocks can be a test response of the other circuit block that shares the same pattern input as the circuit block.

With this configuration, it is possible to perform a test even for a test pattern in which the expected value is not registered in advance.

Further, the semiconductor device further includes a pattern generator (40) that generates a test pattern, and the plurality of circuit blocks can accept the test pattern generated by the pattern generator as the pattern input.

With this configuration, it is possible to determine in advance whether or not the output of the circuit block is normal by holding the expected value of the test response to the output of the pattern generator in advance and comparing the test response with the expected value.

Further, the semiconductor device further includes a test controller (30) for controlling the execution of the self-test, and the test controller is the circuit in hibernation based on the operation schedule of each of the plurality of circuit blocks. The self-test can be performed on the block.

With this configuration, the entire circuit block group can be tested by dynamically repeating the test for an empty circuit block while referring to the circuit block schedule even during operation.

Further, in the present semiconductor device, the test controller can generate a pattern initialization input, and the pattern generator can generate the test pattern based on the pattern initialization input.

With this configuration, the probability that the test covers the functions of the circuit block can be increased, and the possibility of detecting a defect can be increased.

Further, in the present semiconductor device, the pattern input can be an input to be assigned to any of the plurality of circuit blocks in the normal operating state of the semiconductor device.

With this configuration, the pattern generator itself becomes unnecessary, so that the circuit area of the semiconductor device can be further reduced.

The self-test method of the semiconductor device is a test method for performing a self-test of the semiconductor device (10), and is a step of inputting a pattern input to a circuit block and a calculation step of causing the circuit block to calculate the pattern input. A step of compressing the response output by the calculation to generate a test response, and a step of comparing the test response with a reference value to obtain the result of the self-test of the circuit block. The same pattern input is input to the plurality of circuit blocks.

Further, in the self-test method of the semiconductor device, the reference value is an expected value prepared according to the pattern input, and the calculation step has a vacancy in the operation schedule of the plurality of circuit blocks. It may be realized by selecting a circuit block and performing an operation.

Further, in the self-test method of the present semiconductor device, the plurality of circuit blocks have the same function as each other, and the reference value of each of the plurality of circuit blocks shares the same pattern input as the circuit block. It may be realized by making the response of the other circuit block to be a compressed test response.

Further, in the self-test method of the semiconductor device, the pattern input may be an input to be assigned to any of the plurality of circuit blocks in the normal operating state of the semiconductor device.

According to the present invention, it is possible to reduce the circuit scale for testing while maintaining the LBIST function in a semiconductor device having a plurality of arithmetic units. As a result, it is possible to prevent the circuit from becoming complicated and to reduce the size of the entire semiconductor device.

It is a figure for demonstrating the parallel processing which is the premise of this embodiment. It is a figure which shows the example of the system configuration for executing the parallel processing shown in FIG. It is a figure which shows the structural example of the DFP used in FIG. It is a figure which shows the outline of an example of the LBIST circuit. The test circuit of the first embodiment is shown. It is a table which shows the calculation timetable and the test schedule example of the 1st Embodiment. The test circuit of the second embodiment is shown. It is a table which shows the calculation timetable and the test schedule example of the 2nd Embodiment. The test circuit of the third embodiment is shown. The test circuit of the 4th embodiment is shown.

Hereinafter, the present embodiment will be described with reference to the accompanying drawings. It should be noted that the embodiments described below show an example of the case where the present invention is carried out, and the present invention is not limited to the specific configuration described below. In carrying out the present invention, a specific configuration according to the embodiment may be appropriately adopted.

FIG. 1 (A) shows a program code having a graph structure, FIG. 1 (B) shows a thread state, and FIG. 1 (C) shows a state of parallel processing.

As shown in FIG. 1A, the program targeted for processing in the present embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.

When the program code shown in FIG. 1 (A) is automatically vectorized by a compiler and the graph structure is extracted, a large number of threads can be generated as shown in FIG. 1 (B).

For a large number of threads shown in FIG. 1 (B), parallel execution as shown in FIG. 1 (C) can be performed by dynamic register allocation and thread scheduling by hardware. By dynamically allocating register resources during execution, multiple threads can be executed in parallel for different instruction streams.

Subsequently, with reference to FIG. 2, a data processing system 2 which is a system configuration example including a DFP (Data Flow Processor) 10 as an accelerator for performing dynamic register arrangement and thread scheduling will be described.

The data processing system 2 includes a DFP 10, an event handler 20, a host CPU 21, a ROM 22, a RAM 23, an external interface 24, and a system bus 25. The host CPU 21 is an arithmetic unit that mainly performs data processing. The host CPU 21 supports an OS. The event handler 20 is a part that generates interrupt processing.

The ROM 22 is a read-only memory. The RAM 23 is a memory for reading and writing. The external interface 24 is an interface for exchanging information with the outside of the data processing system 2. The system bus 25 is for transmitting and receiving information between the DFP 10, the host CPU 21, the ROM 22, the RAM 23, and the external interface 24.

The DFP 10 is positioned as an individual master provided to cope with the heavy computing load of the host CPU 21. The DFP 10 is configured to support interrupts generated by the event handler 20.

Subsequently, the DFP10 will be described with reference to FIG. As shown in FIG. 3, the DFP 10 includes a command unit 12, a thread scheduler 14, and an execution core 16.
It includes a memory subsystem 18.

The command unit 12 is configured to enable information communication with the config interface. The command unit 12 also functions as a command buffer.

The thread scheduler 14 is a part that schedules the processing of a large number of threads as illustrated in FIG. 1 (B). The thread scheduler 14 can perform scheduling across threads.

The execution core 16 has four processing elements, PE # 0, PE # 1, PE # 2, and PE # 3. The execution core 16 has a large number of pipelines that can be scheduled independently.

The memory subsystem 18 has an arbiter 181 and an L1 cache 18a and an L2 cache 18b. The memory subsystem 18 is configured to enable information communication with the system bus interface and the ROM interface.

FIG. 4 is a diagram showing an outline of an example of an LBIST circuit.
In this specification, the output of the circuit block 50 described later is expressed as a “response”, and the response of the circuit block 50 as the origin and used for the comparison described later is expressed as a “test response”.
The LBIST circuit of FIG. 4 includes a test controller 30, a pattern generator 40, a circuit block 50, and a code compressor 60. The test controller 30 includes a pattern initializer 301 and an expected value comparator 302. The test controller 30 controls the test of the circuit block 50. Specifically, a clock to be supplied to the test circuit is generated, and the pattern initializer 301 generates an initial value of the test pattern and supplies it to the test circuit.

The pattern generator 40 generates a test pattern according to the initial value given by the pattern initializer 301. A pseudo-random number generator (PRPG: Pseudo Random Pattern Generator) is generally used to generate the test pattern, but other methods may be used. The test pattern generated by the pattern generator 40 is input to the circuit block 50, and the circuit block 50 performs an operation based on the test pattern. The circuit block 50 is a logic circuit to be tested, and the processing element PE in FIG. 3 corresponds to an example.

The code compressor 60 compresses the response of the circuit block 50 to generate a test response. The response to the test pattern output by the circuit block 50 is a long serial data, and it is uneconomical to store this as it is in the ROM. Therefore, the test controller 30 holds the compressed result calculated in advance as an expected value and uses it. By design, the test response, which is the compressed value obtained by compressing the response generated by the circuit block 50 by the code compressor 60, and the expected value of the test controller 30 are the same. As a typical code compressor, a multi-input signature register (MISR: Multiple Input Signature Register) is used, but other compressors may be used as long as the conditions are satisfied. The expected value comparator 302 compares the test response, which is the compressed value output from the code compressor 60, with the expected value calculated in advance and stored in the test controller 30 or in the ROM or the like. If the test response and the expected value are the same, the circuit block 50 is operating normally. If the test response and the expected value are different, the circuit block 50 is suspected to be defective.

When performing LBIST on a plurality of circuit blocks, the pattern generator 40 and the code compressor 60 are prepared for the number of circuit blocks to be tested. In this configuration, as the number of circuit blocks to be tested increases, the test circuit area inside the semiconductor device increases, and the manufacturing cost of the semiconductor device increases. Therefore, in the LBIST circuit of this embodiment, as shown in each of the following embodiments, an increase in the test circuit area is suppressed and the manufacturing cost of the semiconductor device is reduced.

In the test circuit of each embodiment shown below, each component has the same function as the component of an example of the LBIST circuit shown in FIG. Therefore, the same reference numerals are given and duplicate description will be omitted. The circuit block 50 in each embodiment has the same function as the processing element PE in FIG.

(First Embodiment)
FIG. 5 shows the test circuit of the first embodiment.
In this embodiment, one pattern generator 40 is shared by all circuit blocks 50.
Since the circuit block 50 has the same function, the response to the test pattern is also the same, and if the test controller 30 stores one corresponding expected value, a plurality of circuit blocks 50 can share the same test pattern. .. As a result, it is not necessary to mount the same number of pattern generators as the circuit block in the semiconductor device, so that the circuit area for testing can be reduced and the manufacturing cost of the semiconductor device can be reduced.

The test controller 30 determines which circuit block 50 is to be tested by referring to the schedule of each circuit block. Specifically, the test controller 30 refers to the thread information generated in advance by the hardware scheduler or the compiler and stored in the arbiter, and selects the circuit block 50 in which the testable free time is scheduled. .. The test controller 30 executes the test when the selected circuit block 50 enters the idle state.

FIG. 6 is a table showing an example of the calculation timetable and the test schedule of the present embodiment.
The table of FIG. 6 shows the state of each of the plurality of circuit blocks at each elapsed time. In each cell of the table, W is the state in which the circuit block is operating normally at the time, L is the state in which the circuit block is executing the test at the time, and the unsigned place is the state at the time. Indicates that the circuit block is idle.

Since the test is completed before the next task is assigned to the circuit block 50 under test, there may be a delay in processing even if the semiconductor device is tested in parallel while operating under actual usage conditions. Absent. In the present embodiment, the same number of code compressors 60 are inserted as the circuit blocks 50. Therefore, when there are a plurality of circuit blocks 50 having a set free time that can be tested at the same time, the time 10 in FIG. As shown in ~ 17, a plurality of circuit blocks 50 can be tested at the same time.

When the pattern generator 40 is a pseudo-random number generator, the test controller 30 can cause the pattern generator 40 to generate a different test pattern by changing the value of the pattern initializer 301. By preparing the correspondence table between the initial value, the pseudo-random number, and the expected value in advance, the test controller 30 can further increase the test variation and improve the completeness of the test.

It is also possible to generate test variations with different estimated execution times and add estimated execution time information to the test variations. By adding the estimated execution time information, the test controller 30 can select various test variations from those whose execution is completed in a short time to those whose execution is long. The test controller 30 refers to how long the idle state of the circuit block 50 to execute the test continues, and selects the optimum test pattern having an assumed execution time to end within the idle time. By providing variations in the estimated execution time, it is possible to execute a short-time test even for the circuit block 50, which cannot be tested for the standard execution time due to insufficient idle time. Further, since the circuit block 50 having a long idle time can be tested for a long time, computational resources can be used without waste.

(Second Embodiment)
FIG. 7 shows the test circuit of the second embodiment.
In the present embodiment, not only the pattern generator 40 but also the code compressor 60 is shared by a plurality of circuit blocks 50. This eliminates the need to mount the same number of code compressors 60 as the circuit block 50 on the semiconductor device. According to this embodiment, the circuit area for testing can be further reduced as compared with the first embodiment, and the manufacturing cost of the semiconductor device can be reduced.

FIG. 8 is a table showing an example of the calculation timetable and the test schedule of the second embodiment.
As in FIG. 6, in the table, the rows show the elapsed time and the columns show the circuit blocks. In the second embodiment, the plurality of circuit blocks 50 share one code compressor 60. Therefore, while one circuit block uses the code compressor 60, the other circuit block 50 cannot use the code compressor 60. Since the response of the circuit block 50 is a long serial data, the circuit block 50 occupies the code compressor 60 for a certain period of time during the test. From the above, in the present embodiment, the test cannot be executed for a plurality of circuit blocks at the same time. The test controller 30 determines a test schedule so that responses are not output from a plurality of circuit blocks at the same time while referring to the thread timetable, and based on this, generates an optimum test pattern as shown in FIG.

(Third Embodiment)
FIG. 9 shows the test circuit of the third embodiment.
In the present embodiment, the circuit block 50 shares the pattern generator 40, but two or more code compressors 60 are prepared, and the same test can be performed on a plurality of circuit blocks 50 at the same time. The comparator of the present embodiment is a code comparator 303 that does not refer to the expected value.

In the first and second embodiments, the expected value to be collated with the test response, which is the compression value generated from the code compressor 60, can be referred to inside the test controller 30 or the test controller 30 such as ROM 22 in FIG. It is stored in the location. However, there is a limit to the storage area that can be reserved for testing. In addition, there are cases where it is desired to perform a test using a test pattern for which an expected value is not prepared in the first place. If there are two or more code compressors 60, the same test is performed on two or more circuit blocks 50 at the same time, and the test responses generated by the two or more code compressors 60 are used for two or more responses. Can be compared. As a result of comparison by the code comparator 303, if the test responses obtained from two or more code compressors 60 are the same, it is considered normal. If the test responses are different, one of the circuit blocks 50 has a problem. Further, if there are three or more code compressors 60, the three or more circuit blocks 50 can be tested at the same time, and the circuit block 50 in which the defect has occurred can be identified by a majority vote.

Further, in the present embodiment, the responses of two or more circuit blocks 50 may be directly compared as test responses without using the code compressor 60. As a result of comparison, if two or more test responses are the same, a defect in the circuit block 50 can be detected without calculating the compression value by the code compressor 60. As a result, the code compressor 60 becomes unnecessary, and the circuit area for testing can be further reduced. In this case, instead of the code comparator 302, a simpler comparator that uses, for example, a bit operation can be used. However, when the code compressor 60 is not used, it is necessary to carry out the test on two or more circuit blocks 50 at the same time. When the code compressor 60 is used, comparison can be performed even if the test timing is deviated.

In the present embodiment, it is not necessary to prepare expected values for all test patterns in advance and incorporate them into the circuit, so that the memory capacity used for LBIST can be reduced. Further, regardless of whether or not the expected value is set, the pattern initializer 301 can pass an arbitrary initial value to the pattern generator 40 for testing. Further, even when a new test pattern in which the expected value is not incorporated is required after manufacturing the semiconductor device, a defect in the circuit block 50 can be found.

(Fourth Embodiment)
FIG. 10 shows the test circuit of the fourth embodiment.
In the present embodiment, the circuit block 50 executes the same processing generated by the controller 70 during normal operation instead of the output of the pattern generator 40. That is, in the present embodiment, the input itself assigned to one of the circuit blocks 50 in the normal operating state of the semiconductor device 10 serves as a test pattern. The code compressor 60 is composed of two or more as in the third embodiment. Also in this embodiment, the plurality of circuit blocks 50 perform the same processing, and the code comparator 303 performs test responses that are compression values generated by two or more code compressors 60 for two or more responses. Compare. If there are three or more code compressors 60, tests can be performed on three or more circuit blocks 50 at the same time, and the circuit block 50 in which a defect has occurred can be identified by a majority vote, and for two or more circuit blocks at the same time. If the test is to be carried out, the code compressor 60 can be configured as unnecessary, and in the above configuration, a simpler comparator can be used instead of the code comparator 302. It is the same as the embodiment of.

With this configuration, since the pattern generator 40 is not required, the circuit area can be further reduced and the manufacturing cost can be reduced. Further, in the product test stage, the operation that the tester wants to test can be input to the circuit block 50 and used for the test. Unlike a normal LBIST that uses a random pattern, the user can perform a test that focuses on the target area of the circuit block 50. In addition, with this configuration, it is possible to test patterns that can occur in actual use but cannot be expected at the design stage.

The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Those skilled in the art with appropriate design changes to these specific examples are also included in the scope of the present disclosure as long as they have the features of the present disclosure. The elements and their arrangement, conditions, shapes, etc. included in the above-described specific example are not limited to those illustrated, and can be changed as appropriate. The combination of the elements included in each of the above-mentioned specific examples can be appropriately changed as long as there is no technical contradiction.

For example, when there are a plurality of code compressors 60, the pattern generator 40 and the control unit 70 during normal operation may be switched so that they can be used for the test. As a result, it is possible to confirm whether the circuit block 50 is operating normally under the condition that the expected value is registered in the non-volatile memory, and the condition that the expected value is not registered or the output of the control unit. In the case of operating in, the defect of the circuit block 50 can be detected by comparing the test responses which are the compressed values of the plurality of code compressors 60.

Further, as a reference, the LBIST circuit shown in FIG. 4 is provided only in the specific circuit block 50, and the other circuit blocks 50 include the pattern generator 40 and the code compressor 60 as shown in the first to third embodiments. It may be shared. By comparing this configuration, it is possible to detect defects in the pattern generator 40 and the code compressor 60.

Even in the case of the embodiment in which the pattern generator 40 and the code compressor 60 are only one, the standby pattern generator 40 and the compressor 60 may be separately prepared. Even if the pattern generator 40 or the compressor 60 fails, the test function can be maintained by switching to the standby system.

In each of the above embodiments, the functions of the circuit block 50 have been described as being the same. However, the function of the circuit block may be different. In a configuration in which the functions of the circuit blocks are all different, the test controller 30 uses a combination of a test pattern and an expected value prepared for each type of circuit block. Even with this configuration, it is not necessary to provide the pattern generator 40 and the code compressor 60 for each circuit block 50, so that the circuit area of the semiconductor device can be reduced and the manufacturing cost can be reduced. Further, if there is a combination having the same function in the variation of the circuit block, a defect occurs by comparing the test responses with each other as described in the third and fourth embodiments. Can be known.

10: DFP, 30: Test controller, 40: Pattern generator, 50: Circuit block,
60: Code compressor, 70: Control during normal use

Claims (13)

A semiconductor device (10) that performs a self-test.
Multiple circuit blocks (50) that accept pattern input and
Obtain a test response originating from the response output by each of the plurality of circuit blocks to the pattern input.
A comparator (302, 303) for obtaining the result of the self-test of the circuit block by comparing each of the plurality of circuit blocks with a reference value.
With
A semiconductor device in which the plurality of circuit blocks share the pattern input. A code compressor (60) that compresses the response to generate a compressed value is further provided.
The comparator uses the compressed value as the test response and compares it with the reference value.
The semiconductor device according to claim 1. The semiconductor device according to claim 2, wherein the code compressor is shared by the plurality of circuit blocks. The semiconductor device according to claim 2, wherein the reference value is an expected value prepared in response to the pattern input. The plurality of circuit blocks have the same function as each other.
The semiconductor device according to claim 1 or 2, wherein the reference value of each of the plurality of circuit blocks is a test response of the other circuit block sharing the same pattern input as the circuit block. Further equipped with a pattern generator (40) that generates a test pattern,
The semiconductor device according to any one of claims 1 to 5, wherein the plurality of circuit blocks receive the test pattern generated by the pattern generator as the pattern input. A test controller (30) for controlling the execution of the self-test is further provided.
The semiconductor device according to claim 6, wherein the test controller executes the self-test on the dormant circuit block based on the operation schedule of each of the plurality of circuit blocks. The test controller generates a pattern initialization input and
The semiconductor device according to claim 7, wherein the pattern generator generates the test pattern based on the pattern initialization input. The semiconductor device according to claim 5, wherein the pattern input is an input to be assigned to any of the plurality of circuit blocks in the normal operating state of the semiconductor device. This is a test method for self-testing the semiconductor device (10).
Steps to input pattern input to the circuit block,
A calculation step for causing the circuit block to perform the calculation of the pattern input, and
A compression step that compresses the response output by the above operation to generate a test response,
The step of obtaining the result of the self-test of the circuit block by comparing the test response with the reference value,
Including
A method for testing a semiconductor device in which the same pattern input is input to a plurality of the circuit blocks. The reference value is an expected value prepared in response to the pattern input.
In the calculation step, a circuit block having a vacancy in the operation schedule is selected from the plurality of circuit blocks and the calculation is performed.
The method for testing a semiconductor device according to claim 10. The plurality of circuit blocks have the same function as each other.
The reference value of each of the plurality of circuit blocks is a test response that compresses the response of the other circuit block that shares the same pattern input as the circuit block.
The method for testing a semiconductor device according to claim 10. The method for testing a semiconductor device according to claim 12, wherein the pattern input is an input to be assigned to any one of the plurality of circuit blocks in the normal operating state of the semiconductor device.

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