JP2021156619A - Semiconductor device and test method of semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of automatically executing a LBIST(incorporated self-test of a logic circuit).SOLUTION: A semiconductor device includes a plurality of circuit blocks 50 that executes normal processing and self-test; a normal controller 70 that controls execution of the normal processing of the plurality of circuit blocks 50; and a test controller 30 that controls execution of the self-test of the plurality of circuit blocks 50. The test controller 30 controls execution of the self-test at least on the basis of an operation state of each of the plurality of circuit blocks 50 and control cause information for controlling execution of the self-test.SELECTED DRAWING: Figure 5

Description

The present invention relates to a semiconductor device that performs self-testing, and a method for testing the semiconductor device.

In recent years, in semiconductor integrated circuits mounted on products for automobiles and industries, there are cases where self-testing is required between normal operations due to functional safety requirements. A test performed by mounting a circuit for performing such a self-test on a semiconductor integrated circuit is called an embedded self-test (BIST: Built-In Self-Test). Of these, the BIST performed on the logic circuit is called an L (Logic) BIST (Patent Document 1).

Japanese Unexamined Patent Publication No. 2013-253840

In LBIST (embedded self-test of logic circuit), creating a software program for executing and controlling a test is a heavy burden for a user of a semiconductor integrated circuit. Therefore, there is a demand for a method that can automatically execute a test when normal processing is not performed. Further, since the execution of the self-test should not adversely affect the normal processing, a mechanism for suppressing the total power required for the execution of the normal processing and the self-test is desired. Furthermore, from the viewpoint of reliability, for normal processing and self-test execution, a mechanism that prevents only specific circuit blocks from being used, adjusts all circuit blocks to be used evenly, and prolongs the life of the entire circuit block. Is desired.

One object of the present invention is to provide a semiconductor device capable of automatically executing a built-in self-test of a logic circuit (hereinafter, simply referred to as "self-test"). Another object of the present invention is to provide a semiconductor device capable of suppressing the influence of self-testing on normal processing. Yet another object of the present invention is to prolong the life of the entire circuit block in a self-testing semiconductor device.

The present invention employs the following technical means to solve the above problems. The scope of claims and the reference numerals in parentheses described in this section are examples showing the correspondence with the specific means described in the embodiments described later as one embodiment, and limit the technical scope of the present invention. It's not something to do.

The semiconductor device (10) of one aspect includes a plurality of circuit blocks (50) that perform normal processing and self-test, a normal controller (70) that controls execution of the normal processing of the plurality of circuit blocks, and the above. A test controller (30) for controlling the execution of the self-test of a plurality of circuit blocks is provided, and the test controller is for controlling the operating state of each of the plurality of circuit blocks and the execution of the self-test. The execution control of the self-test is performed based on at least the control cause information.

According to this configuration, the test controller controls the execution of the self-test based on at least the operating state of each of the plurality of circuit blocks and the control cause information for controlling the execution of the self-test, so that the self-test is automatically performed. Can be executed.

In one aspect of a semiconductor device test method, the operating state of each of a plurality of circuit blocks that perform normal processing and self-test is acquired, and control cause information for performing self-test execution control is acquired. The execution control of the self-test is performed based on at least the operating state of each of the plurality of circuit blocks and the control cause information for performing the execution control of the self-test.

According to this configuration, the self-test execution control is performed based on at least the operating state of each of the plurality of circuit blocks and the control cause information for performing the self-test execution control, so that the self-test can be automatically executed. ..

FIG. 1 is a diagram for explaining parallel processing which is a premise of this embodiment. FIG. 2 is a diagram showing an example of a system configuration for executing the parallel processing shown in FIG. FIG. 3 is a diagram showing a configuration example of the DFP used in FIG. FIG. 4 is a diagram showing a basic configuration of a semiconductor device according to an embodiment of the present invention including an LBIST circuit. FIG. 5 is a diagram showing a configuration according to a self-test of the semiconductor device according to the embodiment of the present invention. FIG. 6 is a table showing an example of information of a plurality of circuit blocks held by the test controller according to the embodiment of the present invention. FIG. 7 is a table showing an operation schedule example of the normal processing and the self-test of the semiconductor device according to the embodiment of the present invention. FIG. 8 is a table showing an example in which the self-test priority of the information of a plurality of circuit blocks held by the controller according to the embodiment of the present invention is set to the lowest “0”. FIG. 9 is a table showing an example of the operation schedule of the normal processing and the self-test of the semiconductor device in the case of FIG. FIG. 10 is a table showing an example in which the self-test priority of the information of a plurality of circuit blocks held by the controller according to the embodiment of the present invention is set to the highest “4”. FIG. 11 is a table showing an example of the operation schedule of the normal processing and the self-test of the semiconductor device in the case of FIG. FIG. 12 is a diagram showing a basic configuration of a semiconductor device according to an embodiment of the present invention including an LBIST circuit in which one pattern generator is shared by all circuit blocks. FIG. 13 is a diagram showing a basic configuration of a semiconductor device according to an embodiment of the present invention, which includes not only a pattern generator 40 but also an LBIST circuit when a plurality of circuit blocks 50 share a code compressor 60. .. FIG. 14 is a diagram showing a basic configuration of a semiconductor device according to an embodiment of the present invention, which includes an LBIST circuit according to another embodiment.

Hereinafter, the present embodiment will be described with reference to the accompanying drawings. It should be noted that the embodiments described below show an example of the case where the present invention is carried out, and the present invention is not limited to the specific configuration described below. In carrying out the present invention, a specific configuration according to the embodiment may be appropriately adopted.

FIG. 1 (A) shows a program code having a graph structure, FIG. 1 (B) shows a thread state, and FIG. 1 (C) shows a state of parallel processing.

As shown in FIG. 1A, the program targeted for processing in the present embodiment has a graph structure in which data and processing are divided. This graph structure maintains the task parallelism and graph parallelism of the program.

When the program code shown in FIG. 1 (A) is automatically vectorized by the compiler and the graph structure is extracted, a large number of threads can be generated as shown in FIG. 1 (B).

The large number of threads shown in FIG. 1 (B) can be executed in parallel as shown in FIG. 1 (C) by performing dynamic register allocation and thread scheduling by hardware. By dynamically allocating register resources during execution, multiple threads can be executed in parallel for different instruction streams.

Subsequently, with reference to FIG. 2, a data processing system 2 which is a system configuration example including a DFP (Data Flow Processor) 10 as an accelerator for performing dynamic register arrangement and thread scheduling will be described.

The data processing system 2 includes a DFP 10, an event handler 20, a host CPU 21, a ROM 22, a RAM 23, an external interface 24, and a system bus 25. The host CPU 21 is an arithmetic unit that mainly performs data processing. The host CPU 21 supports an OS. The event handler 20 is a part that generates interrupt processing.

The ROM 22 is a read-only memory. The RAM 23 is a memory for reading and writing. The external interface 24 is an interface for exchanging information with the outside of the data processing system 2. The system bus 25 is for transmitting and receiving information between the DFP 10, the host CPU 21, the ROM 22, the RAM 23, and the external interface 24.

The DFP 10 is positioned as an individual master provided to cope with the heavy computing load of the host CPU 21. The DFP 10 is configured to support interrupts generated by the event handler 20.

Subsequently, the DFP10 will be described with reference to FIG. As shown in FIG. 3, the DFP 10 includes a command unit 12, a thread scheduler 14, an execution core 16, and a memory subsystem 18.

The command unit 12 is configured to enable information communication with the config interface. The command unit 12 also functions as a command buffer.

The thread scheduler 14 is a part that schedules the processing of a large number of threads as illustrated in FIG. 1 (B). The thread scheduler 14 can perform scheduling across threads.

The execution core 16 has four processing elements, PE # 0, PE # 1, PE # 2, and PE # 3. The execution core 16 has a large number of pipelines that can be scheduled independently.

The memory subsystem 18 has an arbiter 181 and an L1 cache 18a and an L2 cache 18b. The memory subsystem 18 is configured to enable information communication with the system bus interface and the ROM interface.

FIG. 4 is a diagram showing a basic configuration of a semiconductor device according to an embodiment of the present invention including an LBIST circuit. In this specification, the output of the circuit block 50 when a test input described later is given is expressed as a "response", and the response of the circuit block 50 as the origin is used for the comparison described later as a "test response". Is expressed. The LBIST circuit of FIG. 4 includes a test controller 30, a pattern generator 40, a circuit block 50, and a code compressor 60. The test controller 30 includes a pattern initializer 301 and an expected value comparator 302. The test controller 30 controls the execution of the self-test of the circuit block 50. Specifically, a clock is generated, and the pattern initializer 301 generates an initial value of the test pattern and supplies it to the pattern generator 40.

The pattern generator 40 generates a test pattern as a test input according to the initial value given by the pattern initializer 301. A pseudo-random number generator (PRPG: Pseudo Random Pattern Generator) is generally used to generate the test pattern, but other methods may be used. The test pattern generated by the pattern generator 40 is input to the circuit block 50, and the circuit block 50 performs an operation based on the test pattern. The circuit block 50 is a logic circuit to be tested, and the processing element PE in FIG. 3 corresponds to this as an example.

The code compressor 60 compresses the response of the circuit block 50 to generate a test response. The response to the test pattern output by the circuit block 50 is a long serial data, and it is uneconomical to store this as it is in the ROM. Therefore, the test controller 30 holds the compressed result calculated in advance as an expected value and uses it. By design, the test response, which is the compressed value obtained by compressing the response generated by the circuit block 50 by the code compressor 60, and the expected value of the test controller 30 are the same. As a typical code compressor, a multi-input signature register (MISR: Multiple Input Signature Register) is used, but other compressors may be used as long as the conditions are satisfied.

The expected value comparator 302 compares the test response, which is the compressed value output from the code compressor 60, with the expected value calculated in advance and stored inside the test controller 30 or in the ROM or the like. If the test response and the expected value are the same, the circuit block 50 is operating normally. If the test response and the expected value are different, the circuit block 50 is suspected to be defective.

Hereinafter, the configuration of the semiconductor device according to the embodiment of the present invention including the LBIST circuit will be described in detail, but each component has the same function as the component of the example shown in FIG. Therefore, the same reference numerals are given and duplicate description will be omitted.

FIG. 5 is a diagram showing a configuration according to a self-test of the semiconductor device according to the embodiment of the present invention. The semiconductor device 100 includes a plurality of circuit blocks 50. Each of the plurality of circuit blocks 50 is normally controlled by the processing controller 70, and processes of a plurality of threads are executed in parallel. The configuration including the thread scheduler shown in FIG. 3 corresponds to the normal processing controller 70.

Each of the plurality of pattern generators 40 generates a test pattern for performing a self-test. The same number of pattern generators 40 as the circuit blocks 50 may be provided, and the number of pattern generators 40 may be less than the number of circuit blocks 50. The input selector 80 is provided corresponding to each of the plurality of circuit blocks 50, and the corresponding circuit block 50 is subjected to a self-test by inputting the generated test pattern of the pattern generator 40. Select whether to execute the normal processing by inputting the normal processing data from the normal processing controller 70.

The input selector 80 is controlled by the test controller 30 to select the execution of the self-test, and is controlled by the normal controller 70 to select the execution of the normal processing. That is, the input selector 80 is controlled by the test controller 30 and the normal processing controller 70. The input selector 80 may be controlled by only one of the test controller 30 and the normal processing controller 70. For example, the input selector 80 is controlled by the test controller 30 to select the execution of the self-test and self. Whenever the test execution is not selected, the normal processing execution may be selected.

When the output from the circuit block 50 is the output of the result of the self-test, the output selector 90 outputs the output to the code compressor 60. The output selector 90 is controlled by the test controller 30 to select self-test, and whenever self-test is not selected, normal control is selected. The output selector 90 may be controlled by the test controller 30 and the normal processing controller 7. In this case, the output selector 90 may select the self-test under the control of the test controller 30 and perform the normal control controlled by the normal controller 70.

Each of the plurality of code compressors 60 compresses the output of the self-test result to generate a compressed value. This compressed value is a compressed output of the circuit block 50 when the test pattern is processed by the circuit block 50, and is a test response. The same number of code compressors 60 as the circuit blocks 50 may be provided, and the number of code compressors 60 may be less than the number of circuit blocks 50.

The test controller 30 includes a pattern initializer 301, a normal processing counter 303, a self-test counter 304, and an expected value comparator 302. The pattern initializer 301 generates an initial value for generating a test pattern and outputs it to the pattern generator 40. The expected value comparator 302 determines whether or not there is a defect in the self-tested circuit block 50 by comparing the test response from the code compressor 60 with the reference value.

The test controller 30 further includes a normal processing counter 303 that counts the number of times the normal processing is executed in each circuit block 50, and a self-test counter 304 that counts the number of times the self-test is executed in each circuit block 50.

The test controller 30 controls the execution of the self-test in the plurality of circuit blocks 50 based on the execution history of the plurality of circuit blocks 50, that is, the count values of the normal processing counter 303 and the self-test counter 304. In the execution control of the self-test, the test controller 30 determines which circuit block 50 is to execute the self-test, and controls the input selector 80 corresponding to the determined circuit block 50 to select the circuit block 50. A pattern generator 40 corresponding to the circuit block 50 is selected to perform a self-test. Further, the test controller 30 interrupts the self-test executed in the circuit block 50 as the execution control of the self-test.

The test controller 30 and the normal processing controller 70 are connected, and from the normal processing controller 70, signals (start interrupt, start flag, etc.) indicating the start of normal processing in each circuit block 50 and normal processing information are used as processing information. A signal (end interrupt, end flag, etc.) indicating the end of processing is input to the test controller 30. Further, when the circuit block 50 is waiting for processing, the normal processing controller 70 also inputs a signal to that effect to the test controller 30 as processing information.

From the test controller 30, signals (start interrupt, start flag, etc.) indicating the start and end of the self-test in each circuit block 50 are input to the normal processing controller 70 as control information. The normal processing controller 70 selects a circuit block 50 that has not been subjected to normal processing and self-testing, and causes the normal processing to be executed. In the execution control of the normal process, the normal process controller 70 determines which circuit block 50 is to execute the normal process, and controls the input selector 80 corresponding to the determined circuit block 50 to perform the normal process. To execute.

When the test controller 30 receives a signal from the normal processing controller 70 that the normal processing of the circuit block 50 has been completed, the test controller 30 switches the input selector 40 of the circuit block 50 to a self-test to test the pattern generator 40. The pattern is input to the circuit block 50 to cause the circuit block 50 to perform a self-test. As a result, in the circuit block 50, the self-test can be automatically executed after the normal processing is completed.

The test controller 30 controls the execution of the self-test based on the operating state of each circuit block 50 and the control cause information for controlling the execution of the self-test. The operating state of the circuit block 50 includes a normal processing state in which the circuit block 50 is performing normal processing, a self-test state in which the circuit block 50 is performing self-test, and a normal processing state in which the circuit block 50 is waiting for normal processing. There are a processing waiting state, a self-test waiting state in which the circuit block 50 is waiting for a self-test, and a hibernation state that does not correspond to any of the normal processing state, the self-test state, the normal processing waiting state, and the self-test processing waiting state. be.

The test controller 30 determines that the operating state of the circuit block 50 is the normal processing state or the normal processing waiting state based on the processing information input from the normal processing controller 70. Further, the test controller 30 determines that it is in the self-test state or the self-test waiting state according to the execution control of the self-test. Further, the test controller 30 determines that the test controller 30 is not in any of the normal processing state, the normal processing waiting state, the self-test state, and the self-test waiting state based on the processing information from the normal processing controller 70 and the self-test execution control. When it does, it is judged to be in hibernation.

For each circuit block 50, the test controller 30 uses the count value of the normal processing counter 303 as the execution history and the count value of the self-test counter 304 as the execution history, and further as the execution history, the total value (total number of executions) of both counters and both. The difference between the counters (count value of the normal processing counter 303-count value of the self-test counter 304) is calculated.

FIG. 6 is a table showing an example of information of a plurality of circuit blocks 50 held by the test controller 30. FIG. 6 shows an example in which the circuit blocks 50 are four circuit blocks a to d. As shown in FIG. 6, the test controller 30 uses the count value 31 of the normal processing counter 303 of each circuit block 50, the count value 32 of the self-test counter 304, and the total value of both counters (total number of executions) as control cause information. ) 33, the difference 34 between the two counters, the priority 35 for normal processing, and the priority 36 for self-test, and the execution state indicating whether or not each circuit block 50 is being executed is executed. The medium flag 35 and the number of normal processing jobs (waiting normal job number) 36 in the waiting state are held. The test controller 30 controls the execution of the self-test of each circuit block 50 based on the control cause information and the operating state. The normal processing priority 35 and the self-test priority 36 can be arbitrarily set and can be changed after the setting.

FIG. 7 is a table showing an example of an operation schedule for normal processing and self-test of a semiconductor device. In the figure, "W" indicates execution of normal processing, and "L" indicates execution of self-test. In the example of FIG. 7, the circuit blocks a, b, and c are executing the normal processing at time 0, the circuit block d is in the hibernation state, and there is no waiting normal job. When the normal processing is completed in the circuit block a at time 5, the normal processing controller 70 inputs processing information (for example, an end interrupt) indicating that fact to the test controller 30.

When the test controller 30 receives the processing information indicating that the normal processing has been completed in the circuit block a from the normal processing controller 70, the test controller 30 uses this as a trigger to perform a self-test on the input selection unit 80 corresponding to the circuit block a. Output a control signal to select. The input selection unit 80 switches to the execution of the self-test, inputs a test pattern to the circuit block a, and causes the circuit block a to execute the self-test.

When a normal processing start instruction is input to the circuit block 50 executing the self-test during the test execution, the test controller 30 has the normal processing priority 35 and the self-test priority 36 of the circuit block 50. Based on, select whether to suspend the self-test and execute the normal process, or to give priority to the self-test and wait for the normal process to complete the test. Specifically, the test controller 30 selects the higher of the normal processing priority 35 and the self-test priority 36.

When the self-test is interrupted, the test controller 30 may cause a large voltage fluctuation if it is stopped suddenly, which may cause the surrounding circuits to malfunction. Therefore, in order to prevent this, the test controller 30 is not stopped suddenly. , Gradually stop the running self-test by gradually lowering the clock rate.

When the number of pattern generators 40 or code compressors 60 is less than the number of circuit blocks 50, the test controller 30 causes the pattern generator 40 or code compressor 60 to wait for execution of the self-test if there is no space. back. In this case, the information on the number of the pattern generator 40 and the code compressor 60 is also the control cause information.

The test controller 30 counts normal processing as an execution history when the number of pattern generators 40 or code compressors 60 is less than the number of circuit blocks 50 and a plurality of circuit blocks 50 are waiting for self-test execution. The circuit block 50 having the largest difference 34 between the value 31 and the self-test counter 32 is given priority for executing the self-test. For example, in the example of FIG. 6, the circuit block a having the maximum difference 34 between the two counters is made to execute the self-test in preference to the circuit block c.

Alternatively, when the number of pattern generators 40 or code compressors 60 is smaller than the number of circuit blocks 50, the test controller 30 gives priority to the circuit block 50 in which the total 33 of both counters as the execution history is large and self-tests. May be executed. In the case of FIG. 6, of the circuit block a and the circuit block c, the circuit block c has a larger total of 33, so that the circuit block c may be prioritized to execute the self-test.

Further, when the plurality of circuit blocks 50 are waiting for self-test execution and the code compressor 60 is free of more than the number of waiting for execution, the test controller 30 considers the total power consumption of the self-test. An upper limit is set for the number of self-tests that can be executed at one time so that the total power consumption does not exceed a predetermined upper limit, and if the upper limit is exceeded, the self-test execution is awaited. In this case, the upper limit of the total power consumption is also the control cause information.

The test controller 30 passes the normal processing count value 31 and the self-test count value 32 as control instructions to the normal processing controller 70. When allocating normal processing to each circuit block 50, the normal processing controller 70 gives priority to the circuit block 50 having a small normal processing count value 31 when a larger number of circuit blocks 50 than the number waiting for processing are available. To execute normal processing. As a result, it is possible to reduce the bias in the number of times of normal processing in the plurality of circuit blocks 50, and it is possible to prolong the life of the circuit blocks 50.

At this time, the test controller 30 can refer to either or both of the normal processing count value 31 and the self-test count value 32 and prioritize them by a method different from the above. For example, the test controller 30 may preferentially execute the wait job on the circuit block 50 having the smallest total value 33 of both counters.

Further, the test controller 30 may be limited so that the total 33 does not exceed the set number by taking into account not only the self-test count value 32 but also the normal processing count value 31.

When the test controller 30 tries to execute the self-test, it may confirm whether or not there is a processing wait for the normal processing, and if there is a processing waiting, the normal operation may be prioritized and the self-test may not be executed.

Based on the normal processing priority 35 and the self-test priority 36, the test controller 30 may execute the self-test in preference to the normal processing when the self-test priority is higher. Further, in the test controller 30, when the number of pattern generators 40 or code compressors 60 is smaller than the number of circuit blocks 50 and the plurality of circuit blocks 50 are waiting for self-test execution, the test controller 30 of each circuit block 50. The self-test priority 36 may be compared, and the circuit block 50 having the highest self-test priority 36 may be selected to execute the self-test.

For example, when there are four circuit blocks, if the priority of the self-test is set to the lowest "0", the normal processing is prioritized and executed, and the self-test is not executed. On the contrary, if the priority of the self-test is set to the highest "4", the self-test can be executed with priority over the normal processing.

FIG. 8 is an example in which the self-test priority 36 is set to the lowest “0”, and FIG. 9 is a table showing an example of an operation schedule of each circuit block 50 in the case of FIG. As shown in FIG. 9, the processing of the circuit block a ends at time 5, but since there is one waiting for normal processing and the self-test priority of the circuit block a is the lowest, the self in the circuit block a The test is not executed, and the waiting normal processing is executed in the circuit block a. Then, the test controller 30 starts the self-test of the waiting circuit block a at time 13 after the normal processing in the circuit block a is completed.

FIG. 10 is an example in which the self-test priority 36 is set to the highest “4”, and FIG. 11 is a table showing an example of an operation schedule of each circuit block 50 in the case of FIG. As shown in FIG. 10, since the processing of the circuit block a is completed at time 5, there is one waiting for the normal processing, and the self-test has the highest priority, the self-test is executed and the normal processing has been waiting. Processing will continue to wait. Since the normal processing ends in the circuit block b at the time 11 when the normal processing is in the waiting state, the waiting normal processing is executed in the circuit block b from the time 13.

As described above, the number of pattern generators 40 and code compressors 60 may be the same as the number of circuit blocks 50 or less than the number of circuit blocks 50. The pattern generator 40 and the code compressor 60 may be one.

FIG. 12 is a diagram showing an example of the configuration of the LBIST circuit when one pattern generator 40 is shared by all the circuit blocks 50. In this example, the plurality of circuit blocks 50 have the same function. That is, the same test pattern is given as a test input to a plurality of circuit blocks 50 having the same function. Therefore, if the plurality of circuit blocks 50 operate normally, the response to the common test pattern will be the same. Therefore, in the expected value comparator 302 of the test controller 30, one expected value may be stored. As a result, it is not necessary to mount the same number of pattern generators 40 as the circuit block 50 on the semiconductor device, so that the circuit area for testing can be reduced and the manufacturing cost of the semiconductor device can be reduced.

In the example of FIG. 12, since a plurality of code compressors 60 (the same number as the circuit blocks 50) are provided, it is possible for the plurality of circuit blocks 50 to execute the self-test at the same time.

When a plurality of circuit blocks 50 having the same function share a test pattern, the expected value comparator 302 compares the test response of the plurality of circuit blocks 50 with the expected value stored in advance, and each circuit block. Instead of determining whether the circuit block 50 is normal, it can be determined whether the circuit block 50 is normal by comparing the test responses of the plurality of circuit blocks 50 with each other. In this case, it is not necessary to prepare in advance the expected value corresponding to the test pattern generated by the pattern generator 40, and it is not necessary to store it.

In this case, the test controller 30 determines that all the circuit blocks 50 are normal when the test responses obtained from the two or more code compressors 60 are the same as a result of the comparison by the code comparator 303. to decide. Further, the test controller 30 determines that one of the circuit blocks 50 has a defect when the test response is different. Further, when the test controller 30 performs a self-test on three or more circuit blocks 50 at the same time, the circuit block 50 in which a defect has occurred can be identified by a majority vote.

When comparing the test responses of a plurality of circuit blocks 50, the responses of two or more circuit blocks 50 may be directly compared as test responses without using the code compressor 60. As a result of comparison, if two or more test responses are the same, a defect in the circuit block 50 can be detected without calculating the compression value by the code compressor 60. As a result, the code compressor 60 becomes unnecessary, and the circuit area for testing can be further reduced. In this case, instead of the code comparator 302, a simpler comparator that uses, for example, a bit operation can be used. However, when the code compressor 60 is not used, it is necessary to carry out the test on two or more circuit blocks 50 at the same time. When the code compressor 60 is used, comparison can be performed even if the test timing is deviated.

In the present embodiment, it is not necessary to prepare expected values for all test patterns in advance and incorporate them into the circuit, so that the memory capacity used for LBIST can be reduced. Further, regardless of whether or not the expected value is set, the pattern initializer 301 can pass an arbitrary initial value to the pattern generator 40 for testing. Further, even when a new test pattern in which the expected value is not incorporated is required after manufacturing the semiconductor device, a defect in the circuit block 50 can be found.

FIG. 13 is a diagram showing an example of the configuration of the LBIST circuit when not only the pattern generator 40 but also the code compressor 60 is shared by a plurality of circuit blocks 50. This eliminates the need to mount the same number of code compressors 60 as the circuit block 50 on the semiconductor device. According to this form, the circuit area for testing can be further reduced as compared with the example of FIG. 12, and the manufacturing cost of the semiconductor device can be reduced.

In the example of FIG. 13, the test controller 30 controls so that the plurality of circuit blocks 50 do not execute the self-test at the same time.

FIG. 14 is a diagram showing an example of the configuration of the LBIST circuit of another embodiment. In this example, the circuit block 50 executes the same processing generated by the normal processing controller 70 for the normal processing instead of the test pattern from the pattern generator 40. In this example as well, the plurality of circuit blocks 50 have the same function.

The input itself assigned to one of the circuit blocks 50 in the normal operating state of the semiconductor device is the test input. The code compressor 60 is composed of two or more, as in the example of FIG. Also in this embodiment, a plurality of circuit blocks 50 perform the same processing, and the code comparator 303 performs test responses that are compression values generated by two or more code compressors 60 for two or more responses. compare. If there are three or more code compressors 60, tests can be performed on three or more circuit blocks 50 at the same time, and the circuit block 50 in which a defect has occurred can be identified by a majority vote. Also, for two or more circuit blocks at the same time. It is shown in FIG. 12 that the code compressor 60 can be unnecessary if the test is to be performed, and that a simpler comparator can be used instead of the code comparator 302 in the above-described configuration. It is the same as the example of.

With this configuration, the pattern generator 40 is not required, so that the circuit area can be further reduced and the manufacturing cost can be reduced. Further, in the product test stage, the test input that the tester wants to test can be input to the circuit block 50 and used for the self-test. Unlike a normal LBIST circuit that uses a random pattern, the user can perform a test that focuses on the targeted location of the circuit block 50. In addition, with this configuration, it is possible to test patterns that can occur in actual use but cannot be assumed at the design stage.

The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Those skilled in the art with appropriate design changes to these specific examples are also included in the scope of the present disclosure as long as they have the features of the present disclosure. Each element included in the above-mentioned specific example and its arrangement, conditions, shape, etc. are not limited to those illustrated, and may be changed as appropriate. The combinations of the elements included in each of the above-mentioned specific examples can be appropriately changed as long as there is no technical contradiction.

For example, the pattern generator 40 may generate different test patterns. In this case, test variations having different estimated execution times may be generated, and estimated execution time information may be added to the test variations. By adding the estimated execution time information, the test controller 30 can select various test variations from those in which execution is completed in a short time to those in which execution is long.

The test controller 30 refers to how long the hibernation of the circuit block 50 for which the test is to be executed lasts, and selects the optimum test pattern having an assumed execution time that ends within the hibernation time. By providing variations in the estimated execution time, it is possible to execute a short-time test even for the circuit block 50, which cannot be tested for the standard execution time due to insufficient pause time. Further, since the circuit block 50 having a long pause time can be tested for a long time, computational resources can be used without waste.

Further, when a plurality of code compressors 60 are present, the pattern generator 40 and the controller 70 during normal operation may be switched so that they can be used for the test. As a result, it is possible to confirm whether the circuit block 50 is operating normally under the condition that the expected value is registered in the non-volatile memory, and the condition that the expected value is not registered or the output of the controller. In the case of operating in, the defect of the circuit block 50 can be detected by comparing the test responses which are the compressed values of the plurality of code compressors 60.

Even in the case of the embodiment in which the pattern generator 40 and the code compressor 60 are only one, the standby system pattern generator 40 and the code compressor 60 may be separately prepared. Even if the pattern generator 40 or the compressor 60 fails, the test function can be maintained by switching to the standby system.

When the functions of the plurality of circuit blocks 50 are different from each other, the test controller 30 uses a combination of a test pattern and an expected value prepared for each type of the circuit block 50. Even in this configuration, it is not necessary to provide the pattern generator 40 and the code compressor 60 for each circuit block 50, the circuit area of the semiconductor device can be reduced, and the manufacturing cost can be reduced. Further, if there is a combination having the same function in the variation of the circuit block 50, the occurrence of a defect can be known by comparing the test responses with each other as described above.

A power control mechanism is added to the test controller 30 and the normal processing controller 70, a self-test is performed after the normal processing is completed, and then the power of the block is turned off when there is no processing request to reduce power consumption. May be good.

Further, in the above embodiment, the test controller 30 has a priority 35 for normal processing and a priority 36 for self-test as control cause information, but has only one of them. May be good. When the test controller 30 stores the normal processing priority 35, the test controller 30 preferentially causes the circuit block 50 having the lower normal processing priority 35 to execute the self-test, or stores the self-test priority 36. If so, the circuit block 50 having a high self-test priority 36 is given priority to execute the self-test.

10: DFP, 30: Test controller, 40: Pattern generator, 50: Circuit block,
60: Code compressor, 70: Normal processing controller, 80: Input selector, 90: Output selector

Claims (18)

It is a semiconductor device (10).
Multiple circuit blocks (50) that perform normal processing and self-testing,
A normal controller (70) that controls execution of the normal processing of the plurality of circuit blocks, and a normal controller (70).
A test controller (30) that controls execution of the self-test of the plurality of circuit blocks, and a test controller (30).
With
The test controller is a semiconductor device that controls the execution of the self-test based on at least the operating state of each of the plurality of circuit blocks and the control cause information for controlling the execution of the self-test. The semiconductor device according to claim 1, wherein the control cause information is information regarding the execution history of the normal processing and / or the self-test of each of the plurality of circuit blocks. The semiconductor device according to claim 2, wherein the control cause information includes the number of times the normal process is executed for each of the plurality of circuit blocks. The semiconductor device according to claim 2, wherein the control cause information includes the number of times the self-test is executed for each of the plurality of circuit blocks. The control cause information is a total number of executions including the sum of the number of executions of the normal processing of each of the circuit blocks and the number of executions of the self-test.
The semiconductor device according to claim 2, wherein the test controller preferentially causes the circuit block having a small total number of executions to execute the self-test. The control cause information includes the self-test priority set for each of the plurality of circuit blocks.
The semiconductor device according to claim 1, wherein the test controller preferentially causes the circuit block having a higher priority of the self-test to execute the self-test. The control cause information includes the priority of the normal processing set for each of the plurality of circuit blocks.
The semiconductor device according to claim 1 or 6, wherein the test controller preferentially causes the circuit block having a low priority of the normal processing to execute the self-test. The operating state includes a normal processing state in which the circuit block is performing the normal processing, a self-test state in which the circuit block is performing the self-test, and a normal processing in which the circuit block is waiting for the normal processing. Including at least waiting state
The semiconductor device according to claim 1, wherein the test controller preferentially causes the circuit block, which does not correspond to any of the normal processing state, the self-test state, and the normal processing waiting state, to execute the self-test. .. The operating state includes at least a normal processing state in which the circuit block is performing the normal processing and a self-testing state in which the circuit block is performing the self-test.
The semiconductor device according to claim 1, wherein the test controller does not cause any of the circuit blocks to newly execute the self-test when any of the plurality of circuit blocks is in the self-test state. The operating state includes at least a self-testing state in which the circuit block is performing the self-testing.
The claim that the test controller slowly stops the self-test being executed when the self-test being executed by the circuit block in the self-test state is interrupted and the normal processing is performed. The semiconductor device according to 1. The plurality of circuit blocks receive test inputs in the self-test.
The test controller acquires a test response originating from a response output by each of the plurality of circuit blocks with respect to the test input, and compares each of the plurality of circuit blocks with a reference value. Equipped with a comparator that obtains the result of the self-test of the circuit block in
The semiconductor device according to claim 1, wherein the plurality of circuit blocks share the test input. A code compressor (60) that compresses the response and produces the compressed value is further provided.
The semiconductor device according to claim 11, wherein the comparator compares the compressed value with the reference value as the test response. The semiconductor device according to claim 12, wherein the code compressor is shared by the plurality of circuit blocks. The semiconductor device according to claim 12, wherein the reference value is an expected value prepared in response to the test input. The plurality of circuit blocks have the same function as each other and have the same function.
The semiconductor device according to claim 11, wherein the reference value of each of the plurality of circuit blocks is a test response of another circuit block that shares the same test input as the circuit block. Further equipped with a pattern generator (40) that generates a test pattern,
The semiconductor device according to any one of claims 11 to 15, wherein the plurality of circuit blocks receive the test pattern generated by the pattern generator as the test input. It is a test method for semiconductor devices.
Acquire the operating status of each of multiple circuit blocks that perform normal processing and self-testing,
Acquire control cause information for controlling the execution of self-test,
A test method for controlling the execution of the self-test based on at least the operating state of each of the plurality of circuit blocks and the control cause information for controlling the execution of the self-test. The test method according to claim 17, wherein the circuit block is made to execute the self-test when the information indicating that the normal processing is completed in the circuit block is acquired as the operating state.

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