JPS60231186A - Self-testing circuit - Google Patents

Abstract

PURPOSE:To enable drastic simplfication of the testing process without requiring the generation of any test pattern and the output expected value by generating a comparison reference value from output response self of a circuit to be tested without preparing it beforehand. CONSTITUTION:When a trigger signal is applied as test control circuit input signal 13 by a test direction to drive a test control circuit 12, functional blocks are made ready by a control circuit output signal 14 and a state switching circuit 7 applies a test pattern 6 as output of a test pattern generator 5 to a circuit 1 to be tested. On the other hand, a pseudo expected value generation circuit 8 decides by majority on the output response of N units to use the value of the output line 9 as comparison reference value. The output responses from output terminals 3 of these units are compared with the comparison reference value by a comparison circuit 10 and they are judged to be normal when coinciding therewith while otherwise abnormal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a self-test circuit for a logic device having a built-in test function.

(Prior Art) Figure 1 shows the configuration of a conventional test circuit for a logic device. (,) shows a configuration method for determining the pass/fail of the entire circuit under test, and (b) shows a configuration method for configuring the circuit under test. This is a construction method that determines the quality of each unit block.

In FIGS. 1(a) and (b), 1 is a circuit under test, which is N (N is any integer) logic circuits (hereinafter referred to as functional units or simply units) having the same function.
Consisting of 11 to IN, 2 is an input terminal of the circuit under test, 3 is an output terminal of the circuit under test, 4 is an external input signal which is the first signal, and 5 is a test bang generator that applies to the circuit under test. 7 is a state switching circuit, which selects the test pattern 6 in the second test state, and selects the test pattern 6 in the first state, the normal state. Select signal 4 and test circuit 1
Output to input terminal 2 of. Reference numeral 8 denotes an expected value generation circuit for generating a correct output response value of the circuit under test 1 corresponding to the test pattern 6, which is composed of a memory circuit and a sequence control circuit for controlling the memory circuit.
outputs the expected value of the output response. 10 is a comparison circuit for comparing the output value from the output line 9 of the expected value generation circuit 8 and the output value from the output terminal 3 of the circuit under test 1 to judge whether it is good or bad; 11 is the judgment result for the circuit under test; In the case of FIG. 1(a), it is a flag value output indicating the pass/fail status of the entire circuit under test, and in the case of FIG. 1(b), it is a flag value output indicating the status of each unit 11-1. The pass/fail status is displayed for each I. 12
1 is a test control circuit for controlling the whole, 13 is a third signal which is an input signal of the test control circuit, and 14 is an output signal of the test control circuit 12, which is a control signal for each functional block.

The operation of the logic device having such a configuration will be explained in the order of test state and normal state. In order to perform a test, first, a trigger for test execution is given as an input signal 13 to the test control circuit 12.
to drive. As a result, each functional block is placed in a test state by the control circuit output signal 14 that is the output of the test control circuit 12. In the test state, the test bang generator 5 generates a desired test pattern 6, the state switching circuit 7 selects the test pattern 6 that is the output of the test bang generator,
It is applied to the input terminal 2 of the circuit under test 1. In this case the first
In FIG. 1(a), the value is input as a unique value for each unit, and in FIG. 1(b), it is input as a common value for each unit. The expected value generation circuit 8 outputs the correct response value of the unit corresponding to the input button to its output line 9. As a result, the output result obtained at the output terminal 3 of each unit is compared with the output of the output line 9 of the expected value generation circuit by the comparison circuit 10, and a determination result 11 is outputted as to whether or not the unit has operated correctly.

In the normal state, the state switching circuit 7 is controlled by the test control circuit 12.
selects an external signal input, applies it to the input terminal of the circuit under test 1, and deactivates the operations of the test bang generator 5, expected value generation circuit 8, and comparison circuit 10. As a result, the circuit under test 1 performs normal operation.

As described above, in the conventional logic circuit test configuration, it is necessary to prepare in advance a test pattern that is effective for detecting failures in the circuit under test and the corresponding expected value of the output response. This is determined by logic simulation or by hand, but it is the most troublesome task in the testing process, and the number of steps is said to be proportional to the second to third power of the scale of the logic device. Further, when performing a self-test within the device, a large memory for storing these and hardware for controlling the device must be built-in, which increases the burden on the hardware.

For this reason, it is considered that when creating test patterns, the logical structure is ignored and random patterns are generated, thereby significantly reducing the number of testing steps. Furthermore, it is considered that the amount of data can be reduced by compressing the output response. Even in this case, there are drawbacks such as the need to increase the number of test clicks in order to increase the failure detection rate, omissions due to compression, and the need for expected values.

(Objective of the Invention) In order to eliminate these drawbacks, the present invention focuses on repeatable logic structures, and instead of preparing comparison reference values in advance, we have decided to generate them from the output response of the circuit under test itself. It is intended to provide a self-test circuit, and the drawings will be described in detail below.

(Structure and operation of the invention) FIG. 2 shows the structure of an embodiment of the present invention, and the difference is that a pseudo expected value generating circuit 8' is provided in place of the expected value generating circuit 8 shown in FIG. 1, and all other symbols are the same as those explained in FIG.

The pseudo expected value generation circuit 8' includes each unit 11 to 1 of the circuit under test 1. This is a circuit for creating a comparison reference value from the output response value sent from the output terminal 3 of the unit, and is mainly composed of a majority circuit that outputs the response value that accounts for half of the responses of multiple units. .

To operate this, first, a trigger signal is applied as the test control circuit input signal 13 upon power-on or a test instruction, and the test control circuit 12 is driven.

As a result, each functional block is placed in a test state by the control circuit output signal 14, and the state switching circuit 7 operates to apply the test button 6, which is the output of the test button generator 5, to the circuit under test 1. Since a common test pattern is applied to each unit of the circuit under test, if each unit has no failure or defect, they all exhibit the same output response. Furthermore, even if there is a failure or defect, if the probability of its occurrence is small, the correct response sequence can be estimated from the response sequences of a plurality of units. From this point of view, the pseudo expected value generation circuit 8'' takes a majority vote on the output responses of the N units, and uses the value of the output line 9 as a comparison reference value (correct response series).

Therefore, the comparison reference value obtained on the output line 9 and the output response from the output terminal 3 of each unit are compared, and if they match, it is determined to be normal (good), and if they do not match, it is determined to be abnormal (defective).

FIG. 3 is a flow chart showing the basic concept of another embodiment of the present invention. This is a test method in which the response of a specific unit is assumed to be a pseudo-expected value, and this is compared with the output responses of all other units to determine whether all units are good or bad at the same time. shall be. When a large number of test patterns are applied to multiple units having the same function, the output responses of the good units always match. ■It is rare for the output responses of defective units to match (the probability of occurrence is very small).

First, a specific unit is selected as a comparison standard and its output response is compared with the output responses of other units. As a result, if all units do not match, the unit used as the comparison standard is determined to be a defective unit, other units are selected as new comparison standards, and the test is continued. If there is no unit that can be used as a new comparison standard, all units are judged to be defective and the test ends.
If the comparison result is not ``all inconsistency'', the unit serving as the comparison standard is determined to be a good unit, and the test is terminated using the comparison result as the pass/fail determination result for each unit.

FIG. 4 shows the configuration of another embodiment of the present invention based on the basic concept of FIG. 3, in which 1 to 14 are the same as those explained in FIG. The characteristics are that a match determination circuit 15 is provided to determine whether all matches occur, and that the output 16 of the match determination circuit 15 is input to the test control circuit 12 to control the test sequence. be.

To explain its operation, first, when the power is turned on or a test instruction is given, a trigger signal is applied as the test control circuit input signal 13, and the test control circuit 12 is driven. As a result, each functional block is placed in a test state by the control circuit output signal 14, and the state switching circuit 7 is activated by the test button generator 5.
A test pattern 6 which is the output of is applied to the circuit under test 1. Each unit 1 of the circuit under test 1. ~1. Since l is applied with a common test pattern, all the output responses will be the same if there is no failure or defect. The pseudo expected value generation circuit 8' selects an arbitrary output response of the unit specified by the test control circuit 12 according to the control circuit output signal 14 of the test control circuit 12, and outputs it to the output line 9 as a comparison reference value. . As a result, the comparison circuit 10 compares the comparison reference value of the output line 9 and the output response of the output terminal 3 of each unit, and outputs the determination result 11. If the determination results for each unit are all inconsistent, the coincidence determination circuit 15 regards the unit serving as a comparison standard as a defective unit, and makes it unclear whether the other units are good or bad. Further, if there is at least one unit that matches another unit, the unit used as the comparison standard is regarded as a good unit, and the comparison result of each unit is used as the pass/fail determination result and the test is terminated. Therefore, the coincidence judgment circuit engineer 5
If all of the results do not match, the input of the pseudo expected value generation circuit 8' is further switched to another unit, and the above test cycle is repeated until the comparison standard is determined to be a good unit or there are no more units to switch to.

(Effects) As explained above, in the present invention, the pseudo expected value serving as the comparison standard is generated from the output response of the circuit under test itself during testing, so it is not necessary to consider the input test pattern, and The test process can be greatly simplified without the need to create the expected output value. R for generating another special price
There is an advantage that AM, ROM, and related peripheral circuits are not required, and the amount of hardware can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional logic device test circuit.
Fig. 2 is a diagram showing the configuration of one embodiment of the present invention, Fig. 3 is a flowchart showing the basic concept of another embodiment of the invention, and Fig. 4 is a diagram showing the configuration of another embodiment of the invention. It is. 1...Circuit under test, 1. ~IN...unit (
logic circuit), 2...input terminal, 3...output terminal, 4...external input signal, 5...test button output,
stopper, 6... test pattern, 7... state switching circuit, 8... expected value generation circuit, 8'... pseudo expected value generation circuit, 9... output line, 10... Comparison circuit, 11... Judgment result, I2... Test control section, 13
... Test control circuit input signal, 14... Test control circuit output signal, 15... Coincidence judgment circuit, 16... Coincidence judgment circuit output. Patent applicant: Nippon Telegraph and Telephone Public Corporation Figure 1 (a) Figure 2

Claims (3)

[Claims] (1) In a device that realizes a predetermined function with eight functional units of the same configuration, a first signal from the outside consisting of N sets of signals corresponding to each functional unit is input to the input side, and a first signal is generated inside the device. An input switching means is provided for selecting one of the second signals, and in a first state determined by the control signal, the first signal is selected, and in a second state, the second signal is selected. a reference value generating means that inputs the output of each functional unit to the functional unit and generates a judgment reference value for determining the normality of each functional unit by inputting the output of each functional unit;
Judgment means for comparing the output of the reference value generation means and the output of each functional unit to determine the normality of each functional unit, and control for controlling the whole using the output of the judgment means and a third signal from the outside. A self-test circuit comprising means for determining the normality of each of the functional units based on a third signal. (2) The self-test circuit according to claim (1), characterized in that majority voting means is used as the reference value generation means, which outputs output results that account for a majority of the output results of each functional unit. . (3) Claim (1) characterized in that the output result of an arbitrary functional unit is used as the reference value generation means.
Self-test circuit as described in section.