JP2978900B1 - Pseudo failure generation method and pseudo failure generation method - Google Patents

Abstract

An object of the present invention is to perform a failure processing test on a secondary event after a primary event has occurred. SOLUTION: A primary simulated fault set in a simulated fault event setting register 2a is selected based on a primary simulated fault occurrence timing, and set in a simulated fault event setting register 2b based on a secondary simulated fault occurrence timing. A selector (1, 5) for selecting the generated secondary pseudo-failure; a primary pseudo-failure occurrence timing generator 3 for generating the primary pseudo-failure occurrence timing when a predetermined firmware address is executed; Generating the secondary failure occurrence timing when a predetermined primary pseudo failure is selected by the selection unit;
It has a next pseudo fault occurrence timing generation unit 4 and an error processing unit 6 that performs error processing on the pseudo fault selected by the selection unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-failure generating method and a pseudo-failure method for testing a fault processing of an information processing apparatus.

[0002]

2. Description of the Related Art In this type of pseudo fault generation method, a pseudo fault set by firmware is generated, and a test of a fault processing of an information processing apparatus for the pseudo fault is performed. FIG. 2 shows a schematic configuration of a pseudo fault generating circuit disclosed in Japanese Patent Application Laid-Open No. 7-253906 as a conventional example.

[0003] This pseudo failure generating circuit is composed of a random number generating circuit 1.
01, a pseudo fault occurrence timing determination circuit 102, a pseudo fault occurrence number setting circuit 103, a random number instruction register 104, a random value setting circuit 105, a pseudo fault occurrence counter 106, a pseudo fault occurrence control circuit 107, a pseudo fault code designation register 108, a pseudo fault code It comprises a fault occurrence register 109 and a logic circuit 110.

[0004] A random number generation circuit 101 generates 8-bit random number data 204. The random number data 204 from the random number generation circuit 101 is input to the pseudo failure occurrence timing determination circuit 102, the pseudo failure code designation register 108, and the random number value setting circuit 105, respectively.

A simulated fault occurrence number setting circuit 103 determines, based on a simulated fault occurrence signal 200, whether the simulated fault occurrence number uses a value from the outside or the value of random number data from the random number generation circuit 101. When the value of the random number data is used, "1" is set in the random number instruction register 104. When the value from the outside is used, the pseudo failure occurrence signal 20 is set.
A value of 0 is set in the pseudo failure occurrence counter 106. When the random number instruction signal 201 is “1”, the random number value setting circuit 105 sets the value of the random number data 204 from the random number generation circuit 101 in the pseudo failure occurrence counter 106.

A simulated fault occurrence timing determination circuit 102
The random number data 205 from the random number generation circuit 101 and the pseudo failure occurrence counter signal 207 from the pseudo failure occurrence counter 106 are input, and the pseudo failure occurrence counter signal 2
When 07 is 1 or more, lower-order data obtained by dividing the random number data 205 into two is held. Then, the held data is compared with the higher-order data of the random number data 205 obtained when the data is divided into two, and if they match, the pseudo failure occurrence timing signal 20 is output.
8 is output to the simulated fault occurrence control circuit 107. In this way, the occurrence timing of the pseudo failure is determined.

The simulated fault occurrence control circuit 107 receives the simulated fault occurrence timing signal 208 from the simulated fault occurrence timing determination circuit 102 and the simulated fault occurrence counter signal 207 from the simulated fault occurrence counter 106 and receives the simulated fault occurrence timing signal 208. Is "1" and the pseudo failure occurrence counter signal 207 is "1" or more, the pseudo failure occurrence instruction signal 209 is output to the pseudo failure code designation register 108 and the pseudo failure occurrence instruction register 109, respectively. A pseudo failure occurrence counter subtraction signal 211 indicating that the occurrence counter is decremented by 1 is output to the pseudo failure occurrence counter 106.

When the logic of the pseudo failure generation instruction signal 209 is “1”, the pseudo failure code designation register 108 holds the value of the random number data 206 from the random number generation circuit 101,
The value is sent to the logical line 110 as the pseudo failure code 212. When the logic of the pseudo fault occurrence instruction signal 209 is “1”, the pseudo fault occurrence instruction register 109 sends an enable signal 210 to the logic circuit 110. Logic circuit 1
10, when the logic of the enable signal 210 is “1”,
The pseudo fault code 212 is decoded and ORed with the normal fault display signal 213 to set the fault display register 111.

In the above-described simulated fault occurrence circuit, a simulated fault can be generated a plurality of times, and a test can be performed for a plurality of fault handling operations having a series of relations that occur during the operation of the processing device.

[0010]

In an apparatus for controlling a plurality of devices such as a disk array, after the occurrence of a primary event in which a certain device fails, the following processing is performed while maintaining the state of the primary event. A secondary event may occur during which another device may fail. Therefore, in an apparatus for controlling such a plurality of devices, it is required to perform a test of a failure process for a secondary event after a primary event has occurred.

However, the above-described conventional pseudo-failure generation technique merely generates a primary pseudo-failure a plurality of times, and cannot perform a failure processing test for a secondary event. With the current pseudo failure generation technology, it is not possible to perform a failure processing test on a secondary event after the occurrence of a primary event, so that sufficient evaluation cannot be performed, resulting in quality deterioration. .

An object of the present invention is to solve the above-mentioned problem and to provide a pseudo-failure generating method and a pseudo-failure generating method capable of performing a fault handling test even for a secondary event after a primary event has occurred. is there.

[0013]

In order to achieve the above object, the present invention provides a pseudo-failure generating method for an apparatus for controlling a plurality of devices, the pseudo-failure generating method relating to an error of each of the plurality of devices. Primary pseudo-failure event setting means for setting which of the pseudo-failures is to be generated as the primary pseudo-failure, and which pseudo-failure among the pseudo-failures relating to each error of the plurality of devices is set to 2
A secondary pseudo-failure event setting means for setting whether or not to generate a secondary pseudo-failure; and a primary pseudo-failure set in the primary pseudo-failure event setting means based on the input primary pseudo-failure occurrence timing. Selecting means for selecting the secondary simulated fault set in the secondary simulated fault event setting means based on the selected and inputted secondary simulated fault occurrence timing;
Primary pseudo-failure occurrence timing generation means for generating a primary pseudo-failure occurrence timing for generating a primary pseudo-failure when a predetermined address of the firmware is executed, and outputting the same to the selection means; When the selection means selects a primary pseudo failure relating to an error of a predetermined device, a secondary failure generation timing for generating a secondary pseudo failure is generated, and this is output to the selection means. It is characterized by comprising a fault occurrence timing generating means and an error processing means for generating a primary pseudo fault or a secondary pseudo fault selected by the selecting means and performing an error process relating to the pseudo fault.

In the above case, the primary pseudo failure occurrence timing generation means includes a first register in which an address of the currently executing firmware is held at any time, and a predetermined address among the addresses of the firmware. The second register is compared with the address held in the first register and the address set in the second register. If both addresses match, the logic "1" is output.
First comparing means for outputting a logical "0" when they do not match, a third register for setting the output to a logical "1" when a primary pseudo fault occurs, The output of the first comparing means and the output of the third register are each input, and when the logical product of these inputs is logic "1", 1
First logical operation means for outputting the next pseudo-failure occurrence timing to the selection means, and the secondary pseudo-failure occurrence timing generation means includes a primary pseudo-failure set by the primary pseudo-failure event setting means. A fourth register for designating a predetermined primary pseudo failure among the first and second pseudo failures;
The second pseudo fault is compared with the first pseudo fault specified by the fourth register, and a logic “1” is output when both the pseudo faults match, and a logic “0” is output when the two do not match. A second comparing means, a fifth register whose output is set to be logical "1" when a secondary pseudo fault occurs,
A second logical operation means for receiving the outputs of the second comparing means and the fifth register as inputs, and outputting a secondary simulated fault occurrence timing to the selecting means when the logical product of these inputs is logic "1" May be provided.

The first pseudo failure process of the present invention, in the pseudo failure method performed in the apparatus for controlling according to a preset procedure a plurality of devices, the
Along the processing procedure of dummy failure for each of the error of the plurality of devices at any time is generated as the primary pseudo fault, predetermined dummy failure of said dummy failure
Is generated as a primary pseudo-failure, a predetermined pseudo-failure among the pseudo-failures is generated as a secondary pseudo-failure during the error processing relating to the primary pseudo-failure, and the error processing relating to the secondary pseudo-failure is performed. It is characterized by performing.

According to a second simulated fault occurrence method of the present invention, in the simulated fault occurrence method performed in an apparatus for controlling a plurality of devices, one of the simulated faults among the simulated faults relating to each error of the plurality of devices is set to one It is set whether or not to generate a pseudo-failure, and at the timing when a predetermined address of the firmware address is executed, the primary pseudo-failure is generated and error processing is performed. Out of the pseudo-failures related to each error of the plurality of devices, a predetermined pseudo-failure is set as a primary pseudo-failure, and the pseudo-failure is set as a primary pseudo-failure. The error processing is performed by generating the secondary pseudo failure when the error processing related to the error is executed. To.

In the above case, the timing at which the primary pseudo failure occurs is held at any time with the address of the firmware currently being executed, and the held address is compared with a preset address. In this case, a logic "1" is output if it does not match, and a logic "0" is output if it does not match. When a primary pseudo failure occurs, the output of the register is set to be a logic "1". The logical product of the output and the logical product may be calculated so that the logical product is set to a timing at which the logical product becomes “1”.

Further, the timing at which the secondary pseudo-failure is generated is determined by comparing the executed primary pseudo-failure with a preset one.
The second pseudo fault is compared with the next pseudo fault, and when both pseudo faults match, the logic "1" is output, and when they do not match, the logic "0" is output. May be ANDed with the output of a register that is set to be logical "1", and the timing may be such that the logical AND becomes logical "1".

(Operation) In the present invention as described above, a first pseudo fault is generated to execute error processing, and a second pseudo fault is generated during the error processing to execute error processing. So we couldn't
A fault handling test for a secondary event after the occurrence of the next event can be performed.

Further, in the present invention, the occurrence of the primary pseudo failure is performed at a timing when a predetermined address of the firmware address is executed, and the occurrence of the secondary pseudo failure is determined by a primary error relating to a predetermined device error. Because it is performed at the timing when the pseudo failure is executed,
Both the primary pseudo-failure and the secondary pseudo-failure can occur at any timing.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a simulated fault occurrence system according to the present invention. This simulated fault occurrence method tests simulated fault processing in each device of a device for controlling a plurality of devices such as a disk array, and has a configuration including an error display register 1, a simulated fault event setting register 2
a, 2b, a primary simulated fault occurrence timing generator 3, a secondary simulated fault occurrence timing generator 4, a selector 5, and an error processor 6.

The error display register 1 receives an error signal a indicating the occurrence of a normal error and the outputs of the simulated fault event setting registers 2a and 2b via a selector 5, respectively. Stores the value of the input. The error processing unit 6 performs a simulated fault process for the corresponding device based on the value stored in the error display register 1.

The simulated fault event setting register 2a specifies which of the primary simulated fault processing of each device executed by the error processing unit 6 is to be executed. In the pseudo-failure event setting register 2a, a value corresponding to an arbitrary primary pseudo-failure process is set in advance by the FW, and the set value is output to the error display register 1 via the selector 5.

The simulated fault event setting register 2b specifies which of the secondary simulated fault processes of each device executed by the error processing unit 6 is to be executed. In the pseudo-failure event setting register 2a, a value corresponding to an arbitrary secondary pseudo-failure process is set in advance by the FW, and the set value is output to the error display register 1 via the selector 5.

The selector 5 selects the output of the simulated fault event setting register 2a based on the primary fault occurrence timing generated by the primary simulated fault occurrence timing generator 3, and selects the secondary simulated fault occurrence timing generator. 4. Based on the secondary fault occurrence timing generated in step 4, the output of the pseudo fault event setting register 2b is selected. If no fault occurrence timing has been generated, the input related to the normal error signal a is selected. I do.

The primary simulated fault occurrence timing generation unit 3
This determines which of the FW addresses will cause a primary pseudo-failure when executed.
It comprises a FW execution address display register 31, a pseudo failure occurrence timing register 32, a comparison unit 33, a pseudo failure mode register 34, and a logical operation unit 35.

The FW execution address display register 31 holds the address of the currently executed FW as needed. The simulated fault occurrence timing register 32 designates a timing at which a first simulated fault occurs, and a predetermined address among the addresses of the FW is set in advance by the FW when the simulated fault mode is executed. The comparing unit 33 compares the address held in the FW execution address display register 31 with the address specified by the pseudo failure occurrence timing register 32, and when both addresses match, logic "1" is determined. Outputs logic "0". The pseudo failure mode register 34 is a two-bit register, and the logic “1” is set by the FW when the pseudo failure mode is executed, and the logic “0” is set when the pseudo failure mode is not set. The logical operation unit 35 receives the outputs of the comparison unit 33 and the pseudo failure mode register 34 as inputs, takes the logical product of these inputs, and determines the primary pseudo failure occurrence timing when the logical product result becomes “1”. Output to selector 5.

The secondary simulated fault occurrence timing generation section 4
The primary pseudo-failure processing is executed to determine when the secondary pseudo-failure is to be generated. The configuration includes a pseudo-failure occurrence error display register 41, a comparing unit 42, a pseudo-failure mode register 43, and a logical operation unit. 44.

The pseudo failure occurrence error display register 41
This specifies the timing at which the secondary pseudo failure occurs, and a predetermined value among the values stored in the error display register 1 is set in advance by the FW when the pseudo failure mode is executed. The comparing unit 42 compares the value stored in the error display register 1 with the value specified in the pseudo failure occurrence error display register 41, and when these values match, the logic “1” is determined. Outputs logic "0".
The pseudo-failure mode register 43 is a 2-bit register. The FW sets the logic “1” when the pseudo-failure mode is executed, and sets the logic “0” when the pseudo-failure mode is not set. The logical operation unit 44 receives the outputs of the comparison unit 42 and the pseudo-failure mode register 43 as inputs, calculates the logical product of these inputs, and determines the secondary pseudo-failure occurrence timing when the logical product result is “1”. Output to selector 5.

Next, the operation of the pseudo failure generation method will be described in detail.

Normally, since the logic "0" is set in the pseudo failure mode register 34, the output of the logic operation unit 35 is "0", and the output of the logic operation unit 44 is also "0".
Becomes The selector 5 selects the error signal a, and the value of the error signal a is stored in the error display register 1. In this case, the error processing unit 6 does not perform error processing until an original error occurs.

When an error processing test is performed by generating a pseudo-failure, first, the pseudo-failure mode register 3 is set by the FW.
The logic “1” is set in the registers 4 and 43, and which FW
It is set which primary pseudo fault of which content is to be generated when the address is executed, and which secondary pseudo fault of which content is to be generated when which primary pseudo fault is generated. In this setting, a set value indicating what kind of primary simulated fault occurs in the simulated fault event setting register 2a, a set value indicating what kind of secondary simulated fault to generate in the simulated fault event setting register 2b, An address of the FW which is a timing at which a primary pseudo failure occurs is stored in the pseudo failure occurrence timing register 32.
In the pseudo failure occurrence error display register 41, a setting value for which primary pseudo failure occurs when a secondary pseudo failure occurs is set by the FW. After all these settings are completed, normal processing by the FW is executed.

When the normal processing by the FW is executed, the address of the FW currently being executed is held in the FW execution address display register 31 as needed. Then, the comparison unit 33 compares the address held in the FW execution address display register 31 with the address set in the pseudo failure occurrence timing register 32. The comparator 33 outputs a logical “1” when both addresses match, and outputs a logical “0” when they do not match.

The address held in the FW execution address display register 31 and the pseudo failure occurrence timing register 32
, The output of the comparison unit 33 becomes logic “1”. In the logical operation unit 35, the comparison unit 3
3 (logical "1") and the pseudo failure mode register 34
(Logical "1") is obtained, and as a result, logical "1" is output.

When the output of the logical operation unit 35 becomes logical "1", the output of the pseudo failure event setting register 2a is selected by the selector 5, and the value of the pseudo failure event setting register 2a is stored in the error display register 1. . If the address held in the FW execution address display register 31 does not match the address set in the simulated fault occurrence timing register 32, the output of the comparison unit 33 is logic "0".
, And the output of the logic operation unit 35 also becomes logic “0”. When the output of the logical operation unit 35 is logic "0", the selection of the output of the pseudo failure event setting register 2a in the selector 5 as described above is not performed, so that the primary pseudo failure does not occur.

When the value of the simulated fault event setting register 2a is stored in the error display register 1, the simulated fault processing of the corresponding device is performed by the error processing unit 6 based on the value stored in the error display register 1. At the same time, the comparison unit 42 compares the value stored in the error display register 1 with the value set in the pseudo failure occurrence error display register 41. The comparison unit 42 outputs logic “1” when the values match, and outputs logic “0” when the values do not match.

When the value stored in the error display register 1 matches the value set in the pseudo failure occurrence error display register 41, the output of the comparing section 42 becomes logic "1". In the logical operation unit 44, the logical product of the output (logic “1”) of the comparison unit 42 and the output (logic “1”) of the pseudo failure mode register 43 is obtained, and as a result, the logical “1” is output. . When the output of the logical operation unit 44 becomes logic “1”, the output of the pseudo failure event setting register 2 b is selected by the selector 5, and the value of the pseudo failure event setting register 2 b is stored in the error display register 1. Then, based on the value stored in the error display register 1, the error processing section 6 performs the secondary pseudo failure processing of the corresponding device.

If the value stored in the error display register 1 does not match the value set in the pseudo failure occurrence error display register 41, the output of the comparing section 42 becomes logic "0", The output of the operation unit 44 is also logic “0”.
Becomes When the output of the logic operation unit 44 is logic “0”,
Since the output of the pseudo failure event setting register 2b is not selected by the selector 5 as described above, the secondary pseudo failure does not occur.

Hereinafter, the operation of the above-described secondary pseudo failure occurrence processing will be described in detail with specific addresses and set values.

Here, devices to be subjected to the pseudo-failure occurrence processing are assumed to be circuits A to G, and a circuit C is regarded as a primary pseudo-failure.
, An error of the circuit G is generated as a secondary pseudo fault. The error display register 1 in this case is 8
Bit 7: Representative bit Bit 6: Error in circuit A Bit 5: Error in circuit B Bit 4: Error in circuit C Bit 3: Error in circuit D Bit 2: Error in circuit E Bit 1: Circuit F error bit 0: Circuit G error. Here, the address of the FW is 16
00A0 (hex) 00A2 (hex) 00A4 (hex) 00A8 (hex) 00B0 (hex) 00B2 (hex)..., And the FW address is "00".
A case will be described in which an error of the circuit C occurs as a primary pseudo-failure at the time of “B0 (hex)”, and an error of the circuit G occurs as a secondary pseudo-failure.

First, as an initial setting, a pseudo failure occurrence timing register 32: 00B0 (he
x) Pseudo failure occurrence occurrence error display register 43:10 (he
x) Pseudo failure setting register 2a: 10 (hex) Pseudo failure setting register 2b: 01 (hex) Pseudo failure mode register 34: 1 (bin) Pseudo failure mode register 43: 1 (bin) is set.

When the normal processing by the FW is performed to execute “00B0 (hex)” of the address of the FW, and “00B0 (hex)” is held in the FW execution address display register 31, the comparison unit 33 “00B0 (hex)” held in the FW execution address display register 31 is compared with “00B0 (hex)” set in the pseudo failure occurrence timing register 32. Since the values of these registers match, the output of the comparison unit 33 becomes logic "1". In the logical operation unit 35, the output (logic “1”) of the comparison unit 33 and “1” of the pseudo failure mode register 34
(Bin) ", and a logical" 1 "is output from the logical operation unit 35 to the selector 5 as a result.

When the output of the logical operation unit 35 becomes logic "1", "10 (hex)" of the simulated fault event setting register 2a is selected by the selector 5, and the error display register 1
Is stored as "10 (hex)". Here, the error display register 1 has 8 bits, and “10 (hex)” means that a pseudo failure relating to an error of the circuit C is generated.

In the error display register 1, "10 (he
When (x) is stored, the error processing unit 6 performs the primary simulated fault processing relating to the error of the circuit C, and the comparing unit 42 stores “10 (hex)” stored in the error display register 1. Is compared with “10 (hex)” set in the pseudo failure occurrence error display register 41. Since the values of these registers match, the output of the comparison unit 42 becomes logic "1". In the logical operation unit 44, the logical product of the output (logic “1”) of the comparison unit 42 and “1 (bin)” of the pseudo failure mode register 43 is obtained.
As a result, a logical “1” is output from the logical operation unit 44 to the selector 5.

When the output of the logical operation unit 44 becomes logic "1", "01 (hex)" of the pseudo failure event setting register 2b is selected by the selector 5, and the error display register 1
Is stored as “01 (hex)”. Here, the error display register 1 has 8 bits, and “01 (hex)” means that a pseudo failure relating to an error of the circuit G is generated.

In the error display register 1, "01 (he
x) ”is stored, the error processing unit 6 performs the second pseudo failure processing relating to the error of the circuit G. As a result, the secondary pseudo-failure processing relating to the error of the circuit G is performed during the primary pseudo-failure processing relating to the error of the circuit C.

[0048]

According to the present invention configured as described above, a fault handling test for a secondary event after the occurrence of a primary event can be performed, so that the conventional test could not be performed. In addition, it is possible to easily perform a pseudo failure test on a rare secondary event on an actual machine.

Further, according to the present invention, since both the primary pseudo-failure and the secondary pseudo-failure can occur at any timing, a pseudo-failure test is performed in a manner close to the actual occurrence timing. The quality of the device to be tested can be easily increased at an early stage. In addition, in reproduction tests such as obstacles,
A pseudo fault equivalent to the fault occurrence condition can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo failure generation system according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a pseudo fault generating circuit disclosed in Japanese Patent Application Laid-Open No. 7-253906.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Error display register 2a, 2b Pseudo fault event setting means 3 Primary pseudo fault occurrence timing generator 4 Secondary pseudo fault occurrence timing generator 5 Selector 6 Error processing unit 31 FW execution address display register 32 Pseudo fault occurrence timing register 33, 42 comparison unit 34, 43 pseudo failure mode register 35, 44 logical operation unit 41 pseudo failure occurrence error display register

Claims (6)

(57) [Claims] In a pseudo failure generation method for an apparatus that controls a plurality of devices, it is set which of a plurality of pseudo failures relating to errors of the devices is to be generated as a primary pseudo failure. Secondary pseudo-failure event setting means; secondary pseudo-failure event setting means for setting which of the pseudo-failures relating to each error of the plurality of devices is to be generated as a secondary pseudo-failure; The primary pseudo failure set in the primary pseudo failure event setting means is selected based on the secondary pseudo failure occurrence timing, and the secondary pseudo failure event setting means is selected based on the input secondary pseudo failure occurrence timing. 2 set to
Selecting means for selecting a next pseudo fault; generating a first pseudo fault occurrence timing for generating a first pseudo fault when a predetermined address of the firmware address is executed, and outputting this to the selecting means A primary pseudo failure occurrence timing generating means, and a secondary failure occurrence timing for generating a secondary pseudo failure when the primary pseudo failure related to a predetermined device error is selected by the selecting means, Secondary failure occurrence timing generation means for outputting the first pseudo failure or the second pseudo failure selected by the selection means, and performing error processing relating to the pseudo failure. And a pseudo failure generating method. 2. The pseudo failure generation method according to claim 1, wherein the first pseudo failure generation timing generation means includes: a first register in which an address of a currently executing firmware is held as needed; and an address of the firmware. Comparing a second register in which a predetermined address is set in advance with an address held in the first register and an address set in the second register, and when both addresses match with each other A first comparing means for outputting a logic "1" when the values do not coincide with each other, and a third means for setting an output to a logic "1" when a primary pseudo failure occurs. And the output of the first comparing means and the output of the third register, respectively, and when the logical product of these inputs is logical "1", the primary pseudo failure occurrence timing is selected. First logical operation means for outputting to the means, and a secondary pseudo failure occurrence timing generating means, wherein a predetermined primary pseudo failure of the primary pseudo failure set by the primary pseudo failure event setting means is provided. A fourth register for designating a fault, a primary pseudo fault selected by the selection means and a primary pseudo fault specified by the fourth register are compared, and if both pseudo faults match, A second comparing means for outputting a logical "1" and a logical "0" when they do not match, and a fifth for setting the output to be a logical "1" when a secondary pseudo fault occurs. A second register which outputs the output of the second pseudo failure to the selection means when the logical product of these inputs is logic "1"; Pseudo operation characterized by having logical operation means Failure system. 3. A processing device in which a plurality of devices are set in advance by a predetermined processing method.
In the pseudo-failure method performed in the apparatus for controlling according to the order, along the processing procedure to generate a pseudo-fault for each of the error of the plurality of devices as the primary dummy failure at any time, of said dummy failure Predetermined pseudo
When a failure occurs as a primary pseudo failure, during the error processing relating to the primary pseudo failure, a predetermined pseudo failure among the pseudo failures is generated as a secondary pseudo failure, and the error processing relating to the secondary pseudo failure is performed. Performing a pseudo failure. 4. A pseudo-failure generating method performed in an apparatus controlling a plurality of devices, wherein a pseudo-failure among pseudo-failures relating to errors of the plurality of devices is set as a primary pseudo-failure. And performing error processing by generating the primary pseudo-failure at a timing at which a predetermined address of the firmware address is executed. Setting whether to generate as a fault, when a predetermined pseudo fault is set as a primary pseudo fault from among the pseudo faults related to each error of the plurality of devices, and when error processing related to the primary pseudo fault is executed, A pseudo-failure generating method, wherein the secondary pseudo-failure is generated and error processing is performed. 5. The pseudo-failure generating method according to claim 4, wherein the timing at which the primary pseudo-failure is generated is held at an address of a currently executing firmware as needed.
The stored address is compared with a preset address, and when both addresses match, logic "1" is output, and when they do not match, logic "0" is output. A pseudo-failure generating method, which takes the logical product of the register and the output of a register set so that the output becomes logical "1" when generating the logical value, and sets the timing at which the logical product becomes logical "1". . 6. The pseudo-failure generating method according to claim 4, wherein a timing of generating the secondary pseudo-failure is determined by comparing the executed primary pseudo-failure with a preset primary pseudo-failure. Logic "1" when the pseudo failure matches
Is output as a logical "0" if they do not match, and the logical product of the output and the output of a register set to output a logical "1" when a secondary pseudo fault occurs is calculated. The pseudo failure generating method is characterized in that the timing is such that the logical product becomes logical "1".