JP2003194895A - Pattern generating device and method, and semiconductor integrated circuit test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the pattern generating device and method capable of easily generating a pattern such as an address complement pattern without a limit in a maximum value of a line address and a row address, and to provide a semiconductor integrated circuit test device. <P>SOLUTION: A line address operating circuit 30a performs the operation in accordance with the line address operation command S31, and outputs an operation result S41. A line maximum value register 31a stores the maximum value of the line address. A subtracting circuit 32a outputs a subtraction result S61 obtained by subtracting the operation result S41 from the maximum value stored in the line maximum value register 31a, and selects one of the operation result S41 and the subtraction result S61 on the basis of a selecting signal S31. A constitution composed of a row address operating circuit 30b, a line maximum value register 31b, a subtracting circuit 32b and a selecting circuit 33b are also similarly operated. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator and a semiconductor integrated circuit tester, and more particularly to a pattern generator and method for generating an address pattern to be given to a device under test such as a semiconductor memory, and the pattern generator. The present invention relates to a semiconductor integrated circuit test device.

[0002]

2. Description of the Related Art To test an object to be tested such as a semiconductor memory by using a semiconductor integrated circuit tester, an address pattern and a test pattern are given to the semiconductor memory, and these patterns are obtained when the pattern is given to the semiconductor memory. Then, the pass / fail judgment is made by comparing the received signal with a predetermined expected value, and the quality of the semiconductor memory is judged based on the judgment result. Therefore, the semiconductor integrated circuit test apparatus is provided with a pattern generator such as a pattern generator that generates an address signal to be supplied to the semiconductor memory and a pattern generator that generates a test pattern.

As one of the tests for semiconductor memories,
There is a test for examining the interference between adjacent memory cells in a semiconductor memory, and the presence or absence of interference between address lines, data lines, and between address lines and data lines. This test is performed using various patterns, and one of the patterns (address patterns) is a pattern called an address complement pattern.

This address complement pattern is
The row address is incremented from the state where the row address and the column address are both at the minimum value, and when the row address exceeds the maximum value, the row address is returned to the minimum value and the column address is incremented to perform such a pattern change. , The first pattern that repeats until the column address becomes maximum, and the row address is decremented from the state where the row address and the column address both have the maximum value, and when the row address exceeds the minimum value, the row address becomes the maximum value. This is a pattern in which a second pattern in which the column address is decremented while the column address is returned and such a pattern change is repeated until both the row and column addresses are minimized appears alternately.

FIG. 5 is a diagram for explaining an example of an operation at the time of testing a semiconductor memory using an address complement pattern. Here, the operation at the time of testing the memory cells A0 to A15 in which the maximum values of the row address and the column address are “3” will be described. When the test is performed using the address complement pattern, the test of the memory cell A0 in which both the row address and the column address are the minimum value "0" is performed. Next, the memory cell A15 in which both the row address and the column address have the maximum value “3” is tested.

Next, the memory cell A1 having the row address "1" and the column address "0" is tested, and the memory cell A14 having the row address "2" and the column address "3" is tested. Perform the test. Similarly, the memory cell A
The test is conducted in the order of 2, A13, A3, A12, ....
Next, a conventional pattern generator that generates the above address complement patterns will be described.

FIG. 6 is a block diagram showing the structure of a conventional pattern generating device for generating an address complement pattern. As shown in FIG. 6, the conventional pattern generation device 50 is configured to include a row address operation circuit 51, a column address operation circuit 52, an exclusive OR circuit 53, and an exclusive OR circuit 54, and is externally connected. Row address operation instruction C51, column address operation instruction C52, and inverted signal D5
A signal C50 including 1, D52 is input, and this signal C5
The calculation is performed according to 0 and the address complement pattern P50 is output.

The row address operation circuit 51 performs an operation in accordance with the row address operation instruction C51 included in the signal C50, and the row address C6 of the semiconductor memory to be tested.
1 is generated. The column address calculation circuit 52 outputs the signal C50.
Column address calculation instruction C52 included in the column address C6 of the semiconductor memory to be tested.
Generates 2. The exclusive OR circuit 53 includes a row address C61 generated by the row address operation circuit 51 and a signal C50.
The exclusive OR operation is performed with the inversion signal D51 included in the above, and the operation result P51 is output.

The exclusive OR circuit 54 performs an exclusive OR operation on the column address C62 generated by the column address operation circuit 52 and the inverted signal D52 included in the signal C50,
The calculation result P52 is output. Exclusive OR circuit 53
The calculation result P51 and the calculation result P52 of the exclusive OR circuit 54 become the address complement pattern P50. Here, since the maximum values of the row address and the column address are both “3” and the range in which 2 bits can be counted is considered, the exclusive OR circuits 53 and 54 are provided.
Performs 2-bit exclusive OR operation.

FIG. 7 is a timing chart showing the signal waveform of each part of the conventional pattern generator 50 shown in FIG. First, the row address operation circuit 51 outputs "0" as the row address C61 according to the row address operation instruction C51 included in the signal C50, and the column address operation circuit 52 outputs the column address according to the column address operation instruction C52 included in the signal C50. "0" is output as the address C62. Between times t50 and t51, the inversion signals D51 and D52 included in the signal C50 are both "0", so the exclusive OR circuits 53 and 54 both output "0" as the operation results P61 and P62.

Next, from time t51 to t52, the signal C
The inversion signals D51 and D52 included in 50 both become "1", and the exclusive OR circuits 53 and 54 calculate the operation result P61,
Both outputs "3" as P62. At time t52,
An increment instruction is input as the row address operation instruction C51, and the row address operation circuit 51 causes the row address operation circuit C61.
"1" is output as. In contrast, this time t52
Then, since the column address operation instruction C52 is not input,
Column address C6 output from the column address calculation circuit 52
2 remains "0".

Between times t52 and t53, since the inversion signals D51 and D52 included in the signal C50 are both "0", the exclusive OR circuit 53 outputs "1" as the operation result P61, and the exclusive OR circuit 53 The OR circuit 53 calculates the calculation result P6.
"1" is output as 1, and the exclusive OR circuit 54 outputs "0" as the operation result P62. Next, time t53
Between t54 and t54, the inverted signals D51 and D52 are both “1”.
The exclusive OR circuit 53 outputs "2" as the operation result P61, and the exclusive OR circuit 54 outputs the operation result P6.
"3" is output as 2. The above operation is repeated to output the address complement pattern P60.

The conventional pattern generator 50 described above
Then, in order to generate the address complement pattern P60, the row address operation instruction C51 for incrementing the row address, the column address operation instruction C52 for incrementing the column address, and the inversion signals D51, D.
Since it is only necessary to describe the combination of 52 in the test program, the test program can be created easily.

[0014]

By the way, in the above-mentioned conventional test pattern generator 50, the first pattern included in the above-mentioned address complement pattern is generated using the row address operation circuit 51 and the column address operation circuit 52. is doing. On the other hand, in the second pattern, the row address C61 output from the row address operation circuit 51 and the column address C62 output from the column address operation circuit 52 are
It is generated by inverting each of the exclusive OR circuits 53 and 54.

Therefore, it is effective only when the maximum value of the row address and the column address is 2 ⁿ -1 (n is a natural number). In other cases, it is impossible to generate the address complement pattern. A row address operation instruction C51 for incrementing a row address to be described in the test program even if it can be generated, a column address operation instruction C52 for incrementing a column address,
There is a problem that the combination of the inverted signals D51 and D52 becomes extremely complicated.

Since the address of the semiconductor memory is determined by the number of address signal lines, the maximum values of the row address and the column address of the packaged semiconductor memory cannot be other than 2 ⁿ -1. However, at the time when a semiconductor memory circuit is formed on a semiconductor wafer, redundant cells for relieving defective memory cells are formed in addition to normal memory cells. In this unpackaged semiconductor memory test, it is necessary to test a redundant cell together with a normal memory cell, so the maximum row address and column address may be other than 2 ⁿ −1.
The conventional pattern generator cannot be used for this test, or a large amount of labor is required to generate a test program for use.

The present invention has been made in view of the above circumstances, and there is no limitation on the maximum values of the row address and the column address.
An object of the present invention is to provide a pattern generation device and method and a semiconductor integrated circuit test device that can easily generate a pattern such as an address complement pattern.

[0018]

In order to solve the above problems, the pattern generating apparatus of the present invention performs a calculation according to a control signal (S3) input from the outside to generate a specific pattern (S6). An arithmetic unit (30a, which is a generator (12)) that performs an arithmetic operation according to the control signal (S3) and generates a first pattern (S41, S42).
30b), storage units (31a, 31b) for storing the maximum value of the generated pattern (S6), and the storage unit (31).
a, 31b) a second pattern (S6) obtained by subtracting the first pattern (S41, S42) generated by the arithmetic unit (30a, 30b) from the maximum value of the pattern stored in
1, a subtraction unit (32a, 32b) for generating S62),
Based on the control signal (S3), the arithmetic unit (30
a, 30b) the first pattern (S41, S4)
2) and a selection unit (33a, 33b) that selects and outputs one of the second patterns (S61, S62) generated by the subtraction unit (32a, 32b). According to the present invention, the calculation unit generates the first pattern, the subtraction unit generates the second pattern by subtracting the first pattern from the maximum value of the addresses stored in the storage unit, and the selection unit generates the first pattern. Since either one of the second pattern and the second pattern is selected, it is possible to easily generate a pattern such as an address complement pattern without limiting the maximum value. Further, the pattern generator of the present invention is characterized in that the storage unit (31a, 31b) stores an arbitrary natural number as the maximum value of the pattern. Further, the pattern generating apparatus of the present invention includes a plurality of the arithmetic units, the storage units, the subtracting units, and the selecting unit, and the pattern generating device (12) generates a pattern including a plurality of types of patterns as a set. It is characterized by that. Further, the pattern generating apparatus of the present invention is characterized in that each of the storage units individually stores an arbitrary natural number as the maximum value of the pattern. Further, the pattern generator of the present invention is characterized in that the pattern is a pattern given as an address to an object to be tested. In order to solve the above problems, a semiconductor integrated circuit test apparatus of the present invention outputs the pattern generator (12) according to any one of the above, and a control signal (S3) given to the pattern generator (12). It is characterized by including a control unit (10, 11). In order to solve the above-mentioned problems, the pattern generation method of the present invention uses a control signal (S3).
A first pattern generation step of performing a calculation according to the control signal (S3) and generating a first pattern (S41, S42), which is a pattern generating method for generating a specific pattern (S6) according to From the maximum value of the generated pattern (S6), the first pattern (S41, S
42), a second pattern generation step of generating a second pattern (S61, S62), and the control signal (S
3) based on the first pattern (S41, S42)
And a selection step of selecting and outputting any one of the second patterns (S61, S62).

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A pattern generating apparatus and method and a semiconductor integrated circuit testing apparatus according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention including a pattern generating apparatus according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor integrated circuit test apparatus according to an embodiment of the present invention includes a sequence controller 10, an instruction memory 11,
Address pattern generator 1 as a pattern generator
2, including a data pattern generator 13, a memory control pattern generator 14, a waveform shaper 15, and a comparator 16, for example, while setting test conditions according to a test program created by a computer system such as a workstation. The memory under test 20 is tested.

The sequence controller 10 outputs the program counter signal S1 in accordance with the sequence control instruction stored in the instruction memory 11. The instruction memory 11 outputs the sequence control command stored at the address designated by the program counter signal S1 output from the sequence controller 10 as the sequence control command signal S2, and the address pattern generator 12 and the data pattern generator 13 are output. , And the memory control pattern generator 14 respectively, an address pattern generation command signal S3 (control signal), a data pattern generation command signal S4, and a memory control pattern generation command signal S5.
Are output respectively. The sequence controller 10 and the instruction memory 11 correspond to the control unit according to the present invention.

The address pattern generator 12 outputs an address pattern S6 to be given to the memory under test 20 according to the contents of the address pattern generation command signal S3 output from the instruction memory 11. The data pattern generator 13 outputs a data pattern S7 to be given to the memory under test 20 according to the content of the data pattern generation command signal S4 output from the instruction memory 11. Further, the memory control pattern generator 14 controls the operation of the memory under test 20 such as a read signal and a write signal given to the memory under test 20 according to the content of the memory control pattern generation command signal S5 output from the instruction memory 11. Control pattern S8 including control signal
Is output.

The waveform shaper 15 outputs the address pattern S6 output from the address pattern generator 12, the data pattern S7 output from the data pattern generator 13, and the waveform pattern setting described in the test program. A required pattern is selected from the control pattern S8 output from the memory control pattern generator 14, waveform shaping is performed, a test signal S9 is output to the memory under test 20, and an expected value is shown to the comparator 16. The expected signal S10 is output.

The comparator 16 compares the contents of the output signal S11 obtained by applying the test signal S9 to the memory under test 20 with the expected signal S10 output from the waveform shaping section 10, and shows the comparison result. Output a signal. This comparator 1
A control unit (not shown) determines pass / fail based on the comparison result of No. 6, and determines whether the memory under test 20 is defective or not.

The outline of the configuration and the operation of the semiconductor integrated circuit according to the embodiment of the present invention has been briefly described above. Next, the address pattern generator 12 as the pattern generator according to the embodiment of the present invention will be described. .
FIG. 2 is a block diagram showing the configuration of the address pattern generator 12 as the pattern generator according to the embodiment of the present invention. As shown in FIG. 2, the address pattern generator 12 includes a row address operation circuit 30a and a subtraction circuit 31.
a, a row maximum value register 32a, a selection circuit 33a, a column address operation circuit 30b, a subtraction circuit 31b, a column maximum value register 32b, and a selection circuit 33b.

Row address operation circuit 30a and subtraction circuit 31
The configuration including a, the row maximum value register 32a, and the selection circuit 33a is for generating a row address given to the memory under test 20, and includes a column address operation circuit 30b, a subtraction circuit 31b, a column maximum value register 32b, The configuration including the selection circuit 33b is for generating a row address to be given to the memory under test 20.

The row address operation circuit 30a performs an operation in accordance with the row address operation instruction S31 included in the address pattern generation instruction signal S3 output from the instruction memory 11 in FIG. 1 to generate the operation result S41 as the first pattern. To do. The row maximum value register 31a stores the maximum value of the row address of the memory under test 20. still,
The maximum value of the row address stored in the row maximum value register 31a is set by a computer system (not shown). The maximum value that can be stored in the row maximum value register 31a is an arbitrary natural number.

The subtraction circuit 32a includes a row maximum value register 31.
Signal S5 indicating the maximum value of the row address stored in a
The subtraction result S61 as the second pattern is generated by subtracting the operation result S41 as the first pattern generated by the row address operation circuit 30a from 1. Selection circuit 3
3a is a calculation result S41 as the first pattern generated by the row address calculation circuit 30a in accordance with the selection signal D31 included in the address pattern generation command signal S3 output from the instruction memory 11 in FIG.
And one of the subtraction results S61 as the second pattern generated by the subtraction circuit 32a is selected and output as a pattern S71.

The column address operation circuit 30b performs an operation in accordance with the column address operation instruction S32 included in the address pattern generation instruction signal S3 output from the instruction memory 11 in FIG. 1, and produces the operation result S42 as the first pattern. To do. The column maximum value register 31b stores the maximum value of the column address of the memory under test 20. still,
The maximum value of the column address stored in the column maximum value register 31b is set by a computer system (not shown). The maximum value that can be stored in the column maximum value register 31b is an arbitrary natural number.

The subtraction circuit 32b includes a column maximum value register 31.
signal S5 indicating the maximum value of the column address stored in b
The subtraction result S62 as the second pattern is generated by subtracting the operation result S42 as the first pattern generated by the column address operation circuit 30b from 2. Selection circuit 3
3b is a calculation result S42 as the first pattern generated by the column address calculation circuit 30a in accordance with the selection signal D32 included in the address pattern generation command signal S3 output from the instruction memory 11 in FIG.
And one of the subtraction results S62 as the second pattern generated by the subtraction circuit 32b is selected and output as a pattern S72. The pattern S72 from the selection circuit 33a and the pattern S72 from the selection circuit 33b are output as the address pattern S6. The address pattern S6 is an address complement pattern.

Next, the operation of the address pattern generator 12 having the above configuration will be described. FIG. 3 shows the address pattern S output from the address pattern generator 12.
6 is a diagram for explaining an example of an operation at the time of testing the semiconductor memory 20 using 6. Incidentally, here, the semiconductor memory 2
The maximum value of the row address and the column address of 0 is "5", that is, the memory cell A0 other than 2 ⁿ -1 (n is a natural number)
The operation during the test for A35 will be described. Figure 4
FIG. 3 is a timing chart showing signal waveforms of respective parts of the address pattern generator 12 shown in FIG. Before starting the operation of the address pattern generator 12, a computer system (not shown) stores "5" as the maximum value in the row maximum value register 31a and the column maximum value register 31b in advance.

When the address pattern generation command signal S3 is output from the instruction memory 11, the row address calculation circuit 30a outputs "0" as the calculation result S41 in accordance with the row address calculation command S31 included in the address pattern generation command signal S3. Then, according to the column address operation command S32 included in the address pattern generation command signal S3, the column address operation circuit 30b outputs "0" as the operation result S42.

Further, the subtraction circuit 32a outputs the signal S5 indicating the maximum value "5" stored in the row maximum value register 31a.
The subtraction result S whose value is "5" obtained by subtracting the operation result S41 generated by the row address operation circuit 30a from 1
61 is output. Similarly, the subtraction circuit 32b subtracts the operation result S42 generated by the column address operation circuit 30b from the signal S52 indicating the maximum value "5" stored in the column maximum value register 31b, and the value is "5". A certain subtraction result S62 is output.

Between times t10 and t11, the selection signals D31 and D3 included in the address pattern generation command signal S3 are included.
Since both 2 are "0", the selection circuit 33a selects the calculation result S41 output from the row address calculation circuit 30a and outputs the pattern S71 having a value "0", and the selection circuit 33b selects the column The operation result S42 output from the address operation circuit 30b is selected and the pattern S72 having a value of "0" is output. When these patterns S71 and S72 are output as the address pattern S6, the test of the memory cell A0 in which both the row address and the column address shown in FIG. 3 are the minimum value "0" is performed.

Next, between times t11 and t12, the selection signal D3 included in the address pattern generation command signal S3 is included.
1 and D32 are both "1", and the selection circuit 33a selects the subtraction result S61 output from the subtraction circuit 32a and outputs the pattern S71 having a value "5".
b selects the subtraction result S62 output from the subtraction circuit 32b and outputs a pattern S72 having a value of "5". These patterns S71 and S72 are the address patterns S6.
Is output, the memory cell A35 whose row address and column address shown in FIG. 3 are both the minimum value "5" is tested.

At time t12, the row address operation instruction S3
The increment instruction is input as 1, and the row address operation circuit 30a outputs "1" as the operation result S41. On the other hand, at this time t52, since the column address operation instruction C32 is not input, the column address operation circuit 3
The calculation result S42 output from 0b remains "0".

At this time, the subtraction circuit 32a subtracts the operation result S41 generated by the row address operation circuit 30a from the signal S51 indicating the maximum value "5" stored in the row maximum value register 31a. The subtraction result S61 of "4" is output. Here, the column address calculation circuit 3
Since the calculation result S42 output from 0b remains "0", the subtraction circuit 32b generates by the column address calculation circuit 30b from the signal S52 indicating the maximum value "5" stored in the column maximum value register 31b. Calculated result S4
A subtraction result S62 whose value is "5" obtained by subtracting 2 is output.

Between times t12 and t13, the selection signals S31 and D3 included in the address pattern generation command signal S3 are included.
Since both 2 are "0", the selection circuit 33a selects the calculation result S41 output from the row address calculation circuit 30a and outputs the pattern S71 having a value "1", and the selection circuit 33b selects the column The operation result S42 output from the address operation circuit 30b is selected and the pattern S72 having a value of "0" is output. When these patterns S71 and S72 are output as the address pattern S6, the memory cell A1 having the row address "1" and the column address "0" shown in FIG. 3 is tested.

Next, between times t13 and t14, the selection signal D3 included in the address pattern generation command signal S3 is included.
1 and D32 are both "1", the selection circuit 33a selects the subtraction result S61 output from the subtraction circuit 32a, outputs the pattern S71 having a value "4", and the selection circuit 33a.
b selects the subtraction result S62 output from the subtraction circuit 32b and outputs a pattern S72 having a value of "5". These patterns S71 and S72 are the address patterns S6.
Is output as, the row address shown in FIG. 3 is "4".
And the test of the memory cell A34 whose column address is "5" is performed. The above operation is repeated to perform the address pattern S6 as the address complement pattern.
Is output.

The address pattern generator 12 described above
Then, in order to generate the address pattern S6 as the address complement pattern, the row address operation instruction S31 for incrementing the operation result S41 of the row address operation circuit 30a and the column address operation for incrementing the operation result S42 of the column address operation circuit 30b. Since it is only necessary to describe the combination of the instruction S32 and the selection signals D31 and D32 in the test program, it is easy to create the test program.

Although the semiconductor integrated circuit testing device and method according to one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and can be freely modified within the scope of the present invention. . For example, in the above embodiment,
The case of generating a pattern for designating a row address and a column address has been described as an example, but it is also applicable to a case where one kind of pattern such as only a row address is used as an address complement pattern. You can

In addition, when a pattern in which three or more types of patterns are combined is generated, the row address operation circuit 30 is used.
a, a subtraction circuit 31a, a row maximum value register 32a, and a selection circuit 33a, or a column address operation circuit 3
0b, the subtraction circuit 31b, the column maximum value register 32b, and the selection circuit 33b may be provided as many as the number of patterns required. Further, in the above embodiment, the row maximum value register 31a and the column maximum value register 31 are
Although the case where "5" is stored as the maximum value in b has been described as an example, the maximum value stored in the row maximum value register 31a and the maximum value stored in the column maximum value register 31b are:
They may be the same or different and can be set individually.

[0042]

As described above, according to the present invention,
The calculating unit generates the first pattern, and the subtracting unit generates the second pattern by subtracting the first pattern from the maximum value of the address stored in the storage unit. The selecting unit generates either the first pattern or the second pattern. Since one of them is selected, there is an effect that a pattern such as an address complement pattern can be easily generated without limiting the maximum value.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention including a pattern generation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an address pattern generator 12 as a pattern generator according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining an example of an operation during a test of the semiconductor memory 20 using the address pattern S6 output from the address pattern generator 12.

4 is a timing chart showing signal waveforms of respective parts of the address pattern generator 12 shown in FIG.

FIG. 5 is a diagram for explaining an example of an operation at the time of testing a semiconductor memory using an address complement pattern.

FIG. 6 is a block diagram showing a configuration of a conventional pattern generator that generates an address complement pattern.

FIG. 7 is a timing chart showing signal waveforms of respective parts of the conventional pattern generating device 50 shown in FIG.

[Explanation of symbols]

10 sequence controller (control unit) 11 instruction memory (control unit) 12 address pattern generator (pattern generator) 30a row address operation circuit (operation unit) 30b column address operation circuit (operation unit) 31a line maximum value register (storage) Part) 31b column maximum value register (storage part) 32a, 32b subtraction circuit (subtraction part) 33a, 33b selection circuit (selection part) S3 address pattern generation command signal (control signal) S6 address pattern (pattern) S41, S42 operation result (First pattern) S61, S62 Subtraction result (second pattern)

Claims (7)

[Claims] 1. A pattern generator for performing a calculation in accordance with a control signal input from the outside to generate a specific pattern, and a calculation section for performing a calculation in accordance with the control signal to generate a first pattern, A storage unit that stores the maximum value of the generated pattern; a subtraction unit that generates a second pattern by subtracting the first pattern generated by the calculation unit from the maximum value of the pattern stored in the storage unit; A first unit generated by the arithmetic unit based on the control signal,
A pattern generation device, comprising: a selection unit that selects and outputs one of the pattern and the second pattern generated by the subtraction unit. 2. The pattern generator according to claim 1, wherein the storage unit stores an arbitrary natural number as the maximum value of the pattern. 3. The calculation unit, the storage unit, the subtraction unit,
2. The pattern generating apparatus according to claim 1, further comprising a plurality of selecting units, wherein the pattern generating apparatus generates a pattern including a plurality of types of patterns as a set. 4. The pattern generating apparatus according to claim 3, wherein each of the storage units individually stores an arbitrary natural number as the maximum value of the pattern. 5. The pattern generating apparatus according to claim 1, wherein the pattern is a pattern given as an address to an object to be tested. 6. A semiconductor integrated circuit test, comprising: the pattern generation device according to claim 1; and a control unit that outputs a control signal to be given to the pattern generation device. apparatus. 7. A pattern generating method for performing a calculation according to a control signal to generate a specific pattern, the first pattern generating step of performing a calculation according to the control signal to generate a first pattern, A second pattern generating step of generating a second pattern by subtracting the first pattern from the maximum value of the pattern, and selecting and outputting one of the first pattern and the second pattern based on the control signal A method of generating a pattern, comprising: