JPS60229146A - Automatic switching device of spare unit - Google Patents

Abstract

PURPOSE:To omit production of a test pattern and the expected value of an output response corresponding to said pattern and to simplify greatly a test stage by producing the expected pseudo-value used as a comparison standard from the output response of a part to be tested itself in a test mode. CONSTITUTION:A test mode is set when a control circuit 12 is driven by an external input signal 13. A state switch circuit 7 selects the output of a test pattern generator 5 and impressed it to an input terminal 2 of a part 1 to be tested. As a result, the same test pattern 6 is supplied to each unit, and each unit shows the same output response when no fault is detected. A correct response can be estimated from said output response despite the generation of a fault and as long as the fault generation factor is small. A false expected pseudo-value producing circuit 8' applies the decision by majority to the output response and decides a comparison standard with output signals occupying the majority. This output signal is compared with the output signal of the circuit 8' by a comparator 10 to decides whether or not the number of normal units exceeds K units. When a test mode is over, the part 1 executes a prescribed function according to the combination of function units decided by the signal of the decision result 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a spare unit automatic switching device for switching functional units of a device having a redundant configuration with a built-in test function.

(Prior Art) Generally, the motive for implementing equipment with a redundant configuration is to maintain high reliability against failures and defects both statically and dynamically. For this reason, especially in integrated circuits and the like, it has been desired to eliminate functionally redundant parts as much as possible, excluding parts essential for realizing a predetermined function. Therefore, in a device with a redundant configuration, the challenge is to minimize the control part for redundant switching, and a realistic method is to provide most of the dest circuits necessary for determining the normality of the switching unit externally. Met. However, with this method, the features of the original redundant configuration, such as self-testing and automatic switching of units, cannot be fully utilized by the equipment alone.

Fig. 1 shows the configuration of a conventional spare unit automatic switching device, where 1 is the unit to be tested, which is composed of N (N is any integer) functional units (1□ to IN) with the same configuration. , 2 is an input terminal of the part to be tested, 3 is an output terminal of the part to be tested, 4 is an external input signal (terminal) which is the first signal, and 5 is a test bang generator for applying to the part to be tested. A test pattern 6, which is the second signal of the test pattern 6, is generated. Reference numeral 7 denotes a state switching circuit which selects the external input signal 4 (actually appears as its output 16 through the input switching circuit 15 as described later) in the first state, which is the normal state, and selects the external input signal 4 (actually, as described later, appears as its output 16 through the input switching circuit 15). In the test state, test pattern 6
is selected and output to input terminal 2. 8 is test pattern 6
This is an expected value generation circuit for generating a correct output response value of the unit under test 1 corresponding to do. 10 is expected value generation port vr8
This is a comparison circuit that compares the expected value 9, which is the output value of the unit, with the output value of the output terminal 3 of the tested part to determine pass/fail, and realizes the pass/fail status of each functional unit and a predetermined function. A determination result 11 is output as to whether or not there are at least one normal functional unit required for the purpose. 12 is a control circuit for controlling the whole, 13 is a third signal which is an external input signal to the control circuit, and 14 is an output signal of the control circuit 12, which is a control signal for each functional block. Reference numeral 15 denotes an input switching circuit, which sends the set of input signals corresponding to the functional unit 1- to the normal functional units out of N determined by the quality judgment result 11 of each functional unit as an input switching circuit output 16. distribute. 17 is an output switching circuit, and input switching circuit 1
The outputs of the functional units 1 to 1 specified by 5 are selected and outputted to the external output signal terminal 18.

The operation of the apparatus having such a configuration will be explained in the order of test state 1 and proper state.

<Test state> The control circuit 12 is driven by turning on the power or by giving a test execution trigger as an external input signal 13 to the control circuit. As a result, the control circuit output signal 14, which is the output of the control circuit 12, puts each functional block into a test state. In the dead state, the test bang generator 5 generates a desired test pattern, and the state switching circuit 7 selects the test pattern 6 of the test bang generator 5 and applies it to the input terminal 2 of the section under test 1.

As a result, each functional unit receives a common test pattern. The expected value generation circuit 8 outputs the expected value 9 of the output response, which is the correct response value of the functional unit corresponding to the test pattern.

For this reason, the output result of the output terminal 3 of each functional unit is compared with the expected value 9 of the output response of the expected value generation circuit by the comparison circuit 10, and it is determined whether or not it has operated correctly. Along with the result, a judgment result 11 indicating whether or not there are more than enough normal functional units to realize a predetermined function is output.

Based on the judgment result, if there are at least one normal functional unit, the input switching circuit 15 and the output switching circuit 17 select a combination of the functional units determined by the signal of the judgment result 11.
If the number of normal functional units is less than 1, the control circuit is instructed that the predetermined function cannot be normally realized, the dead state is ended, and the normal state is entered.

<Normal state> In the normal state, the control circuit 12 causes the state switching circuit 7 to select the output 16 of the input switching circuit 15 and apply it to the input terminal 2 of the part 1 to be tested. The operations of the generation circuit 8 and comparison circuit 10 are inactivated. As a result, the tested section 1 enters a normal state and executes a predetermined function.

In this way, with conventional automatic functional unit switching devices for redundant configuration logic devices, it is necessary to prepare in advance the expected value of the output response corresponding to the test patterns that are effective for detecting failures and defects when testing the part under test. be. This is determined by logic simulation or by hand, and is the most troublesome task in the testing process, and the number of steps is said to be proportional to the second to third power of the scale of the logic device. In addition, when performing self-tests within the device, it is necessary to incorporate a large memory to store these and hardware to control it.
Hardware load increases.

For this reason, when creating test patterns, it has been considered to ignore the logical structure and generate random patterns, thereby significantly reducing the number of test man-hours. Furthermore, it is considered that the amount of data can be reduced by compressing the output response. Even in this case, there are drawbacks such as the need to increase the number of deathblows in order to increase the failure detection rate, omissions due to compression, and the need for expected values.

(Objective of the Invention) In order to eliminate these drawbacks, the present invention focuses on a repeatable logical structure, and instead of preparing a comparison reference value in advance, it generates it from the output response of the tested part itself. The aim is to provide a spare unit switching device with
The drawings will be explained in detail below.

(Structure and operation of the invention) FIG. 2 is a block diagram showing the structure of an embodiment of the invention.
The difference is that a pseudo expected value generating circuit 8' is used instead of the expected value generating circuit 8 of the conventional device shown in FIG. Same as shown.

The pseudo expected value generation circuit 8' is a circuit for creating a comparison reference value from the output response values of each of the functional units 11 to IN of the part under test 1, and uses the response value that accounts for the majority of the responses of the plurality of functional units. It is mainly composed of a majority circuit which outputs an output, and 9' is its output signal.

This operation starts by applying the 1~RIG signal as the external input signal 13 to the control circuit upon power-on or test instruction;
The process begins by driving the control circuit 12. Control circuit 1
2 is driven, its output is the control circuit output signal 1
4, each functional block enters a test state. In the test state, the destop bar 92 generator 5 generates a predetermined test pattern, and the state switching circuit 7 selects the test pattern 6 that is the output of the test pattern generator 5 and applies it to the input terminal 2 of the part under test 1. . As a result, each functional unit receives a common test pattern 6 as input. Therefore, if there is no failure or defect in each functional unit, I will all show the same output response. Furthermore, even in the case of a failure or defect, if the probability of its occurrence is small, the correct response sequence can be estimated from the response sequences of a plurality of functional units. From this point of view, the pseudo expected value generation circuit 8' takes a majority vote on the output responses of the N functional units, and uses the output signal 9' that accounts for the majority as a comparison standard (correct response series).

Therefore, the output responses obtained from the output terminals 3 of each of the functional units 1 to 1 are compared with the output signal 9 of the pseudo expected value generation circuit 8' by the comparison circuit 10, and if they match, it is normal (good), and if they do not match, it is normal (good). It is determined that it is abnormal (defective), and the determination result as to whether or not there are more than the number of normal functional units is output as a determination result 11.

The judgment result 11 set in the test state is retained even in the normal state, and based on the judgment result 11, if there are more than one normal functional unit, the combination of functional units determined by the signal of the judgment result 11 is determined. Input switching circuit 1
5 and the output switching circuit 17, and if the number of normal functional units is less than one, it is indicated that the predetermined function cannot be normally realized and the test state is terminated.

When the test state is completed, the control circuit 12 enters the normal state. In the normal state, the state switching circuit 7 is the input switching circuit 1.
5 is selected and applied to the input terminal 2 of the unit under test 1, and the test pulse generator 5 and the pseudo expected value generation circuit 8'
and inactivates the operation of the comparison circuit 10. As a result, the unit under test 1 executes a predetermined function by the combination of functional units determined by the signal of the determination result 11.

FIG. 3 shows an embodiment of the present invention, which has a configuration in which the number of output responses of the functional units input to the majority circuit constituting the pseudo expected value generation circuit is limited. this is.

The number of inputs to the pseudo expected value generation circuit 8' is (2(N-K)+
1), the meanings and operations of the numbers are exactly the same as in Figure 2. In Figure 3, although the detailed pass/fail distribution of each functional unit is sometimes unknown, the objective of realizing a predetermined function using only normal functional units and a K out of N redundant configuration is achieved with exactly the same accuracy. can. Therefore, the pseudo expected value generation circuit 8' is simplified, and the overall amount of hardware can be reduced. Note that the minimum number of inputs to the pseudo expected value generation circuit 8' is (2(N-K)+1), and it goes without saying that the number may be greater than this.

Next, the normality of the functional unit will be described.

Generally, when a large number of test patterns are applied to a plurality of units having the same configuration, the following two terms can be said. ■
The output responses of normal functional units always match.

■ Abnormal (defective) functional unit (- It is rare that the output responses of the same unit always match (the probability of occurrence is very small).

) Therefore, assuming the above 2 items as preconditions, the output response of a specific functional unit is assumed to be a pseudo expected value, and this is compared with the output response of other functional units to determine the vehicle number of all units at the same time. is possible.

FIG. 4 is a flowchart 1- showing the basic concept of another embodiment of the present invention based on the above viewpoint.

First, a specific functional unit is selected as a comparison standard, and its output response is compared with the output responses of other functional units. If the results do not match all the functional units, the functional unit used as the comparison standard is determined to be defective (defective), and the test continues by selecting another functional unit as a new comparison standard. Functional unit 1 that should become a new comparison standard
If there is no -, it is determined that all functional units are defective and the test is terminated.Also, if the comparison result is not a mismatch in all parts, the functional unit that is the comparison standard is considered normal, and the comparison result is applied to each functional unit as it is. The test ends as a result of the pass/fail judgment.

FIG. 5 shows an embodiment of the present invention having a configuration based on the basic concept shown in FIG. 4, and the meanings and operations of symbols 1 to 7 and 10 to 18 are exactly the same as in FIGS. 2 and 3. be. Reference numeral 8' designates a pseudo expected value generation circuit for extracting the output response of an arbitrary functional unit of the tested section and using it as a comparison standard, and is mainly configured with a multiplexer function, and 9' is its output signal.

Reference numeral 19 denotes a coincidence judgment circuit for judging whether all the pass/fail judgment results match or not, and its output 20 is input to a control circuit to control the test sequence. In the test sequence up to the end of the quality determination of each functional unit in FIG. However, the quality of other functional units is unknown. Also, if there is at least one functional unit that matches the other, the functional unit used as the comparison standard is considered normal;
The comparison result of each functional unit is directly used as the pass/fail determination result, and Test I~ is completed. Therefore, if the judgment results of each functional unit I~ are all inconsistent, the pseudo expected value generation circuit 8
' is switched to another functional unit, and the above test cycle is repeated until the comparison standard is determined to be normal or there are no more functional units 1 to 1 to be switched.

FIG. 6 also shows another embodiment of the present invention, and has a configuration in which the number of output responses of the functional units input to the multiplexer circuit constituting the pseudo expected value generation circuit is limited. In FIG. 6, the number of inputs to the pseudo expected value generation circuit 8' is (N-K)+1
The meanings and operations of the numbers are exactly the same as in FIG. 5, except for . In this way, the detailed pass/fail distribution of each functional unit 1- may be unknown, but normal functional units 1-1-
With the K out of N redundancy configuration, the objective of realizing a given function can be achieved with exactly the same accuracy using only K out of N redundant configurations.

FIG. 7 is a flowchart 1~ showing an outline of the operation in FIG.
In the case of Figures 4 and 5, a maximum of (N-1) 9 cycles of death were required, whereas in Figure 7, five shaku (N-K) cycles were required.
)+1 test cycle can significantly shorten test time. Furthermore, the pseudo expected value generation circuit can be simplified and the amount of hardware can be reduced. The number of inputs to the pseudo expected value generation circuit is (
NK)+1 is the minimum value, and it goes without saying that it may be greater than this. Further, the control circuit creates a functional unit i/selection signal as a comparison and lA standard in accordance with the number of inputs to such a pseudo expected value generation circuit.

(Effects) As explained above, in the present invention, the pseudo expected value serving as the comparison standard is generated from the output response of the tested part itself during the test, so it is not necessary to consider the input test pattern depending on the function of the device. Therefore, it is not necessary to create a test pattern or an expected value of an output response corresponding to the test pattern, and the testing process can be greatly simplified.

As a result, RAM, ROM, and related peripheral circuits for generating expected values are unnecessary, and the amount of hardware can be reduced. Further, the present invention has the advantage that automatic repair of defects can be realized, and a logic device that operates completely upon power-on can be realized with a high yield value.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional spare unit 1 to an automatic switching device, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 3, 5, and 6 are diagrams of the present invention. FIGS. 4 and 7 are flowcharts showing the basic concept of other embodiments of the present invention. 1. 1 part to be tested, 18. Functional unit, 2. Input terminal, 3. Output terminal, 4. External input signal (terminal), 5. Test bang generator, 6.
・Death button, 7 ・State switching circuit, 8 ・・
Expected value generation circuit, 8'...Pseudo expected value generation circuit,
9...Expected value of output response, 9'...Output signal, 10
... Comparison circuit, 11 ... Judgment result, 12 ... Control circuit, 13 ... External input signal (terminal) to control circuit, 1
4 ・Control circuit output signal, 15... Input switching circuit, 1
6...Input switching circuit output, 17...Output switching circuit, 1
8... External output signal terminal, -19, match determination circuit, 2
0... Match determination circuit output. Patent Applicant Nippon Telegraph and Telephone Public Corporation Figures 1 to 4 Figure 5 m

Claims (3)

[Claims] (1) From N functional units with the same configuration to K (2≦K<
N) an input switching means for supplying a first signal from the outside to a group of functional units determined by a control signal; A state switching means for switching the input to the group is provided on the input side, the first signal and the control signal are input to the input switching means, and the output of the input switching means and the second signal and control signal generated within the device are connected. is input to a state switching means, in a first state determined by a control signal, the output of the input switching means is selected, and in a second state, the second signal is selected and input to each functional unit, On the output side, there is a reference value generation means that takes the output of each functional unit as input and generates a judgment reference value for determining the normality of each functional unit, and a reference value generation means that receives the output of the reference value generation means and the output of each functional unit. A determining means for comparing and determining the normality of each functional unit, a condition detecting means for receiving the output of the determining means as an input and detecting whether there are at least one normal functional unit, and a determining means/condition detecting means. A control means for controlling the whole by each output and a third signal from the outside, and a control signal and N
Output way switching means receives the output way of N functional units as an input and selects the output of N functional unit groups selected by the input switching means from among the N functional units and sets it as the output way of the device. The third signal determines the normality of each functional unit, and if there are at least one functional unit that is normal based on the determination result, automatically selects from N functional units and performs the predetermined function. 1. A spare unit automatic switching device characterized in that when the number of normal functional units is less than 1, it automatically indicates that a predetermined function cannot be normally realized. (2) Claim (1) characterized in that, as the reference value generation means, majority voting means is used which outputs the results that account for a majority of the output results of each functional unit.
Spare unit automatic switching device described in Section 1. (3) Claim No. 1 (1) characterized in that the output result of an arbitrary functional unit is used as the reference value generation means.
) Spare unit automatic switching device/