JPH07191102A - Automatic inspection line producer - Google Patents

Abstract

PURPOSE:To produce a short inspection line at a high speed in automatic inspection line production for a combined circuit. CONSTITUTION:An automatic inspection line production part 101 produces the first patten for constituting an inspection line and a fault simulator 102 performs fault simulation by using the first pattern so that a set of the first pattern and a fault detectable by the first pattern is input to an inspection line compressor 103. In the inspection line compressor 103, the inspection line can be compressed by deletion of the first pattern. When the first pattern is output as the second pattern for constituting the compressed inspection line, to an output part 106, any fault detectable by the second pattern is deleted out of target faults in the automatic inspection line production part 101 and the fault simulator 102 so as to shorten an inspection line production time and a fault simulation time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test sequence automatic generation device for automatically generating a test sequence for a combinational circuit.

[0002]

2. Description of the Related Art As a conventional automatic inspection sequence generation method,
A target fault in a combinational circuit is randomly selected, a test sequence for detecting the fault is generated, and it is determined whether the target fault in the combinational circuit can be detected using the pattern in the test sequence. A method is known in which a simulation is performed to investigate, and then the sequence length of the test sequence is shortened, that is, the test sequence is compressed.

[0003]

However, in the above-described conventional test sequence automatic generation method, since the test sequence is compressed as a post-process, the fault simulation of the test sequence targets all the faults in the combinational circuit. Therefore, there is a problem that the failure simulation time becomes huge.

By the way, the following is considered as an example of the test sequence compression processing in the automatic test sequence generation.

FIG. 2 is a block diagram showing the configuration of a test sequence automatic generation apparatus having a test sequence compression unit 203 for compressing a test sequence. In FIG. 2, reference numeral 201 denotes a test sequence automatic generation unit that randomly selects a target fault in a combinational circuit and generates a test sequence for detecting the fault, and 202 inputs a pattern in the test sequence. And 203 is a fault simulator for checking whether or not a target fault in the combinational circuit can be detected using the pattern, 203 is a check sequence compression unit, and 204 is a pattern and a pattern detected using this pattern. Is a buffer capable of storing one or more sets of detected faults, and 205 is an output unit for storing the test sequence after compression processing. The test sequence compressing unit 203 receives the test sequence as input, stores it in the buffer 204, checks the coverage of the detection fault for each pattern in the test sequence, and deletes the pattern in which all the detection faults are covered from the buffer 204. The test sequence is compressed, and when the buffer 204 is full, the pattern with the most detected faults is output from the buffer 204 to the output unit 205, and the detected faults of the output pattern are sent to the detected faults in the buffer 204 and thereafter to the buffer 204. It is deleted from the detection failure of the input inspection sequence.

The operation of the test sequence automatic generation device configured as described above will be described. Here, the buffer 20
It is assumed that the size of 4 is 3 and a test sequence is generated for a single stuck-at fault in the combinational circuit shown in FIG.
In FIG. 3, 10 to 13 are external input signal lines, and 20 and 2.
Reference numeral 1 is an external output signal line, and 30 to 38 are signal lines assuming a single stuck-at fault.

First, the test sequence automatic generation unit 201 generates a pattern until all target faults in the combinational circuit are detected, and the fault simulator 202 processes 18 faults (Table 1). The test sequence shown shall be generated.

[0008]

[Table 1]

In the description of the detected failure column in (Table 1), the number on the left side of "/" indicates the signal line, and the number on the right side indicates the failure of the signal line. If it is ", it indicates a stuck-at-0 fault.

Next, the set of the pattern at time 1 and the seven detected faults that can be detected by this pattern are input to the test sequence compression unit 203 and stored in the buffer 204.

Next, the set of the pattern at time 2 and the four detected faults that can be detected by this pattern are input to the test sequence compression unit 203, stored in the buffer 204, and the buffer 2 is stored.
Check the fault coverage within 04. However, since there is no pattern that covers all the detected faults, the next pattern is input.

Next, the set of the pattern at time 3 and the five detected faults that can be detected by this pattern are input to the test sequence compression unit 203, stored in the buffer 204, and stored in the buffer 2.
Check the fault coverage within 04. However, no pattern covers all detected faults. Buffer 20
4 is full, the pattern at time 1 with the largest number of detection failures is output to the output unit 205, and the inspection failure of the pattern at time 1 is detected as the pattern detection failure in the buffer 204 and the time 4
It is deleted from the detection failures of the following patterns.

Next, the set of the pattern at time 4 and the three detected faults that can be detected by this pattern are input to the test sequence compression unit 203, stored in the buffer 204, and stored in the buffer 2.
Check the fault coverage within 04. However, no pattern covers all detected faults. Buffer 20
4 is full, the pattern at time 3 with the largest number of detection failures is output to the output unit 205, and the detection failure of the pattern at time 3 is detected with the pattern detection failure in the buffer 204 and the time 5
It is deleted from the detection failures of the following patterns.

Next, the set of the pattern at time 5 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 203, stored in the buffer 204, and the buffer 2 is stored.
Check the fault coverage within 04. Since the detection failure of the pattern at time 5 is covered by the detection failure of the pattern at time 4, the buffer 204 stores the pattern at time 5 and the detection failure.
Remove from.

Next, the set of the pattern at time 6 and the two detected faults that can be detected by this pattern are input to the test sequence compression unit 203, stored in the buffer 204, and stored in the buffer 2.
Check the fault coverage within 04. However, no pattern covers all detected faults. Buffer 20
4 is full, the pattern at time 2 with the largest number of detected failures is output to the output unit 205, and the detected failure of the pattern at time 2 is detected with the detected failure of the pattern in the buffer 204 and the time 7
It is deleted from the detection failures of the following patterns.

Next, the set of the pattern at time 7 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 203, stored in the buffer 204, and the buffer 2 is stored.
Check the fault coverage within 04. Since the detection failure of the pattern at time 7 is covered by the detection failure of the pattern at time 6, the buffer 204 stores the pattern at time 7 and the detection failure.
Remove from.

Next, the set of the pattern at time 8 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 203, stored in the buffer 204, and the buffer 2 is stored.
Check the fault coverage within 04. Since the detection failure of the pattern at time 8 is covered by the detection failure of the pattern at time 4, the buffer 204 stores the pattern at time 8 and the detection failure.
Remove from.

Next, since all the detection failures of the pattern at time 9 have been deleted, the next pattern is input.

Next, a set of the pattern at time 10 and two detected faults that can be detected by this pattern is input to the test sequence compression unit 203, stored in the buffer 204, and the coverage relation of the faults is stored in the buffer 204. Find out. Since the detection failure of the pattern at time 4 is covered by the detection failure of the pattern at time 10, the buffer 2 stores the pattern at time 4 and the detection failure.
Delete from 04.

As described above, the pattern output to the output unit 205 and the pattern remaining in the buffer 204 are combined to generate the compressed test sequence shown in (Table 2).

[0021]

[Table 2]

However, in the test sequence automatic generation apparatus as described above, when performing the compression process, it is necessary to examine the fault coverage relationship between the patterns with many detected faults, so that it takes an enormous amount of time to compress the test sequence. There is a problem that it ends up.

The present invention has been made in view of the above, and an object of the present invention is to provide an automatic test sequence generation device capable of generating a test sequence having a short sequence length at high speed.

[0024]

To achieve the above object, the present invention is to generate a test sequence having a short sequence length at a high speed by simultaneously generating and compressing a test sequence.

Specifically, the solution means taken by the invention of claim 1 is a combinational circuit for a test series automatic generation device, which constitutes a test series for checking the presence or absence of a target fault in the combinational circuit. Pattern generation means for generating a first pattern, which is a set of values simultaneously set as external inputs of the, and a fault simulation for checking whether or not the target fault in the combinational circuit can be detected using the first pattern. And a pair of the first pattern and a fault detectable by the first pattern are inputted, and the first pattern is deleted from the inspection sequence or the first pattern is compressed. When a test sequence compression process of outputting as a second pattern forming a check sequence is performed and the first pattern is output as the second pattern, And a test sequence compression unit that executes a fault deletion process that deletes a fault that can be detected by the second pattern from a fault that is targeted in the fault simulation that is performed by the fault simulation execution unit. Is.

Further, the invention of claim 2 is, specifically,
In the configuration of the invention of claim 1, when the test sequence compression means outputs the first pattern as the second pattern, the failure simulation execution means executes a failure detectable by the second pattern. By deleting from the target fault in the fault simulation, the fault detectable by the second pattern from the target fault in the generation of the first pattern executed by the pattern generating means. This is to add a configuration for executing the failure deletion processing.

Further, the invention of claim 3 is, specifically, in the structure of the invention of claim 1, wherein the check sequence compression means is a combination of the first pattern and a fault detectable by the first pattern. And a buffer capable of storing the first pattern and outputting the first pattern as the second pattern when a predetermined condition is satisfied, and a failure detectable by the first pattern and the first pattern when the predetermined condition is not satisfied. In the buffer, and when two or more sets of the first pattern and a fault detectable by the first pattern are stored in the buffer, one of the buffers in the buffer is stored. It is checked whether or not there is a fault coverage relationship in which the fault detectable by the first pattern is included in the faults detectable by the other first patterns in the buffer,
A second pattern that deletes a set of the first pattern and a fault detectable by the first pattern from the buffer when a first pattern that covers all the detectable faults exists in the buffer. And a third step of selecting one first pattern from the first patterns in the buffer and outputting the one first pattern as the second pattern when the buffer is full And a test sequence compression process executing means for executing the test sequence compression process by executing the above.

Further, the invention of claim 4 is, specifically,
In the configuration of the invention of claim 3, the check sequence compression processing execution means is provided when the number of faults that can be detected by the first pattern is n or more (where n is all targets in the combinational circuit). The first pattern is output as the second pattern, while the first pattern and the first pattern are output when the number of faults detectable by the first pattern is less than n. A configuration for executing the first step is added by storing a set of faults that can be detected by one pattern in the buffer.

The invention of claim 5 is, specifically, claim 4
In the configuration of the present invention, the check sequence compression processing execution means has the largest number of uncovered faults among the detectable faults from the first pattern in the buffer when the buffer is full. A configuration for executing the third step by selecting a large number of first patterns and outputting the first patterns as the second patterns is added.

[0030]

According to the configuration of the invention of claim 1, the pattern generating means generates the first pattern forming the inspection sequence, and the first pattern
The failure simulation is executed by the failure simulation executing means using the pattern. As a result, the first pattern reveals a detectable fault. Where the first
The test sequence can be compressed by deleting the pattern from the test sequence by the test sequence compression means. Further, when the first pattern input to the test sequence compression means is output from the test sequence compression means as the second pattern forming the compressed test sequence, the test sequence compression means can detect the second pattern. The fault is deleted from the faults targeted in the fault simulation.

By simultaneously generating and compressing the test sequence in this way, the second pattern forming the compressed test sequence can be determined during the generation of the test sequence. Therefore, by deleting the fault that can be detected by the second pattern from the fault simulation target, it is possible to reduce the amount of simulation processing. Therefore, the failure simulation time can be shortened.

Further, according to the configuration of the second aspect of the present invention, by eliminating the fault that can be detected by the second pattern from the target in the generation of the first pattern forming the inspection series, the processing amount of the inspection series generation processing is increased. Can be reduced, so that it is possible to shorten the inspection sequence generation processing time.

According to the third aspect of the invention, the test sequence compressing means compresses the test sequence by using the buffer and checking the fault coverage between the plurality of first patterns stored in the buffer. Processing can be realized.

Further, according to the structure of the fourth aspect of the present invention, in the inspection sequence compression means, the fault coverage relation is examined only for the first pattern in which the number of detectable faults is less than n. Therefore, it is possible to reduce the processing time of the compression processing of the inspection series.

According to the configuration of the fifth aspect of the present invention, in the test sequence compressing means, when the buffer is full, the first pattern having the largest number of uncovered faults constitutes the compressed test sequence. Output as a pattern.
The detection failure of the first pattern, which has the largest number of uncovered failures, is less likely to be covered later by the detection failure of the other first pattern. Therefore, by outputting it as the second pattern, the compression efficiency of the test sequence is improved. Can be improved.

[0036]

【Example】

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described.

FIG. 1 is a block diagram showing the arrangement of the test sequence automatic generation apparatus according to the first embodiment. In FIG. 1, 1
Reference numeral 01 is a test sequence automatic generation unit as pattern generation means for randomly selecting a target fault in a combinational circuit and generating a pattern constituting a test sequence for detecting the fault, and 102 is a test sequence. A failure simulator is a failure simulation executing means for checking whether or not a target failure in a combinational circuit can be detected by using the pattern generated by the automatic generation unit 101 as an input, and 104 is an inspection series. Reference numeral 105 denotes a control unit as a compression processing execution unit, 105 is a buffer capable of storing one or more sets of patterns and detection failures detected using the patterns, and 103 is a control unit 104 and a buffer 105. Reference numeral 106 denotes a test sequence compression unit as a test sequence compression unit that is provided, and 106 is a compression sequence output from the test sequence compression unit 103. An output unit for storing a pattern constituting a by test sequence. The control unit 104 receives the pattern generated by the test sequence automatic generation unit 101 as an input,
If the number of detected faults that can be detected by this pattern is n or more, the pattern is output to the output unit 106, while if it is less than n, the pattern and the detected fault of this pattern are stored in the buffer 105, and the buffer 105 is stored. The inspection sequence is compressed by checking the covering relation of the detected faults for each pattern in the buffer, and deleting the pattern in which all the detected faults are covered from the buffer 105. When the buffer 105 is full, the detected faults are the most frequent. Pattern buffer 10
5 to the output unit 106, and the detection fault of the pattern output to the output unit 106 is detected from the detection fault in the buffer 105, the fault targeted by the test sequence automatic generation unit 101, and the fault targeted by the fault simulator 102. delete.

The operation of the test sequence automatic generation apparatus of the first embodiment configured as above will be described. Here, it is assumed that the size of the buffer 105 is 3, n in the determination process executed by the control unit 104 is 4, and a test sequence is generated for a single stuck-at fault in the combinational circuit shown in FIG. .

Table 3 shows that, when the test sequence automatic generation apparatus of the first embodiment is applied to the combinational circuit shown in FIG. 3, the test sequence automatic generation is performed until all target faults in the combinational circuit are detected. The patterns of the inspection series generated by the unit 101 and the detected faults detectable by each pattern are shown.

[0040]

[Table 3]

First, the test sequence automatic generation unit 101 performs time 1
Pattern "1100" is generated and failure simulator 1
In 02, a failure simulation is performed for 18 failures to detect 7 failures. When a pair of the pattern at time 1 and the seven detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are seven detected faults and n
= 4 or more, the control unit 104 outputs the pattern at time 1 to the output unit 106, and deletes the detected failure of the pattern at time 1 from the 18 failures targeted by the test sequence automatic generation unit 101 and the failure simulator 102. .

Next, the test sequence automatic generation unit 101 performs time 2
Failure simulator 1
In 02, a failure simulation is performed for 11 failures to detect 3 failures. When the set of the pattern at time 2 and the three detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are three detected faults and n
= 4, the control unit 104 stores the pattern at time 2 and the detected failure in the buffer 105.

Next, the test sequence automatic generation unit 101 sets time 3
Failure simulator 1
In 02, a fault simulation is performed for 11 faults to detect 5 faults. When a set of the pattern at time 3 and the five detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are five detected faults and n
= 4 or more, the control unit 104 outputs the pattern at time 3 to the output unit 106, and deletes the detected failure of the pattern at time 3 from the 11 failures targeted by the test sequence automatic generation unit 101 and the failure simulator 102. With buffer 1
It is deleted from the detection failure of the pattern at time 2 in 05.

Next, the inspection sequence automatic generation unit 101 sets time 4
Pattern "0001" is generated and the fault simulator 1
In 02, a fault simulation is performed for 6 faults to detect 2 faults. When a pair of the pattern at time 4 and two detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are two detected faults and n =
Since there are less than four, the control unit 104 stores the pattern at time 4 and the detected failure in the buffer 105. Buffer 1
The coverage relation of the fault is examined in 05, but since there is no fault coverage, the process moves to the generation of the next pattern.

Next, the test sequence automatic generation unit 101 performs time 5
Pattern 1101 is generated and the failure simulator 1
In 02, a fault simulation is performed for 6 faults to detect 1 fault. When a pair of the pattern at time 5 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 103, there is one detected fault and n =
Since there are less than four, the control unit 104 stores the pattern at time 5 and the detected failure in the buffer 105. Buffer 1
When the fault coverage relation is examined in 05, the pattern detection fault "36/1" at time 5 is covered by the pattern detection fault "34/0, 36/1" at time 4, so The detected failure is deleted from the buffer 105.

Next, the test sequence automatic generation unit 101 performs time 6
Pattern 1111 is generated and the failure simulator 1
In 02, a fault simulation is performed for 6 faults to detect 2 faults. When a pair of the pattern at time 6 and two detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are two detected faults and n =
Since there are less than four, the control unit 104 stores the pattern at time 6 and the detected failure in the buffer 105. Buffer 1
The fault coverage is examined in 05, but there is no fault coverage. Since the buffer 105 is full, the pattern at time 4 with the largest number of detected failures is output to the output unit 106, and the detected failure of the pattern at time 4 is targeted by the test sequence automatic generation unit 101 and the failure simulator 102. The faults are deleted from the individual faults, and are deleted from the detection fault of the pattern at time 2 and the detection fault of the pattern at time 6 in the buffer 105.

Next, the test sequence automatic generation unit 101 sets time 7
Pattern "0010" is generated and the failure simulator 1
In 02, a fault simulation is performed for four faults to detect one fault. When a pair of the pattern at time 7 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 103, there is one detected fault and n =
Since there are less than four, the control unit 104 stores the pattern at time 7 and the detected failure in the buffer 105. Buffer 1
When the fault coverage relation is examined in 05, the pattern detection fault “33/1” at time 7 is covered by the pattern detection fault “33/1, 35/0” at time 6, so The detected failure is deleted from the buffer 105.

Next, the inspection sequence automatic generation unit 101 sets time 8
Pattern "1001" is generated and the failure simulator 1
In 02, a fault simulation is performed for four faults to detect one fault. When a pair of the pattern at time 8 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 103, there is one detected fault and n =
Since there are less than four, the control unit 104 stores the pattern at time 8 and the detected failure in the buffer 105. Buffer 1
When the fault coverage relation is examined in 05, the detection fault “31/1” of the pattern at time 2 is covered by the detection fault “31/1” of the pattern at time 8, so that the pattern at time 2 and its detection fault are Is deleted from the buffer 105.

Next, at the inspection sequence automatic generation unit 101, time 9
Pattern 0101 is generated and the fault simulator 1
In 02, a fault simulation is performed for four faults to detect one fault. When a pair of the pattern at time 9 and one detected fault that can be detected by this pattern is input to the test sequence compression unit 103, there is one detected fault and n =
Since there are less than four, the control unit 104 stores the pattern at time 9 and the detected failure in the buffer 105. Buffer 1
The fault coverage is examined in 05, but there is no fault coverage. Since the buffer 105 is full, the pattern at time 6 having the largest number of detected failures is output to the output unit 106, and the detected failure of the pattern at time 6 is targeted by the test sequence automatic generation unit 101 and the failure simulator 102. The faults are deleted from the individual faults, and are deleted from the detection fault of the pattern at time 8 and the detection fault of the pattern at time 9 in the buffer 105.

As described above, when the pattern output to the output unit 106 and the pattern remaining in the buffer 105 are combined, the compressed test sequence shown in (Table 4) is obtained, and the test sequence shown in (Table 3) is obtained. A test sequence with a short sequence length can be obtained.

[0051]

[Table 4]

Further, since the target faults of the test sequence automatic generation unit 101 can be gradually reduced, the number of times the test sequence automatic generation unit 101 generates a pattern can be reduced. Further, since the failures targeted by the failure simulator 102 can be gradually reduced, the processing amount in the failure simulator 102 can be reduced. Further, in the buffer 105, since it is only necessary to check the fault coverage relation of the pattern having a maximum of three detected faults, it is possible to shorten the time for examining the fault coverage relation.

Therefore, according to the first embodiment, it is possible to quickly generate a test sequence having a short sequence length.

(Second Embodiment) A second embodiment of the present invention will be described below.

The test sequence automatic generation apparatus according to the second embodiment is
Except for the control unit of the test sequence compression unit, it has the same configuration as the test sequence automatic generation device of the first embodiment, and the control unit of the test sequence compression unit in the second embodiment detects that the buffer 105 is not covered when it is full. The pattern having the largest number of failures is output from the buffer 105.

The operation of the automatic test sequence generator of the second embodiment will be described. Here, as in the first embodiment, the size of the buffer 105 is set to 3, n in the determination process executed by the control unit is set to 4, and the test series is targeted for the single stuck-at fault in the combinational circuit shown in FIG. Shall be generated.

Table 5 shows that when the test sequence automatic generation apparatus of the second embodiment is applied to the combinational circuit shown in FIG. 3, the test sequence automatic generation is performed until all target faults in the combinational circuit are detected. The patterns of the inspection series generated by the unit 101 and the detected faults detectable by each pattern are shown.

[0058]

[Table 5]

Since the processing of the pattern from time 1 to time 5 is the same as that of the first embodiment, the description thereof will be omitted.
The process will be described starting with the generation of the pattern.

The test sequence automatic generation unit 101 generates the pattern "1110" at time 6, and the fault simulator 102 performs a fault simulation on six faults to detect two faults. When a pair of the pattern at time 6 and two detected faults that can be detected by this pattern is input to the test sequence compression unit 103, the number of detected faults is 2, which is less than n = 4. The pattern and the detected failure are stored in the buffer 105. The fault coverage is examined in the buffer 105, but there is no fault coverage. Since the buffer 105 is full, the pattern at time 6 having the largest number of uncovered detection failures is output to the output unit 106, and the detection failure of the pattern at time 6 is targeted by the test sequence automatic generation unit 101 and the failure simulator 102. It is deleted from the six detected failures and the detected failure of the pattern at time 2 and the detected failure of the pattern at time 4 in the buffer 105.

Next, the test sequence automatic generation unit 101 sets time 7
Pattern "1001" is generated and the failure simulator 1
In 02, a fault simulation is performed for four faults, and three faults are detected. When a set of the pattern at time 7 and three detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are three detected faults, and n =
Since there are less than four, the control unit stores the pattern at time 7 and the detected failure in the buffer 105. When the fault coverage is examined in the buffer 105, the pattern detection failure “31/1, 34/0” at time 2 and the pattern detection failure “34/0, 36/1” at time 4 are the pattern at time 7. Since the detection failures of "31/1, 34/0, 36/1" are deleted from the buffer 105, the patterns of the time 2 and the time 4 and the detected failures thereof are deleted.

Next, the inspection sequence automatic generation unit 101 sets time 8
Pattern 0101 is generated and the fault simulator 1
In 02, a fault simulation is performed for four faults, and three faults are detected. When the set of the pattern at time 8 and the three detected faults that can be detected by this pattern is input to the test sequence compression unit 103, there are three detected faults and n =
Since there are less than four, the control unit stores the pattern at time 8 and the detected failure in the buffer 105. The fault coverage is examined in the buffer 105, but there is no fault coverage.

When the pattern output to the output unit 106 and the pattern remaining in the buffer 105 are combined as described above, the compressed test sequence shown in (Table 6) is obtained, and the test sequence shown in (Table 4) is obtained. A test sequence with a short sequence length can be obtained.

[0064]

[Table 6]

Therefore, according to the second embodiment, when the buffer of the test sequence compressor is full, the pattern with the most uncovered detection faults is output first, thereby improving the compression efficiency of the test sequence. be able to.

In the first and second embodiments, the inspection sequence automatic generation unit 10 detects the detection failure of the pattern output to the output unit 106.
1 has been described as a case of deleting from the target fault, the number of times the pattern is generated is also reduced when the test sequence automatic generation unit 101 deletes the fault detected by the fault simulator 102 from the target fault. Similar effects can be obtained except that

[0067]

As described above, according to the test sequence automatic generation apparatus of the first aspect of the present invention, the second pattern forming the compressed test sequence is performed by simultaneously generating and compressing the test sequence. Can be determined during the generation of the test series. Therefore, by deleting the fault that can be detected by the second pattern from the fault simulation target, the processing amount of the simulation process can be reduced, and the fault simulation time can be shortened.

Further, according to the test sequence automatic generation apparatus of the second aspect of the present invention, the fault that can be detected by the second pattern is deleted from the target in the generation of the first pattern that constitutes the test sequence. Since it is possible to reduce the processing amount of the generation processing of {circle around (3)}, it is possible to shorten the inspection series generation processing time.

According to the test sequence automatic generation apparatus of the third aspect of the present invention, the test sequence compression is performed by using the buffer and checking the fault coverage between the plurality of first patterns stored in the buffer. Processing can be realized.

Further, according to the automatic test sequence generation device of the fourth aspect of the present invention, since the fault coverage is examined only for the first pattern in which the number of detectable faults is less than n, the test sequence compression processing is performed. The processing time can be shortened.

According to the automatic test sequence generation device of the fifth aspect of the present invention, when the buffer is full, the first pattern having the largest number of uncovered faults is output as the second pattern. The compression efficiency of can be improved.

As described above, according to the present invention, it is possible to provide a test sequence automatic generation device capable of generating a test sequence having a short sequence length at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a test sequence automatic generation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a test sequence automatic generation device including a test sequence compression unit.

FIG. 3 is a logic circuit diagram showing a combinational circuit that is an object of generation of a test sequence.

[Explanation of symbols]

101 Automatic Test Sequence Generation Unit (Pattern Generation Means) 102 Fault Simulator (Fault Simulation Execution Means) 103 Inspection Sequence Compression Unit (Test Sequence Compression Means) 104 Control Unit (Inspection Sequence Compression Processing Execution Means) 105 Buffer 106 Output Unit

Claims (5)

[Claims] 1. A pattern generating means for generating a first pattern, which is a set of values simultaneously set as an external input of the combinational circuit, which constitutes a test sequence for checking the presence or absence of a target fault in the combinational circuit. A fault simulation executing means for executing a fault simulation for checking whether or not a target fault in the combinational circuit can be detected using the first pattern; and the first pattern and the first pattern that can be detected. A pair of faults is input, and a test sequence compression process of deleting the first pattern from the test sequence or outputting the first pattern as a second pattern constituting a compressed test sequence is executed. When one pattern is output as the second pattern, the failure that can be detected by the second pattern is detected by the failure simulation execution procedure. Test pattern automatically generated apparatus characterized by and a test sequence compressing means for performing a fault deletion process of deleting from the fault to be a target in the fault simulation performed by. 2. The test sequence compression means, when outputting the first pattern as the second pattern, detects a failure that can be detected by the second pattern in a failure simulation executed by the failure simulation execution means. The fault deletion process is performed by deleting from the target fault and also deleting the fault detectable by the second pattern from the target fault in the generation of the first pattern executed by the pattern generation means. The test sequence automatic generation device according to claim 1, which is executed. 3. The check sequence compressing means stores a set of the first pattern and a fault detectable by the first pattern, and a buffer which can store the first pattern in the second pattern when a predetermined condition is satisfied. A first step of storing a set of the first pattern and a fault detectable by the first pattern in the buffer when the predetermined condition is not satisfied, while outputting the pattern as a pattern; and the first pattern in the buffer. And the first
When two or more sets of faults that can be detected by the pattern are stored, the fault that can be detected by the first pattern in the buffer is included in the faults that can be detected by the other first pattern in the buffer. It is checked whether or not there is a fault coverage relationship that is detected, and when there is a first pattern that covers all detectable faults in the buffer, it can be detected by the first pattern and the first pattern. A second step of deleting a pair with a specific fault from the buffer,
A third pattern which, when the buffer is full, selects a first pattern from the first patterns in the buffer and outputs the first pattern as the second pattern.
The test sequence automatic generation device according to claim 1, further comprising: a test sequence compression process executing unit that executes the test sequence compression process by performing the step of. 4. The check sequence compression processing execution means, when the number of faults detectable by the first pattern is n or more (where n is the number of all target faults in the combinational circuit). While outputting the first pattern as the second pattern (which is a natural number below), the first pattern and the first pattern detect if the number of faults detectable by the first pattern is less than n. 4. The first step is performed by storing a set of possible faults in the buffer.
Inspection sequence automatic generation device described in. 5. The check sequence compression processing execution means is configured to execute a first check in the buffer when the buffer is full.
From the patterns, the first pattern having the largest number of uncovered faults among the detectable faults is selected, and the first pattern is selected.
The test sequence automatic generation device according to claim 4, wherein the third step is executed by outputting a pattern as the second pattern.