JPS5455179A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPS5455179A
JPS5455179A JP12209577A JP12209577A JPS5455179A JP S5455179 A JPS5455179 A JP S5455179A JP 12209577 A JP12209577 A JP 12209577A JP 12209577 A JP12209577 A JP 12209577A JP S5455179 A JPS5455179 A JP S5455179A
Authority
JP
Japan
Prior art keywords
package
circuits
comparator
doubled
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12209577A
Other languages
Japanese (ja)
Inventor
Nobuo Wakatsuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12209577A priority Critical patent/JPS5455179A/en
Publication of JPS5455179A publication Critical patent/JPS5455179A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To facilitate self-testing of packages by providing doubled circuits and a comparator for the output of said circuits in the package and comparing the outputs of the doubled circuits for the same input. CONSTITUTION:The package is constituted by inputs 1, doubled circuits 2 and a comparator 3. The inputs 1 are simultaneously applied in the doubled circuits 2 and logical operations are carried out. Next, the results of the operations are compared in the comparator 3, by which the presence or absence of any fault in the package is detected. since the self-testing function is provided to the package in this way, testing of the package board mounting this may be made higher in speed.
JP12209577A 1977-10-11 1977-10-11 Integrated circuit package Pending JPS5455179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12209577A JPS5455179A (en) 1977-10-11 1977-10-11 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12209577A JPS5455179A (en) 1977-10-11 1977-10-11 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPS5455179A true JPS5455179A (en) 1979-05-02

Family

ID=14827519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12209577A Pending JPS5455179A (en) 1977-10-11 1977-10-11 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS5455179A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55155262A (en) * 1979-05-23 1980-12-03 Nippon Telegr & Teleph Corp <Ntt> Fault detection system
JPS61160071A (en) * 1985-01-09 1986-07-19 Sumitomo Electric Ind Ltd Self-diagnostic circuit of ic
JPS6392215A (en) * 1986-10-03 1988-04-22 富士電機株式会社 Abnormality indication system in digital protective relay
JPH01109274A (en) * 1987-10-22 1989-04-26 Nec Corp Single event evaluating circuit for gate array
JP2020165802A (en) * 2019-03-29 2020-10-08 株式会社エヌエスアイテクス Semiconductor device and method for testing semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55155262A (en) * 1979-05-23 1980-12-03 Nippon Telegr & Teleph Corp <Ntt> Fault detection system
JPS61160071A (en) * 1985-01-09 1986-07-19 Sumitomo Electric Ind Ltd Self-diagnostic circuit of ic
JPS6392215A (en) * 1986-10-03 1988-04-22 富士電機株式会社 Abnormality indication system in digital protective relay
JPH01109274A (en) * 1987-10-22 1989-04-26 Nec Corp Single event evaluating circuit for gate array
JP2020165802A (en) * 2019-03-29 2020-10-08 株式会社エヌエスアイテクス Semiconductor device and method for testing semiconductor device

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees