JP2004302731A - Information processor and method for trouble diagnosis - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform trouble diagnosis action for a multiprocessor system without requiring any special hardware for trouble diagnosis. <P>SOLUTION: A POST process task table for trouble diagnosis is loaded into a memory 5 and the CPU of one of a group of processors 1 performs tasks serially while referring to the task table. Further, a command format table is loaded into the memory 5, and the group of processors 1 updates and refers to the table serially to determine whether or not the execution of each task of the POST can be completed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus using a plurality of processors, and more particularly, to a PC server apparatus having a function of automatically recovering from a failure.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in order to improve the reliability of a PC server device, when a failure such as a hard disk device failure or a network failure occurs, a function of diagnosing the failure content and automatically recovering the failure (hereinafter referred to as POST (Power On Self Test)) ).
[0003]
When executing POST, the plurality of tasks are sequentially executed according to a task table held in the BIOS of the system. In a normal BIOS, the task number is output to a specific input / output port before the task is executed, to indicate to the outside which task is being executed. For example, by connecting a task number externally assigned to each task to an I / O port of an LED or the like, the content of the task can be determined from the blinking content of the LED. Thus, if the system hangs up, looking at the LEDs tells which task was hung during execution.
[0004]
Recent PC server BIOS uses a specific command called IPMI (Intelligent Management Platform) to notify a processor called BMC (Baseband Management Controller) of a task number. At the same time, the timer of the BMC is set (if it is not reset even after the set time has elapsed, it is rebooted). If the system hangs up during POST, the system is rebooted and the system is restored after the lapse of the set time. Since the BMC holds the task number at the time of reboot, this is recorded as log data.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H10-14387 (FIG. 1)
[0006]
[Problems to be solved by the invention]
As described above, the conventional fault diagnosis method always requires a dedicated processor such as a BMC. Some systems do not have a BMC. In this case, it is possible to reboot when the system hangs up, but the functions are limited, such as not being able to record which task number hung.
[0007]
Accordingly, an object of the present invention is to provide a PC server that can monitor a POST startup failure without having a specific processor such as a BMC.
[0008]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION In order to solve the above-described problems, the present invention provides, in an information processing apparatus having a plurality of processors, a first CPU that sequentially executes a plurality of failure diagnosis tasks, and a first CPU that executes the first tasks. A second CPU for monitoring the execution status of the task being executed, a content of the task to be sequentially executed, and a memory for loading monitoring data corresponding to the task, and the first CPU executes The monitoring data is updated for each task that is being performed, and the second CPU determines the presence or absence of a failure by referring to the monitoring data update status.
[0009]
According to the present invention, in order to solve the above-described problem, the monitoring data includes a task number for specifying the task processing content, a timeout value corresponding to the task number, and status data indicating a task execution status. And
[0010]
According to the present invention, in order to solve the above-described problem, the second CPU does not refer to the timeout value and update the status data within the time indicated by the timeout value by the first CPU. In this case, it is determined that a failure has occurred.
[0011]
According to another aspect of the present invention, there is provided a first CPU that sequentially executes a plurality of failure diagnosis tasks and a second CPU that monitors an execution status of the task being executed by the first CPU. In a failure diagnosis method for an information processing device having a CPU, a content of the task to be sequentially executed, and a memory for loading monitoring data corresponding to the task, the first CPU executes Every time, the monitoring data is updated, and the second CPU determines the presence or absence of a failure by referring to the update status of the monitoring data.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a system configuration of a PC server according to an embodiment of the present invention.
The PC server according to the present embodiment has a plurality of processor groups 1. The processor group 1 includes M CPUs CPU0 to m, the CPU0 is a BSP (Boot StrapProcessor) that executes a system startup process, and the CPU1 to the CPUm are APs (APs) that execute application programs after the system is started. Application Processor).
[0013]
The processor group 1 is connected to a north bridge 3 via a host bus 2, and a memory 5 connected via a memory bus 4 and various I / O device groups connected via a PCI bus 5 Operation control 6 is executed. A task table for POST processing as shown in FIG. 2 is loaded in the memory 5, and one CPU of the processor group 1 sequentially executes each task while referring to the task table.
[0014]
Further, a command format table as shown in FIG. 3 is loaded into the memory 5, and the processor group 1 sequentially updates and refers to this table to determine whether or not the execution of each task of POST is completed.
[0015]
The memory 5 is specifically a DIMM (Dual Inline Memory Module). The devices of the device group 6 include a hard disk device storing an application program, a ROM storing a BIOS program, and the like.
[0016]
The south bridge 7 is a bridge circuit for the processor group 1 to control the operation of other I / O devices connected via an ISA bus (not shown) or the SM bus 8.
Next, the contents of the task table of FIG. 2 will be described.
The task table is a list in which the processing contents are described for each task. After starting the system, the task table is sequentially executed from task 1 to diagnose a system failure state. For example, the first task 1 is a process of initializing the chipset, and if the initialization is completed normally, the process proceeds to the next task process.
[0017]
Then, when each task is performed without any problem, the BIOS is finally set up (task N-1), and the OS starts (task N), and the POST operation is completed.
[0018]
In this embodiment, the CPU 0 sequentially executes each task written in the task table. Then, the CPU 1 monitors whether or not the execution of the task processing of the CPU 0 is successful, using the command format of FIG.
[0019]
The command format shown in FIG. 3 is used for executing and monitoring the task processing. The contents of this command format will be described.
The command format is a command table list in which offset numbers, command sizes, and data fields are associated.
The offset number is used as a list number. The size is the data size of the data to be written in the data field. The data field is data that is updated for each task, and the number of the task being executed is written in offset 1. A time-out value is written in the offset 2 and is time information for detecting that the task execution has not been completed within a predetermined time when the CPU 0 executes each task. The time-out value differs for each task, and a time-out value corresponding to each task is written in units of 100 ms.
[0020]
The offset 3 is reference data for detecting whether or not the execution of the task has been completed. When the CPU 0 normally completes the task being executed, the bit 1 (1b) is written. On the other hand, when the task is being executed or when the execution of the task cannot be completed normally, bit 0 (0b) has been written. By monitoring the offset 3 by the CPU 1, it is possible to determine whether the current task has been completed or is still being executed. Then, the CPU 1 refers to the timeout value in which the offset 2 is written. If the data of the offset 3 is not updated within the time of the timeout value, the CPU 1 determines that this task has not been completed normally. A time-out action is executed as shown at offset 4 in FIG. 4 to execute the failure recovery processing. Specifically, it is one of No Action (maintaining operation stop without performing recovery processing), Hard Reset (forced reset), Power Down (shutdown processing), and Power Cycle (restart processing). The data is written into the command format loaded in the memory 5.
[0021]
As described above, the command format shown in FIG. 3 is sequentially updated for each task according to the write instruction from the CPU 0. That is, the tasks are sequentially executed from the task 1 to the CPU 0 in the task table shown in FIG. 2, and when the execution of one task is completed, the data is changed to data on the next task.
[0022]
The operation of the present embodiment in such a configuration will be described.
First, the BIOS read from the device group 6 performs the following processing at the same timing as when the first task number 1 shown in FIG. 2 is transmitted from the CPU 0 to a specific port.
[0023]
(1) Wake the CPU 1 (issue a wake interrupt to the CPU 1 to start driving).
(2) Notifying the CPU 1 of the task number (3) Notifying the CPU 1 of the timeout time.
((2) to (3) are executed by the CPU 1 referring to the command format written in the memory 5. The CPU 0 writes the command format shown in FIG. , CPU 1 executes an operation according to the command format).
[0024]
(4) Instruct the CPU 1 to start a timer, and the CPU 1 monitors the time related to the completion status of the task execution of the CPU 0.
In the operation (4), when the CPU 1 does not receive the stop or start / restart command within the time written in the offset 1 of the command format, the CPU 1 executes the time action processing shown in FIG. Further, the task number at the time of timeout is recorded in a nonvolatile memory such as a flash memory so that a failure analysis can be performed later.
[0025]
Then, the tasks subsequent to the task number 2 are sequentially executed. In this case, only the task number is notified as follows.
(5) Notify the CPU of the task number.
(6) Notify the CPU 1 of the timeout time.
(7) Instruct the CPU 1 to start the timer.
(The operations (5) to (7) are executed by the same specific operations as (2) to (4))
Then, the following processing is executed immediately before OS startup, which is the last task shown in FIG.
(8) Instruct CPU 1 to stop timer measurement.
(9) CPU1 shifts to HLT State (operation stop state).
As described above, when the operation of (9) is completed, it is determined that there is no failure, the OS is started, and the operation of the application program of the PC server is started.
As described above, according to the present embodiment, it is possible to execute a fault diagnosis operation in a multiprocessor system without requiring special hardware for fault diagnosis.
[0026]
【The invention's effect】
According to the present invention, a fault diagnosis operation can be performed in a multiprocessor system without requiring special hardware for fault diagnosis.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a system configuration of a PC server according to an embodiment of the present invention.
FIG. 2 is a diagram showing contents of a task table in the embodiment.
FIG. 3 is a diagram illustrating a command format during execution of a task according to the embodiment;
FIG. 4 is a diagram illustrating a command format indicating a recovery operation when a failure occurs in the embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Processor group, 2 ... Host bus, 3 ... North bridge, 4 ... Memory bus, 5 ... Memory, 6 ... Device group, 7 ... South bridge.

Claims (6)

In an information processing apparatus having a plurality of processors,
A first CPU for sequentially executing a plurality of tasks for fault diagnosis,
A second CPU for monitoring an execution status of a task executed by the first CPU;
The content of the task to be sequentially executed, and a memory for loading monitoring data corresponding to the task,
The first CPU updates monitoring data for each task being executed, and the second CPU determines the presence or absence of a failure by referring to the update status of the monitoring data. Information processing device. 2. The monitoring data according to claim 1, wherein the monitoring data includes a task number for specifying the task processing content, a timeout value according to the task number, and status data indicating a task execution status. Information processing device. The second CPU refers to the timeout value, and determines that a failure has occurred if the status data has not been updated by the first CPU within the time indicated by the timeout value. 3. The information processing apparatus according to claim 2, wherein A first CPU for sequentially executing a plurality of tasks for failure diagnosis, a second CPU for monitoring the execution status of the task being executed by the first CPU, and contents of the task to be sequentially executed And a failure diagnosis method in an information processing apparatus having a memory for loading monitoring data corresponding to the task,
The first CPU updates monitoring data for each task being executed, and the second CPU determines the presence or absence of a failure by referring to an update status of the monitoring data. Failure diagnosis method. The fault according to claim 4, wherein the monitoring data includes a task number for specifying the task content, a timeout value corresponding to the task number, and status data indicating a task execution status. Diagnostic method. The second CPU refers to the timeout value, and determines that a failure has occurred if the status data has not been updated by the first CPU within the time indicated by the timeout value. The fault diagnosis method according to claim 5, wherein

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