JP2015064633A - Information processing device, information processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device, information processing method, and program that can guarantee the flexibility of a process that is executed after resetting caused by hang-up.SOLUTION: An information processing device 1 includes: a storage unit 140 that stores a plurality of processes that are executed when hang-up occurs; and a processing unit 120 that performs a restart in response to the occurrence of hang-up during the execution of a predetermined inspection. The processing unit executes processing matching a predetermined condition out of a plurality of processes stored in the storage unit after the restart.

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

  If a hang-up occurs when the computer (software or program) is running (a situation where the running software or program stops running), restart the computer (reset) and restart the computer. There is a recovery function to try.

  When an hang-up occurs during initialization processing by POST (Power On Self Test), the information processing apparatus described in Patent Document 1 resets the information processing apparatus and operates normally. The process that could not be processed (the process in which the hang-up occurred) is stored. Then, when the information processing apparatus executes the process again after the reset, the information processing apparatus skips the stored process. This avoids repeatedly executing the process in which the hang-up occurred, and avoids a fixed failure in which the hang-up occurs again at the same point after the information processing apparatus is reset.

JP 2013-125533 A

  The information processing apparatus described in Patent Document 1 discloses skipping a hung-up process, but there is a problem that simply skipping the process lacks the flexibility of the process executed after reset. For example, the information processing apparatus described in Patent Document 1 has a low possibility of a fixed failure depending on the hang-up process, and may not need to skip the process. Will be skipped.

  An object of the present invention is to solve the above-described problems and to provide an information processing apparatus, an information processing method, and a program capable of ensuring the flexibility of processing executed after reset due to hang-up.

  The information processing apparatus according to the present invention includes a storage unit that stores a plurality of processes to be executed when a hang-up occurs, and a process that performs a restart in response to the occurrence of the hang-up when a predetermined inspection is executed And the processing means executes a process that matches a predetermined condition among the plurality of processes stored in the storage means after the restart.

  The information processing method of the present invention stores a plurality of processes executed when a hang-up occurs, performs a restart in response to the occurrence of the hang-up when a predetermined inspection is executed, and restarts the process. Later, a process that matches a predetermined condition among the plurality of previously stored processes is executed.

  The program of the present invention includes a process for storing a plurality of processes to be executed when a hang-up occurs, a process for restarting in response to the occurrence of the hang-up when executing a predetermined inspection, After the restart, the computer is caused to execute a process that executes a process that matches a predetermined condition among the plurality of previously stored processes.

  The present invention has an effect that in an information processing apparatus, an information processing method, and a program, the flexibility of processing executed after reset due to hang-up can be ensured.

It is a figure which shows the example of the information processing apparatus of the 1st Embodiment of this invention. It is a figure which shows the example of the information regarding the operation mode memorize | stored in the non-volatile memory in the 1st Embodiment of this invention. It is a flowchart which shows the operation example of BMC of the information processing apparatus in the 1st Embodiment of this invention. It is a figure which shows the example of the information processing apparatus in the 2nd Embodiment of this invention. It is a figure which shows the structural example of the non-volatile memory in the 2nd Embodiment of this invention. It is a figure which shows the information of the operation mode at the time of POST hang-up in the 2nd Embodiment of this invention. It is a figure which shows an example of the current POST Task table in the 2nd Embodiment of this invention. It is a figure which shows an example of the WDT (watch dog timer) timeout generation table in the 2nd Embodiment of this invention. It is a figure which shows the relationship between POST Task Code and Sub Task in the 2nd Embodiment of this invention. It is a flowchart which shows the operation example of the information processing apparatus (POST) in the 2nd Embodiment of this invention. It is a flowchart which shows the execution example of POST Task in the 2nd Embodiment of this invention. It is a flowchart which shows the detailed operation example of "POST hang-up operation | movement" in the 2nd Embodiment of this invention. It is a figure which shows an example of the information processing apparatus in the 3rd Embodiment of this invention.

<First Embodiment>
First, a first embodiment of the present invention will be described with reference to FIG. Note that the drawing reference numerals attached to FIG. 1 are appended to the respective elements for convenience as an example for facilitating understanding, and the outline description is not intended to be any limitation.

  FIG. 1 is a diagram illustrating an example of an information processing apparatus 1 according to the first embodiment of the present invention. As shown in FIG. 1, the information processing apparatus 1 according to the first exemplary embodiment of the present invention includes a device 11 and a BMC (Baseboard Management Controller) 12. The information processing apparatus 1 includes a BIOS (Basic Input / Output System) 13 and a nonvolatile memory 14. The device 11, BIOS 13, and nonvolatile memory 14 are connected to the BMC 12.

  The device 11 is one of main devices constituting the information processing apparatus 1, for example, a CPU (Central Processing Unit), a PCI (Peripheral Component Interconnect) device, a memory, or the like. One or more devices. The memory includes, for example, a semiconductor memory in addition to a disk memory such as a hard disk or an optical disk.

  The BMC 12 functions as a unit that executes device status monitoring and maintenance processing (hereinafter simply referred to as “maintenance processing”) such as sensor control of the information processing apparatus 1. In the first embodiment of the present invention, when a hang-up occurs during execution of a predetermined test in the information processing apparatus 1, the BMC 12 restarts after resetting, and refers to the nonvolatile memory 14. Among the plurality of processes stored there, a process that matches the condition is executed. The plurality of processes are, for example, “retry”, “degenerate”, “skip”, and “auto” operation modes. The operation mode and conditions will be described later.

  The BIOS 13 functions as a means for initializing various devices (for example, the CPU and memory of the device 11) after the information processing apparatus 1 is turned on and executing processing until control is passed to the OS (Operating System). .

  The nonvolatile memory 14 stores a process (an operation mode at the time of hang-up) that is executed when the information processing apparatus 1 hangs up. The nonvolatile memory 14 stores information related to the operation mode when the information processing apparatus 1 is hung up. The nonvolatile memory 14 can be accessed from both the BIOS 13 and the MBC.

  FIG. 2 shows information related to the operation mode when the information processing apparatus 1 is hung up, which is stored in the nonvolatile memory 14. As shown in FIG. 2, the operation modes at the time of hang-up are, for example, “retry”, “degeneration”, “skip”, and “auto”.

  “Retry” is an operation mode indicating that after a reset due to a hang-up, the process including the hang-up process is executed again.

  “Degeneration” means that when a hang-up occurs, the device 11 (for example, PCI device) that has been processed by POST (Power On Self Test) is stopped (that is, excluding the device 11). This is an operation mode indicating that the process is executed again.

  “Skip” is an operation mode indicating that, when a hang-up occurs, the processing that has been processed by POST is excluded and the processing is executed again.

  “Auto” means “retry” as described above for the first few times of hang-up, but “degenerate” is performed when hangs up multiple times at the same point, and still hangs up multiple times at the same point. Is an operation mode indicating that "skip" is performed. Information on these operation modes is stored in the nonvolatile memory 14 as instructions, program data, or flag data indicating each operation mode.

  FIG. 3 is a flowchart showing an operation example of the BMC 12 in the first embodiment of the present invention.

  The BMC 12 determines whether or not the first condition is satisfied when a hang-up occurs during execution of a predetermined inspection. Here, the predetermined inspection is, for example, a POST task. In the determination of the first condition, the BMC 12 performs a hang-up (POST hang-up, etc.) in a predetermined inspection when the operation is “retry” or “auto” and the number of times the watch hangs up at the same point (watchdog It is determined whether or not the time-out occurrence count in the timer (WDT) is less than a first predetermined number of times (S101).

  When the first condition is satisfied as a result of the determination (YES in S101), the CPU 13 is restarted after being reset by the instruction of the BIOS 13 or the BMC 12, and the operation mode is "retry". The BMC 12 includes the hang-up process. The process is executed again (Sub Task is executed) (S102). A Sub Task is one or more tasks that are performed in a test. On the other hand, as a result of the determination, the first condition is not satisfied, that is, the operation at the time of hang-up is not “retry” or “auto”, or the number of times of hang-up at the same point is equal to or more than the first predetermined number ( (No in S101), without resetting, the process proceeds to Step 103 (S103).

  If the determination result in step 101 (S101) is NO, the BMC 12 determines whether or not the second condition is satisfied. In other words, the BMC 12 has a “degenerate” or “auto” operation at the time of hang-up in a predetermined inspection, and the number of times of hang-up at the same point is greater than or equal to the first predetermined number of times and less than the second predetermined number of times. It is determined whether or not (S103).

  As a result of the determination, if the second condition is satisfied (YES in S103), after the CPU is reset by an instruction from the BMC 12 or the BIOS 13, the system is restarted to enter the “degenerate” operation mode (degenerate mode). With the device 11 (for example, PCI device) being executed stopped (that is, excluding the device), the process is executed again (Sub Task is executed) (S104). On the other hand, as a result of determination, the second condition is not satisfied, that is, the operation at the time of hang-up is not “degenerate” or “auto”, or the number of times of hang-up at the same point is equal to or greater than the second predetermined number of times. If so (NO in S103), the process does not reset, and the process proceeds to step 105 (S105).

  If the determination result in step 103 (S103) is NO, the BMC 12 determines whether or not the third condition is satisfied. That is, the BMC 12 determines whether the operation at the time of hang-up in a predetermined inspection is “skip” or “auto” and the number of times of hang-up at the same point is equal to or greater than the second number ( S105).

  As a result of the determination, if the third condition is satisfied (YES in S105), after the CPU is reset by an instruction from the BMC 12 or the BIOS 13, the system is restarted to enter the “skip” operation mode (skip mode), and the BMC 12 performs processing with POST. The process (Sub Task) is executed again with the process being executed being excluded (S106). On the other hand, as a result of the determination, if the third condition is not satisfied, that is, the operation at the time of the hang-up is not any operation mode stored in the nonvolatile memory 14 (NO in S105), the process is not reset. The process moves to step 107 (S107), an error is notified, and a notification that a hang-up has occurred is notified.

  In the above description, the first predetermined number of times <the second predetermined number of times <the third predetermined number of times.

  As described above, in the first embodiment of the present invention, when the hang-up occurs, the information processing apparatus 1 refers to the nonvolatile memory 14 and executes a process that matches a condition from among a plurality of processes. Therefore, the information processing apparatus 1 can ensure the flexibility of processing executed after reset due to hang-up.

<Second Embodiment>
FIG. 4 is a diagram illustrating an example of the information processing apparatus 1 according to the second embodiment of the present invention. As illustrated in FIG. 4, the information processing apparatus 1 according to the second exemplary embodiment of the present invention includes a CPU 110, a PCI device 111, a memory (for example, a hard disk) 112, a BMC 12, a BIOS 13, and a nonvolatile memory 14. , And BIOS Setup (BIOS setup) 15.

  Note that in the second embodiment of the present invention, the description of the same configuration as that of the first embodiment of the present invention is omitted.

  For example, the CPU 110 executes a program stored in the memory 112.

  For example, the PCI device 111 performs communication between the CPU 110 and peripheral devices.

  A memory (for example, hard disk) 112 is connected to the CPU 110, and direct reading and writing are controlled by the CPU 110.

  The BIOS 13 is connected to the CPU 112. The BIOS 13 is also connected to the nonvolatile memory 14.

  The BIOS Setup 15 functions as a means for relaying between the BMC 12 and the BIOS 13. The BIOS Setup 15 functions as means for notifying the BIOS 13 of a setting request from the BMC 12.

  FIG. 5 is a configuration example of the nonvolatile memory 14 in the second embodiment of the present invention. The non-volatile memory 14 includes a “POST hangup operation mode table”, a “current POST Task Code” table, a “Current Sub Task” table (current POST Task table), and a “WDT timeout occurrence table”. Including.

  The “POST hangup operation mode table” can be changed by the BIOS Setup 15 and the BMC 12, and indicates “Retry”, “Degenerate”, “Skip”, and “Auto” operation modes. The BMC 12 can select an operation at POST hang-up from a plurality of operation modes according to the table.

  FIG. 6 is a table (operation mode 141 at POST hang-up) showing information on the operation mode at POST hang-up in the second embodiment of the present invention.

  As shown in FIG. 6, the “retry” mode is an operation mode in which the same processing is tried again when POST hangs up.

  The “degeneration” mode is an operation mode in which a device (CPU 110, PCI device 111, or memory 112) that is processed by the POST Sub Task is disabled and processing is executed. Note that the Sub Task indicates a processing unit executed inside the POST Task Code.

  “Skip” is an operation mode for skipping processing in the POST Sub Task.

  “Auto” is an operation mode in which “retry” processing is performed a predetermined number of times after the first POST hang-up occurs, and “degeneration” processing is performed when POST hang-up is performed several times at the same point without recovery. Further, if the post hangs up several times at the same point without recovery, the BMC 12 performs “skip” processing in the “auto” operation mode.

  In the “degenerate” and “skip” modes, the BIOS 13 needs to create an operation at the time of degeneration and skip for each POST Sub Task and store it in the nonvolatile memory 14 in order to execute the operation. is there. For example, the BIOS 13 stores the following operation settings (1) to (4) in the nonvolatile memory 14 in advance. (1) When performing “degeneration” of the CPU 110, all but the CPU 110 that operates POST are stopped. (2) If the memory is “degeneration”, the minimum memory is initialized. (3) “ If it is “degeneration”, PCI Root Port is stopped. (4) In the case of skip, the degeneration operation itself is not performed, but in the case of a basic process that cannot be skipped in the process, it is equivalent to the degeneration operation. Requests for setting these operations are made from the BMC 13 via the BIOS Setup 15.

  FIG. 7 shows the details of the “current POST Task Code”, “Current Sub Task”, and “identifier of executing device” table (current POST Task table 142) according to the second embodiment of the present invention.

  The “Current POST Task Code” and “Current Sub Task” tables include the current POST Task Code (executed when a hang-up occurs) (eg, POST Task Code 200) and the current Sub Task (eg, Sub Task 202). ) And the identifier of the executing device (e.g., PCI Device identifier: AAA).

  FIG. 8 shows details of the “WDT timeout occurrence table” table (WDT timeout occurrence table 143) in the second embodiment of the present invention.

  The “WDT timeout occurrence table” includes “POST Task Code”, “Sub Task”, and “WDT timeout count”.

  “POST Task Code” records the POST Task Code when a WDT timeout occurs.

  “Sub Task” indicates a POST Sub Task when a WDT timeout occurs.

  The “count number of WDT timeout” indicates the count number (number of times) of the WDT timeout that has occurred in the Sub Task.

  FIG. 9 is a diagram illustrating the relationship between the POST Task Code and the POST Sub Task. First, POST Task Code indicates the processing content (rough processing content) to be performed in the Task Code. For example, POST Task Code 100 indicates initialization of CPU 110 (CPU 1 and CPU 2), and POST Task Code 200 indicates initialization of PCI device (device) and USB device.

  The Sub Task is a number assigned so that the processing can be uniquely determined within each POST Task. For example, in POST Task Code 200, PCI Device initialization is numbered 201, and USB Device initialization (not shown in FIG. 4) is numbered 202. Here, when a POST hang-up occurs in the USB device and a WDT timeout occurs, the POST Task Code 200 and the POST Sub Task 202 are recorded in the WDT timeout occurrence table, and the count number of the WDT timeout is set to “1”. If the same POST Task Code and POST Sub Task already exist in the table, the WDT timeout count is incremented by “+1”.

  FIG. 10 is a flowchart showing the operation flow of POST in the second embodiment of the present invention. Note that the flow of FIG. 10 may be executed by the BMC 12 instructing the BIOS 13 via the BIOS Setup 15.

  First, the BMC 12 starts WDT at the point of POST Start when the power is turned on (S201). WDT is executed by the CPU.

  Next, the BMC 12 stores the current POST Task Code in the “current POST Task Code” (see FIG. 7) of the nonvolatile memory 14 (S202). Thereafter, the BMC 12 executes the current POST Task (predetermined device inspection) (S203). The execution of “POST Task”, which is the predetermined inspection, will be described later with reference to FIG.

  If a WDT timeout occurs during execution of the current POST Task (YES in S204), the BMC 12 changes the “Current POST Task Code” and the “Current Sub Task” stored in the nonvolatile memory 14 to the “WDT timeout”. It is recorded in the POST Task Code and POSTSub Task of the “generation table” (see FIG. 9). If the same POST Task Code and Sub Task have already been recorded, the WDT timeout count is incremented by “+1” (S205). Thereafter, Reboot (reboot process) is executed in accordance with an instruction from the BMC 12 (S206).

  On the other hand, if the WDT timeout does not occur and the POST Task process ends (NO in S204), the BMC 12 determines whether there is a next POST Task, and if there is, the process proceeds to the process (YES in S207). S208). On the other hand, if there is no remaining POST Task (NO in S207), the POST process ends, the BMC 12 stops the WDT (S210), and becomes OS Boot (S210).

  FIG. 11 is a flowchart showing the execution of the POST Task in FIG.

  First, the BMC 12 stores the current Sub Task in the “Current Sub Task” table (see FIG. 7) of the nonvolatile memory 14 (S301).

  Next, the BMC 12 proceeds to the next check when there is a POST Task Code that matches the current POST Task in the “WDT timeout occurrence table” (see FIG. 9) (YES in S302).

  If the current Sub Task matches the Sub Task stored in the “WDT timeout occurrence table” (YES in S303), the BMC 12 proceeds to “POST hang-up operation” (S304). This POST hang-up operation will be described later with reference to FIG.

  If the current POST Task Code and Sub Task are not in the “WDT timeout occurrence table” (NO in S302 and NO in S303), the BMC 12 executes the Sub Task of the current POST Task (S305). This process is executed for all the Sub Tasks in the current POST Task (S306 and S307).

  FIG. 12 is a diagram showing details of the “POST hang-up operation” in FIG. This process corresponds to the operation of the flow shown in FIG. 3 described in the first embodiment. When this process is entered, a WDT timeout has already occurred at least once in the combination of this POST Task Code and Sub Task.

  First, the BMC 12 refers to the value of “operation at POST hang-up” stored in the nonvolatile memory 14. If this value is set to “Retry” or “Auto”, and “WDT timeout count” is less than n times (n is an arbitrary number) (YES in S401), the BMC 12 executes Sub Task. (S402) Try to cancel the POST hang-up operation by executing the same process again. On the other hand, if n times or more (NO in S401), the process in the BMC 12 proceeds to step 403 (S403).

  If the value of “POST hang-up operation” is “degenerate” or “auto” and the “number of WDT timeout count” is n or more and less than m (m is an arbitrary number) (YES in S403), the BMC 12 The sub task is executed in the mode (S404). On the other hand, if m times or more (NO in S403), the process in the BMC 12 proceeds to step 405 (S405).

  This degenerate mode needs to be created in advance by the BIOS 13 so that the degenerate mode operation is performed in each Sub Task code. For example, if the process is performed by the CPU 110, the BIOS 13 stops the CPU 110. In the case of the PCI device 111, the BIOS 13 stops the PCI root bridge (disabled).

  If the value of “POST Hang-up” is “Skip” or “Auto” and “WDT timeout count” is greater than or equal to m (YES in S405), the BMC 12 executes the Sub Task in the skip mode ( S406). The skip mode is an operation mode in which the degeneration processing in the Sub Task is not performed, and the processing is exited without performing anything on the device (CPU 110, PCI device 111, memory (for example, hard disk) 112).

  If the “operation during POST hang-up” is not any of “retry”, “degenerate”, and “skip” (NO in S405), the BMC 12 displays an error and generates a POST hang-up (S407). In these series of processes, the BIOS 13 needs to be built in advance so as to operate in all the Sub Tasks in both the reduced mode and the skip mode.

  Hereinafter, specific processing in the information processing apparatus 1 according to the second embodiment of the present invention will be described with reference to FIGS. 10 to 12. The specific example to be described is that a POST hang-up occurs in the initialization of the USB device (not shown) indicated by the POST Sub Task 202 in the initialization of the PCI device indicated by the POST Task Code 200 (see FIG. 9). This is an example.

  First, as shown in FIG. 10, at the POST Start, the BMC 12 starts WDT (S201), and stores the current POST Task Code 200 in “Current POST Task Code” of the nonvolatile memory 14 (S202). Thereafter, the BMC 12 executes POST Task (S203).

  The POST Task execution is shown in FIG. 11. First, the BMC 12 stores the current Sub Task in the “Sub Task” of the nonvolatile memory 14 (S301). Here, it is assumed that the process starts from the Sub Task 201. First, the Sub Task 201 is saved.

  Next, since the POST Task Code and the POST Task in the “WDT timeout occurrence table” are not yet stored (NO in S302), the BMC 12 executes the Sub Task (S305).

  Next, since there is still a sub task in the branch check whether or not the sub task is completed (NO in S306), the BMC 12 proceeds to the next sub task (S307). Returning to the beginning of the processing, the BMC 12 stores 202 in the “current sub task” of the nonvolatile memory 14. Since the POST Task Code of the “WDT timeout occurrence table” does not yet contain the POST Task Code (NO in S302), the Sub Task is executed (S305).

  Here, a POST hang-up occurs and a WDT timeout occurs (S204 no YES).

  If a WDT timeout has occurred, the BMC 12 proceeds to a process for generating a WDT timeout, which is a branch after the POST Task in FIG. 10 (S205). In other words, the BMC 12 takes out the value “200” that is the “current POST Task Code” stored in the nonvolatile memory 14 and the value 202 that is the “current Sub Task Code”, and stores the values in the nonvolatile memory 14. Record in the WDT timeout occurrence table (S205). The BMC 12 sets the WDT timeout count to “1” and performs the Reboot operation (S206).

  In the operation after Reboot, the process returns to the POST start, starts WDT (S201), and the BMC 12 stores the current POST Task Code in the “current POST Task Code” of the nonvolatile memory 14 (S202).

  Here, the case where the hang-up is performed again with the POST Task Code 200 and the Sub Task 202 will be described. The BMC 12 stores the POST Task Code 200 in the “current POST Task Code” of the nonvolatile memory 14 and executes the POST Task (S203).

  In the POST Task execution of FIG. 10, the BMC 12 stores the current Sub Task in the “Current Sub Task” of the nonvolatile memory 14 (S301). First, the Sub Task 201 is saved. Subsequently, in the WDT timeout occurrence table, if the POST Task Code matches but the Sub Task does not match (NO in S302), the BMC 12 executes the Sub Task 201 (S305).

  In the subsequent process, the Sub Task 202 is processed (S307).

  The BMC 12 checks the “WDT timeout occurrence table” and moves to the next check because there is one that matches the current POST Task Code 200 (YES in S302). Next, since the current Sub Task 202 and the Sub Task 202 are shown in the “WDT timeout occurrence table” (YES in S303), the process in the BMC shifts to the POST hang-up process shown in FIG. (S304).

  In the processing of the POST hang-up operation illustrated in FIG. 12, the BMC 12 checks the value of “operation during POST hang-up” in the nonvolatile memory 14. If this value is “retry” (YES in S401), the BMC 12 executes the Sub Task 202 once again without doing anything (S402).

  If it is “degenerate” (YES in S403), the BMC 12 stops the PCI Root Device corresponding to the Sub Task 202 (S404). This degeneration operation is different for each POST Task Code and Sub Task, and it is necessary to create the BIOS 13 in advance so that the POST Task passes through the degeneration operation.

  If it is “skip” (YES in S405), the BMC 12 does not process the Sub Task 202, and exits the process as it is. Also in this case, the BIOS 13 needs to be created in advance so that the POST Task can be passed through the skip operation.

  In the case of “auto”, the BMC 12 checks the value of the “count number of WDT timeout”, and executes the Sub Task as it is (YES in S401), executes in the reduced mode (YES in S403), and executes in the skip mode (S405). YES).

  As described above, also in the second embodiment of the present invention, when the hang-up occurs, the information processing apparatus 1 refers to the nonvolatile memory 14 and executes a process that matches a condition from among a plurality of processes. Therefore, the information processing apparatus 1 can ensure the flexibility of processing executed after reset due to hang-up.

<About BMC>
In the first embodiment and the second embodiment of the present invention, the BMC 12 may be a computer. That is, the BMC 12 includes a CPU (Central Processing Unit) or an MPU (Micro-Processing Unit) and a memory, and executes software (a program stored in the memory) that realizes the functions of the above-described embodiments. In each embodiment, the apparatus that executes the software (program) is not limited to the information processing apparatus 1 illustrated in FIGS. 1 and 4 and may be any apparatus.

  In the first and second embodiments of the present invention, the information processing apparatus 1 is configured by the above-described embodiments from an external interface (not shown) via various storage media such as a CD-R (Compact Disc Recordable) or a network. Software (program) for realizing the function may be acquired. The software (program) may be stored in advance in, for example, a predetermined storage unit included in the information processing apparatus 1.

  The computer, CPU, MPU, or the like of the information processing apparatus 1 reads out and executes the acquired program code of software (program). Therefore, the same process as the process of the information processing apparatus 1 in each embodiment described above is executed.

According to the first and second embodiments of the present invention, the present invention can also be applied to applications such as a program to be implemented in a computer, a CPU, an MPU, or the like of the information processing apparatus 1.
<Third Embodiment>
A third embodiment of the present invention will be described with reference to the drawings. Note that in the third embodiment of the present invention, the description of the same configuration as each of the above embodiments is omitted.

  FIG. 13 shows the information processing apparatus 1 according to the third embodiment of the present invention. As illustrated in FIG. 13, the information processing apparatus 1 of the present invention includes a storage unit 140 and a processing unit 120.

  The storage unit 140 stores a plurality of processes that are executed when a hang-up occurs.

  The processing unit 120 restarts in response to the occurrence of a hang-up when executing a predetermined test including one or more tasks. In the third embodiment of the present invention, the processing unit 120 executes a process that matches a predetermined condition among a plurality of processes stored in the storage unit 140 after the restart.

  As described above, in the third embodiment of the present invention, the information processing apparatus 1 executes a process that matches a predetermined condition among a plurality of processes stored in the storage unit 140 after restart when a hang-up occurs. The processing unit 120 is provided. Therefore, the information processing apparatus 1 can ensure the flexibility of processing executed after reset due to hang-up.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to each above-mentioned embodiment. The present invention can be implemented based on modifications, substitutions, and adjustments of the embodiments. The present invention can also be implemented by arbitrarily combining the embodiments. That is, the present invention includes various modifications and corrections that can be realized in accordance with all the disclosed contents and technical ideas of the present specification.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

[Appendix 1]
Storage means for storing a plurality of processes executed due to the occurrence of the hang-up,
Processing means for restarting in response to the occurrence of the hang-up when executing a predetermined inspection including one or more tasks,
The information processing apparatus, wherein the processing unit executes a process that matches a predetermined condition among the plurality of processes stored in the storage unit after the restart.

[Appendix 2]
The information processing apparatus according to appendix 1, wherein the processing unit executes a process determined according to the number of times of the hang-up among the plurality of processes.

[Appendix 3]
The storage means further stores the number of hangs during execution of the task in the predetermined inspection,
The plurality of processes are:
If the number of times of hang-up is less than a first predetermined number of times, a first process for re-execution of the task in the predetermined inspection after restarting,
If the number of times of the hang-up is equal to or more than the first predetermined number of times and less than the second predetermined number of times, after restarting, the predetermined device is stopped and the task in the predetermined inspection is executed. processing,
If the number of times of the hang-up is equal to or more than a second predetermined number of times, a third process of skipping a specific task among the tasks in the stored predetermined inspection after restarting 2. The information processing apparatus according to 2.

[Appendix 4]
The information processing apparatus according to any one of appendices 1 to 3, wherein the storage unit stores a task in the predetermined inspection when the hang-up occurs.

[Appendix 5]
The third process according to any one of appendices 1 to 4, including skipping the hang-up task stored in the storage unit among the tasks in the predetermined inspection after the restart. The information processing apparatus described in 1.

[Appendix 6]
A device on which a task in the predetermined inspection is performed,
The information processing apparatus according to any one of appendices 1 to 5, wherein the storage unit further stores an identifier of a device that has executed the predetermined inspection item when the hang-up has occurred.

[Appendix 7]
The information processing apparatus according to appendix 6, wherein the plurality of processes include stopping a device corresponding to the stored identifier and executing the stored predetermined examination item after restarting.

[Appendix 8]
Remembers multiple actions that occur due to the hangup,
Reboot in response to the occurrence of the hang-up when performing a predetermined test that includes one or more tasks,
An information processing method for executing a process that matches a predetermined condition among the plurality of stored processes after the restart.

[Appendix 9]
The information processing method according to appendix 8, wherein a determined process is executed according to the number of times of the hang-up among the plurality of processes.

[Appendix 10]
Further storing the number of hangs during execution of the task in the predetermined inspection;
If the number of times of hang-up is less than the first predetermined number of times, after restarting, the task in the predetermined inspection is re-executed,
If the number of times of hang-up is greater than or equal to the first predetermined number of times and less than the second predetermined number of times, after rebooting, the predetermined device is stopped and the task in the predetermined inspection is executed,
If the number of times of the hang-up is equal to or more than a second predetermined number of times, the method further includes skipping a specific task of the stored tasks in the predetermined inspection after restarting. Information processing method.

[Appendix 11]
The information processing method according to any one of appendices 8 to 10, wherein a task in the predetermined inspection when the hang-up occurs is stored.

[Appendix 12]
The third process according to any one of appendices 8 to 11, including skipping the hang-up task stored in the storage unit among the tasks in the predetermined inspection after the restart. Information processing method described in 1.

[Appendix 13]
The information processing apparatus according to any one of appendices 8 to 12, further storing an identifier of a device that has executed the predetermined inspection item when the hang-up has occurred.

[Appendix 14]
14. The information processing method according to appendix 13, wherein the plurality of processes include stopping the device corresponding to the stored identifier and executing the stored predetermined examination item after restarting.

[Appendix 15]
A process for storing multiple processes executed due to the occurrence of a hang-up,
Processing to restart in response to the occurrence of the hang-up when executing a predetermined inspection including one or more tasks;
A program that causes a computer to execute a process that matches a predetermined condition among the plurality of stored processes after the restart.

[Appendix 16]
The program according to supplementary note 15, including a process of executing a process determined according to the number of times of the hang-up among the plurality of processes.

[Appendix 17]
Processing for further storing the number of times of hang-up during execution of the task in the predetermined inspection;
If the number of times of hang-up is less than the first predetermined number of times, a process of re-executing the task in the predetermined inspection after restarting;
If the number of times of hang-up is greater than or equal to the first predetermined number of times and less than the second predetermined number of times, after rebooting, a process of stopping the predetermined device and executing the task in the predetermined inspection;
If the number of times of the hang-up is equal to or greater than the second predetermined number of times, a process of skipping a specific task among the stored tasks in the predetermined inspection after restarting The listed program.

[Appendix 18]
18. The program according to any one of appendices 15 to 17, including a process of storing a task in the predetermined inspection when the hang-up occurs.

[Appendix 19]
The third process includes any one of appendices 15 to 18 including a process of skipping the task at the time of the hang-up stored in the storage unit among the tasks in the predetermined inspection after the restart. The program described in.

[Appendix 20]
The program according to any one of supplementary notes 15 to 19, further comprising a process of storing an identifier of a device that has executed the predetermined inspection item when the hang-up has occurred.

[Appendix 21]
The program according to appendix 19, wherein the plurality of processes include a process of stopping a device corresponding to the stored identifier and executing the stored predetermined examination item after restarting.

1 Information processing device 11 Device 12 BMC
13 BIOS
14 Nonvolatile memory 15 BIOS Setup
110 CPU
111 PCI device 112 Memory (eg, hard disk)
120 processing unit 140 storage unit 141 operation mode at POST hang-up 142 current POST Task
143 WDT timeout occurrence table

Claims (10)

Storage means for storing a plurality of processes executed due to the occurrence of the hang-up,
Processing means for restarting in response to the occurrence of the hang-up when executing a predetermined inspection including one or more tasks,
The information processing apparatus, wherein the processing unit executes a process that matches a predetermined condition among the plurality of processes stored in the storage unit after the restart.   The information processing apparatus according to claim 1, wherein the processing unit executes a process determined according to the number of times of the hang-up among the plurality of processes. The storage means further stores the number of hangs during execution of the task in the predetermined inspection,
The plurality of processes are:
If the number of times of hang-up is less than a first predetermined number of times, a first process for re-execution of the task in the predetermined inspection after restarting,
If the number of times of the hang-up is equal to or more than the first predetermined number of times and less than the second predetermined number of times, after restarting, the predetermined device is stopped and the task in the predetermined inspection is executed. processing,
3. A third process for skipping a specific task among the tasks in the stored predetermined test after the restart if the number of times of hang-up is equal to or greater than a second predetermined number of times. Or the information processing apparatus of 2.   The information processing apparatus according to claim 1, wherein the storage unit stores a task in the predetermined inspection when the hang-up occurs.   The said 3rd process includes skipping the task at the time of the said hang-up memorize | stored in the said memory | storage means among the tasks in the said predetermined | prescribed test | inspection after restart. The information processing apparatus according to item. A device on which a task in the predetermined inspection is performed,
The information processing apparatus according to claim 1, wherein the storage unit further stores an identifier of a device that has executed the predetermined inspection item when the hang-up has occurred.   The information processing apparatus according to claim 6, wherein the plurality of processes include, after restarting, stopping a device corresponding to the stored identifier and executing the stored predetermined examination item. Remembers multiple actions that occur due to the hangup,
Reboot in response to the occurrence of the hang-up when performing a predetermined test that includes one or more tasks,
An information processing method for executing a process that matches a predetermined condition among the plurality of stored processes after the restart.   The information processing method according to claim 8, wherein the determined process is executed according to the number of times of the hang-up among the plurality of processes. A process for storing multiple processes executed due to the occurrence of a hang-up,
Processing to restart in response to the occurrence of the hang-up when executing a predetermined inspection including one or more tasks;
A program that causes a computer to execute a process that matches a predetermined condition among the plurality of stored processes after the restart.