JPS6031643A - Storage circuit of state history - Google Patents

Abstract

PURPOSE:To prevent the registration of redundant information by controlling registration while comparing a set address with a microinstruction word address. CONSTITUTION:A suppressing address comparator 16 and a restart address comparator 18 compare the contents of a suppressing address register 15 and a restart address register 17 with an address designated by a microinstruction word reading address circuit 11 respectively. If the comparator 16 detects the coincidence, the detecting signal designates a control circuit 40 to suppress the registration in a tracer 20. If the comparator 18 detects the coincidence, the detecting signal designates the control circuit 40 to restart the registration in the tracer 20. Therefore, the registration of redundant information can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a state history storage circuit that stores a history of internal states point by point for tracing the operation of an information processing device.

[Description of prior art]

Conventionally, this type of state history storage circuit is provided inside an information processing device 1, as shown in FIG.

The state history circuit includes an instruction execution control circuit 10, a state history storage device 20, an internal state information register 32, an address register 30 for state history storage device (hereinafter abbreviated as address register), and an address counter 31. The contents stored in the internal state information recorder 32 outputted from the instruction execution control circuit 10 at various timings (for example, firmware steps) are output to the state history storage device 20. The storage address in the state history storage device 20 at this time is given by the address register 30. Every time the contents of the internal status information register 32 are stored in the status history storage device 20, the contents of the address register 30 are changed to
The counter 31 is updated and set to indicate the next address stored immediately before. According to the contents of this address register 30, the internal state is determined by the state history storage device 20.
The data is stored sequentially starting from the lowest address.

By storing the internal state information in the state history storage device 20 in this way, when a failure occurs, the state history storage device 20
The internal state information stored in 0 is extracted and used as a countermeasure for troubleshooting. However, state history storage device 2
0 is the state history storage device 20 because the storage capacity is limited.
After storing the internal state information up to the highest address, the address register 30 again points to the lowest address of the state history storage device 20, and when the state information is further stored at the lowest address, the address register 30 returns to the counter. 31 points to the next address. Therefore, the internal state information stored in the state history storage device 20 is
The data will be rewritten sequentially starting from the lowest address. Therefore, in the operation trace in which the internal state of each step of the firmware instruction is stored in the state history storage device 20 one by one.

When the same firmware step loop is executed many times while waiting for the next command, the step information of the firmware is stored, and when a failure occurs, this redundant information is included.

This had the drawback of missing more useful information.

[Detailed description of the invention]

An object of the present invention is to provide a first storage means (state history storage device) for registering micro-instruction word addresses that control an information processing device one by one, and a second storage means for inhibiting registration of the micro-instruction word addresses. If the address matches the address set in the storage means, registration in the first storage means is suppressed, and the microinstruction word address is set as a third unique means for restarting registration. and a control means that restarts registration in the first storage means when the address matches), thereby preventing redundant information from being registered in the first storage means. Another object of the present invention is to provide a state history storage circuit that can make more effective use of the limited first storage means.

[Structure of the invention]

According to the present invention, in a state history storage circuit that stores a history of the state of an information processing device that is controlled by microinstructions, addresses of microinstructions controlling the information processing device are registered one by one. a first storage means; a second storage means capable of presetting an address for inhibiting registration in the first storage means; an address stored in the second storage means; and a control unit for controlling the information processing device. an inhibition address comparison means for comparing the address of the microinstruction word that is being executed; a third storage means capable of presetting a registration@restart address in the first storage means; restart address comparison means for comparing the stored address with the address of the microinstruction word controlling the information processing device; There is obtained a state history storage circuit characterized in that it has a control means for controlling whether or not to register the address of a microinstruction word in the storage means.

[Detailed description of the invention]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 2, a state history storage circuit according to an embodiment of the present invention stores the address of a microinstruction word in an information processing apparatus that is controlled by the microinstruction word. The state history storage circuit according to this embodiment is provided in an information processing device. The state history storage circuit according to this embodiment is as follows.

A microinstruction word memory (hereinafter abbreviated as C8M) 12 in which microinstruction words are stored, and the C8M 12
It's within. A micro-instruction all-word read address circuit (hereinafter abbreviated as address circuit) 11 that instructs the address for reading out the micro-instruction word at a certain address, and a state history that sequentially stores the addresses indicated by the address circuit 11. A storage device (hereinafter abbreviated as a tracer) 20, an address register 30 indicating the address to be stored in the tracer 20, and the contents from the address circuit 11 (the address circuit of the C8M 12) are stored in the tracer 2o. An address counter (hereinafter abbreviated as counter) updates the contents of the address register 30 each time it is stored.

)31.

This embodiment further includes an inhibition address register that can set an address at which storage inhibition is to be started in the tracer 2o when storing the contents from the address circuit 11 (which is the address of the C8M 12) in the tracer 2o. (hereinafter abbreviated as an inhibition register) 15, a restart address register (hereinafter abbreviated as a restart register) 17, which can similarly set a cell address for restarting storage in the tracer 2o, and a content from the address circuit 11 (hereinafter referred to as a restart register). C3M12 address) and the contents of the inhibition register 15 (hereinafter abbreviated as inhibition comparison circuit).

) 16 and the contents from the address circuit 11 (the C8
A restart address comparison circuit (hereinafter abbreviated as the restart comparison circuit) 18 compares the contents of the restart register 17 (address of M 12) with the contents of the restart register 17, receives a match signal from the inhibition comparison circuit 16 and the restart comparison circuit 18, and compares the contents of the restart register 17. A control circuit 40 that controls each input of the tracer 20 and the address register 30;
0 and input darts 41 and 42 that suppress and release the input of the address register 30.

The operation will be explained below.

A microinstruction word is read out from the C8M 12 according to the microinstruction address indicated by the address circuit 11, and the information processing device performs processing according to the microinstruction word. This micro-instruction word specifies the micro-instruction address from which the next micro-instruction word should be read. This microinstruction word address is taken into the address circuit 11 and instructed to the C8M 12 as the next step microinstruction word address. In this way, the microinstruction word addresses indicated by the address circuit 11 are registered one after another at the positions indicated by the address register 30 of the tracer 20.

Further, the inhibition comparison circuit 16 and the restart comparison circuit 18 constantly compare the contents of the inhibition register 15 and the restart register 17 with the address specified by the address circuit 11. now.

The explanation will be continued assuming that address A is temporarily set in the inhibition register 15 and address B is temporarily set in the restart register 17.

When the microinstruction word address specified by the address circuit 11 is A, the inhibition comparison circuit 16 detects a match and baldness. This detection signal instructs the control circuit 40 to suppress registration for the tracer 20. The control circuit 4 that received this input all the above inputs) 41.42
Instruct to suppress registration. Upon receiving this, all the input groups 41 and 42 are closed to save the contents of the tracer 20 and the address register 30, and registration is inhibited.

On the other hand, the address circuit 11 instructs new addresses one after another, the microinstruction word is read out from the C3M 12, and processing is performed. Here, when the microinstruction word address specified by the address circuit 1 becomes B, the restart comparison circuit 18 detects a match. This detection signal instructs the control circuit 40 to restart registration of the tracer 20. Upon receiving this, the control circuit 40 controls all the input ports 41.
Instruct ゜42 to restart registration. This causes all input darts 41, 42 to open their gates to update the contents of the tracer 20 and address register 30, and registration is resumed.

In this way, by setting the entry and exit addresses of the known microinstruction word routine in the inhibition register 15 and the restart register 17, the tracer 2
0 does not require registering a known microinstruction routine, and it becomes possible to prevent redundant information from being registered in the tracer 20.

Incidentally, by using sesotoassociate memory for the inhibition register 15 and the restart register 17, it is also possible to set a plurality of inhibition addresses and restart addresses.

[Detailed description of the invention]

As explained above, in the present invention, data is stored in the state history storage device (first storage device) while comparing the address set in the inhibition address register and the restart address register with the microinstruction word address.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional state history storage circuit. FIG. 2 is a block diagram of a state history storage circuit according to an embodiment of the present invention. ■... Information processing device, 10... Instruction execution control circuit. 11...Microinstruction word read address circuit.

Claims (1)

[Claims] 1. In a state history storage circuit that stores the state history of an information processing device controlled by microinstruction words,
a first storage means for registering addresses of microinstructions controlling the information processing device one by one; a second storage means for presetting addresses for inhibiting registration in the first storage means; an address stored in the second storage means; a third storage means capable of setting a microinstruction word controlling the information processing device; an address stored in the third storage means; restart address comparison means for comparing the address of a microinstruction word controlling the information processing device; and a microinstruction to the first storage means in response to output signals of the inhibition address comparison means and the restart address comparison means. 1. A state history storage circuit comprising: control means for controlling whether or not to register a word address.