JPS62272331A - Tracer system - Google Patents

Abstract

PURPOSE:To keep back data before the occurrence of a trouble in a memory even in case of the trouble detected by a timer by stopping the write to the memory when the number of times of coincidence between current and preceding micro instruction addresses exceeds a specific value in case of continuity of the same micro instruction address. CONSTITUTION:The micro instruction address inputted to a memory 1 and that held in a data register 2 are compared with each other by a comparing circuit 3, and a coincidence signal is outputted when they coincide with each other. A counting circuit 4 counts the number of times of coincidence signal output from the comparing circuit 3 up to the specific value, and the circuit 4 outputs a carry signal when the counted value exceeds this specific value. A detecting circuit 5 detects it by the carry signal that the counting circuit 4 continues counting beyond the specific value, and the circuit 5 outputs the output to a control circuit 8. The control circuit 8 stops update of a write address counter of an address counter circuit 7 and write instruction to the memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Technical Field The present invention relates to a tracer method, and more particularly to a tracer method for storing a fat layer of an internal state of an information processing device.

Prior Art Conventionally, in this type of tracer method, a tracer circuit composed of a memory, an address circuit, and a control circuit constantly writes data indicating the internal state of an information processing device to the memory while changing the write address. There is. When data is written to all words of this memory, the write address is returned to the initial address and is written over the previously written word.

This operation continues until the information processing device detects a failure. When a fault is detected, the tracer circuit stops updating the write address and writing to the memory via the control circuit,
Data indicating the internal state of the information processing VR device is stored in the memory with the maximum number of words in the memory going back from the failure detection.

In such conventional tracer methods, data continues to be written to memory until a failure in the information processing device is detected.
Among the failures of the information processing apparatus, there are failures in which the state within the information processing apparatus remains constant and does not progress, and in the case of this failure, writing to the memory continues without stopping. For this reason, a failure is determined only after a timer is used to detect that the state within the information processing device remains unchanged for a certain period of time. The detection period using a timer is generally longer than the period for writing data to all words in the tracer circuit's memory, so if such a fault is detected, only the same data remains in the tracer circuit's memory. However, there is a drawback that there is no data remaining on the internal state of the information processing device prior to the occurrence of this fault, which would be useful for elucidating the cause of this fault.

-Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and even in the case of a failure detected by a timer, data from before the occurrence of this failure can be retained in the memory. The purpose is to provide a tracer method.

Structure of the Invention The tracer method according to the present invention is a tracer method that stores data indicating the internal state of an information processing device, and stops the storage operation of the data in response to detection of a fault in the information processing device, Processing bag fi Color (7) When microinstructions At and Address are consecutive at the same address, the storage operation is stopped in response to detecting that the number of consecutive times exceeds a predetermined specific value. It is characterized by the following.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the tracer circuit according to one embodiment of the present invention includes a memory 1, a data register 2, a comparison circuit 3, and a counting circuit 4.
, a detection circuit 5 , a state holding circuit 6 , an address counter circuit 7 , and a control circuit 8 .

FIG. 2 is a more detailed circuit diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. The configuration and operation of an embodiment of the present invention will be explained in detail using FIG. 1 and FIG. 2.

The memory 1 stores microinstruction addresses for accessing a control memory (not shown) that stores microprograms, and multi-bit data indicating the status of an information processing device (not shown) containing this control memory. It also has a sufficient number of words to store data for the period from the occurrence of any fault to the detection of that fault. Write data is written to the word specified by the address output from the address counter circuit 7 in the memory 1 when the control circuit 8 instructs it with a write instruction signal, and when the control circuit 8 does not instruct it with a write instruction signal. In this case, the contents of the word specified by the address output from the address counter circuit 7 are read from the memory 1.

The data register 2 inputs and holds the microinstruction address input to the memory 1.

The microphone 1 command address held in the data register 2 is sent to the comparator circuit 3.

The comparison circuit 3 is composed of a comparator 30, which receives the microinstruction address input to the memory 1 and the microinstruction address held in the data register 2, compares these addresses, and determines whether these addresses match. When this occurs, a match signal is output.

That is, when the address input last time to the memory 1 and the address input this time match, a match signal is output.

The counting circuit 4 is composed of a register 40, a +17 dar 41, and a not circuit 42.
1 forms a counter.

+17der 41 inputs all bits of register 40, adds +1 to the contents, returns to register 40, and +
As a result of the addition of 1, a carry signal indicating that a carry is output from the most significant pin 1- is output. Register 40 is +
The output of 17der 41 is always set, and the comparator circuit 3
When an address mismatch is detected, this +17 dar 4
The contents of the register 40 are reset in priority to setting the output of 1.

In this embodiment, since the bit width of the register 40 is matched to the bit width of the specific value detected by the detection circuit 5, +17
The carry signal output from the register 41 is obtained by a counter formed by the register 40 and the +17 register 41 counting the number of times the matching signal is output from the comparator circuit 3 up to a specific value.
If this specific value is exceeded, it will be output. That is, when the same microinstruction address continues and the number of times exceeds a specific value, the +17 der 41 outputs a carry signal.

The not circuit 42 inverts the match signal from the comparator circuit 3 and turns it into a mismatch signal. This mismatch signal is used as a reset signal for the register 40 to initialize the count value, and is also sent to the detection circuit 5 to change the count value. Used to reset a flip-flop that indicates that is greater than or equal to a specific value.

The detection circuit 5 is composed of a 1-pit flip-flop 50, and the flip-flop 50 detects, based on a carry signal from the counting circuit 4, that the counting circuit 4 continues counting beyond a specific value. Furthermore, the setting of the flip-flop 70 and the knob 50 is performed by the carry signal output from the +17 circuit 41, and the reset of the flip-flop 50 is performed by the knot circuit 4.
2, and this reset is given priority over the set. The negative output of flip-flop 50 is sent to control circuit 8.

The above specific value is 11/2 of the total number of words in memory 1.
Set to the value of This results in 1 of the total number of words in memory 1.
/2 can store data for the period from the occurrence of a failure to the detection of the failure.

The state holding circuit 6 includes a register 60 and three AND circuits 6.
1, register 62, OR circuit 63, and NOT circuit 6
4. The register 60 stores and holds mask data specifying valid conditions among the stop conditions. This mask data is given externally,
It is stored in the register 60 by a mask set signal from the outside.

The AND circuit 61 ANDs the 3-bit output of the register 60 and the stop condition specified by each bit and outputs a stop signal. For this stop condition, detection signals of various failures within the information processing device are used. The register 62 inputs the stop signal from the AND circuit 61, stores and holds this stop signal, and is reset by an external operation start signal to initialize the held stop signal.

The OR circuit 63 receives the 3-bit stop signal of the register 62,
OR with the external forced stop signal.

Both of these signals indicate that writing of data to memory 1 is stopped. The NOT circuit 64 inverts the output from the OR circuit 63 and outputs a signal indicating that data writing to the memory 1 is active. This signal is used as a set signal to set a stop signal in register 62.

The address counter circuit 7 includes a register 70 and a +17 der 7.
1, an adder 72, and a switch 73.

The register 70 and the +17 register 71 form a counter for creating the write address of the memory 1. +17dar71
inputs the pin I- of the register 7o, adds +1 to this input content, and returns it to the register 70. In the register 70, the signal from the control circuit 8 is set as a set signal and +17 is input.
Set the output from 1. Roughly speaking, the register 70 outputs its contents to the adder 72 and the switch 73.

The adder 72 inputs the write address of the register 70 and external subtraction data, subtracts the subtraction data from this write address, outputs the subtraction result, and uses the fixed write address as a read address for memory 1. used to create relative addresses. The switch 73 switches between the write address of the register 70 and the read address output from the adder 72 based on the output signal from the state holding circuit 6. When this output signal is "1", that is, when writing data to the memory 1 is in operation, the switch 73 selects the write address of the register 70, and when it is "O", the switch 73 selects the write address of the register 70. Select a lead address.

The control circuit 8 is composed of an AND circuit 80. The AND circuit 80 ANDs the signal from the detection circuit 5 and the signal from the state holding circuit 6, so that data can be written to the memory 1 and the count value in the 31 number circuit 4 is specified. A signal indicating that the value is not greater than the value is generated, and based on this signal, the write address counter of the address counter circuit 7 is updated and a write instruction to the memory 1 is issued. Detection circuit 5'
When the signal from the control circuit 4 is a negative output indicating that the count value in the counting circuit 4 has exceeded a specific value, or when the signal from the state holding circuit 6 indicates a stop signal due to a failure in the information processing device, the control circuit 8 updates the write address counter of the address counter circuit 7 and stops writing instructions to the memory 1.

In this way, a microinstruction address is extracted from the data from the information processing device written to memory 1, and when the microinstruction address continues at the same address, the number of consecutive times is counted, and the count value is specified. By stopping writing data to the memory 1 when the value exceeds the value, even in the case of a fault detected by a timer, data before the occurrence of this fault can be left in the memory.

11. As explained above, according to the present invention, when microinstruction addresses are consecutive at the same address, writing to the memory is stopped when the number of consecutive microinstruction addresses exceeds a specific value. Even in the case of a failure detected by , data from before the occurrence of the failure can be left in the memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a more detailed circuit diagram showing one embodiment of the present invention. Explanation of symbols of main parts 2... Data register 3... Comparison circuit 4... Counting circuit 5... Detection circuit 8... Control circuit

Claims (1)

[Claims] A tracer method that stores data indicating an internal state of an information processing device and stops the storage operation of the data in response to detection of a failure in the information processing device, wherein the microinstruction address from the information processing device is the same address. 2. A tracer method characterized in that, when the number of consecutive times exceeds a predetermined specific value, the storage operation is stopped in response to detecting that the number of consecutive times exceeds a predetermined specific value.