RU1798804C - Device for object control - Google Patents

Abstract

The device relates to digital command-software temporary devices and can be used in devices that control an autonomous object. The device contains: input register (2), 2 blocks of clarity control (3). 5 decoders (4,5,18, 21,23), write and read control unit (7), 3 memory blocks (9, 10, 11), majority block (12), address register (13), 2 comparison blocks (14, 19), 2 counters (17, 22), 2 OR elements (15, 20). 1 ill.

Description

The invention relates to digital command-software temporary devices and can be used in devices that control an autonomous object.

The purpose of the invention is to increase the reliability of the device, to ensure control of the information recorded in the memory unit during its input, to increase the speed of reading and to control the object according to quantity commands.

The drawing shows a block diagram of the proposed device.

The device comprises an information input 1, input register 2, a first parity checker 3, first and second decoders 4 and 5, a block of elements And 6, a write and read control unit 7, a zero input 8, the first, second and third memory blocks 9. 10 and 11, majority block 12, address register 13, second comparison block 14, first OR element 15, second parity block 16, first counter 17, fourth decoder 18, first comparison block 19, second OR element 20, third decoder 21, the second counter 22, the fifth decoder 23, the signal output 24 of the device.

The device operates as follows.

The zeroing signal at input 8 resets input register 2, address register 12, write and read control unit 7, and first counter 17, for example, when the device is powered up.

 Through the information input 1, binary-coded data is inputted, which are divided into types:

- data subject to immediate decryption in the device and the issuance of one-time commands (RK);

- program data to be stored in memory, divided into program instructions (PC) and quantity instructions (VK);

- signs dividing this data and regulating the beginning and end of input.

According to signs, the teams are divided into the following types. RK is the command to be executed after its reception, PC is the command to be executed at a time determined by the program, VK is the command issued at the time of reading from the memory with a duration determined by the program.

In the characteristic part of a one-time command, the address of the subscriber to whom this command is to be issued is encoded. In the characteristic part of the program command, both the address of the subscriber and the current time in the program when this command should be issued to the subscriber are encoded. In the characteristic part of the quantity

the command encodes both the subscriber address and the duration of the command determined by the program.

The command word is input to input register 2, the input result is monitored

0 by the first block of parity 3. If the result of the control word is negative, then the signal output 24 of the device through the element OR 15 receives a signal indicating the need for repeated

5 words input.

If the correctly received word is a one-time command, then from the second output of the second attribute decoder 5 an enable signal is issued to the first

0 is a decoder of 4 one-time commands, from the output of which a one-time command is issued to the corresponding subscriber on the first information output.

In case the received word is

5

software, then from the first exit of the second

the sign decoder 5 is given a inhibitory signal to the first decoder 4, the enable signal to the second input of the block of elements And 6 and the signal to the first input

0 of the control unit for writing and reading 7. Block 7 provides the recording of the received word through the block of elements And 6 into three blocks 9, 10 and 11 of the memory and ensures the operation of the second block of comparison 14. Immediately information from the memory blocks is read and received through majority block 12 in the address register 13 for control. In the second block of comparison 14, the information is compared with the information stored in the input register 2. If the result of monitoring the information is negative, then the signal output 24 receives an signal through the OR 15 element, indicating the need to re-enter the word,

5 which makes it possible to bypass faulty memory addresses. If the control result is positive, the writing of words to the memory continues. At the end of the program recording by the Signal from the second decoder 5 block 7

The write and read control 0 goes into program read mode from the memory units 9, 10 and 11 without destroying the information. However, it passes through the majority block 12 with multiplexing either according to the majority principle, or only from one of the selected memory blocks 9, 10 or 11, depending on the state of the first counter 17 failures and enters the address register 13, as it goes to the second block parity control 1.6.

In case of a negative result, the control from the second output of the second parity block 16 gives a inhibit signal to the fourth decoder 18 and the word is not processed. At the same time, a signal is output from the first output of the second parity check block 16 to the first fault counter 17, by which the majority block 12c is controlled by multiplexing. The counter changes state. Immediately, the signal from the first output of the second parity block 16 is supplied to the write and read control unit 7 and the read is repeated.

If the control result is positive, the resolving potential is issued to the fourth decoder 18 from the second output of the second parity check block 16, and the feature part of the word is decoded in it. If the word has the sign PC, the fourth decoder gives the resolving potential from the second output to the first block of comparison 19. The address part of the word stored in the address register 13 is decrypted using the third program decoder 21, provided that the code of the time part of the word matches the current time code and an enable signal is supplied to the input of the third decoder 21 at the time of equal codes. If the word has the sign VK, the fourth decoder 18 gives the resolving potential from the first output to the second integrator counter 22. The address part of the word stored in the address register 13 is decrypted using the fifth decryptor 23 of the quantity instructions until the value of the duration of the instruction matches the value stored in the information part of the word. At the end of the command issued in accordance with the program, the write and read control unit 7 by the signal at the third input received through the second element OR 20 from the output of the first comparison unit or the second integrator counter 22 provides reading of the next program word,

The combination of control of the information recorded in the memory unit during its input, control of the words being read, selection of the output of the memory unit or one or most without rewriting, indestructibility of the information during reading, issuing of quantity instructions, provides the possibility of repeated cyclic execution of the entire array commands, and information recovery in case of its distortion in one or even two memory blocks, which reduces the failure rate of the device by half, improves performance

when reading information from the memory, and this increases the life of the object and reduces its reaction time to the commands issued by the program, compared with

prototype.

Claims (1)

SUMMARY OF THE INVENTION An apparatus for controlling an object, comprising a first parity block, an input register, an output connected to a first input of a block of elements I. to a first input of a first decoder and to a first input of a second decoder connected to a second output of a first decoder connected 5 by the first output with the second input of the first decoder, and the second output with the second input of the AND block, the first and second memory blocks, the first OR element, the address register associated with the output with the first 0 information input of the first comparison unit and with the first input of the third decoder connected by the second input to the output of the first comparison unit, the parity block connected by the first 5 by the output with the counting input of the first counter, the first output of the first parity block is connected to the third input of the first decoder, the output of which is the first Information output of the device, the information input of the input register, the second information input of the first comparison unit and the output of the third decoder are respectively information input, input time code and 5 by the second information output of the device, in that, in order to increase the reliability and speed of the device, a memory block, a majority block, a comparison block, a block are inserted into it 0 write and read control, two decoders, counter and OR element, the input and third output of the second decoder are connected respectively to the first output of the first parity block and the first 5 to the information input of the write and read control unit associated with the second information input with the first output of the second parity control unit, and the third information input with the output 0 of the second OR element, the first output - with control inputs for recording the first, second and third memory blocks connected by information inputs to the output of the block of AND elements, and outputs - 5 to the corresponding inputs of the majority block, connected by the control input to the output of the first counter, and by the output - from the information input of the address register, connected by the output to the first input of the fourth decoder, to the installation the input of the second counter and the information input of the second comparison unit, connected by the second information input to the output of the input register, the output - with the first input of the first OR element, and the control input - with the second output of the write and read control unit and with the control input of the second control unit parity T connected by the second output - to the second input of the fourth decoder, connected by the first and second outputs, respectively, with the control input of the account resolution of the second counter and with the control input of the first block Comparisons and connected to the output of the first input of the second OR gate, a second input connected to the output of the second counter and the first input of a fifth decoder, a second input connected to vy0 5 0 during the address register, the second input of the first OR element is connected to the second input of the first parity block, the information inputs of the first and second parity blocks are connected to the outputs of the input register and address register, inputs for resetting the input register, read and write control unit, address register and the first counter are combined and are the zeroing input of the device, the second information input of the first comparison unit and the counting input of the second counter are respectively set and so device inputs, the output of the fifth decoder is the third information output of the device, the output of the first OR element is the signal output of the device.