RU1798814C - Device for speech signal generation - Google Patents

Description

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The invention relates to speech informatics and can be used in various systems of speech interaction between a person and a computer.

The aim of the invention is to increase the volume of stored voice information and simplify the device.

Fig. 1 is a block diagram of a device for synthesizing speech signals; in FIG. 2 is an embodiment of a control unit; in FIG. 3 - a fragment of real speech (curve A) and its modernization (curve B); in FIG. 4 - key; in FIG. 5 - time schedules of the device; in FIG. 6 is a buffer structure defining a sequence of codes output to the device; in FIG. 7 is an algorithm for outputting a speech unit in standby mode.

The device for synthesizing speech signals contains a series-connected address generator 1, memory 2, the input of which is the input of the device connected to the computer interface highway, interface unit 3, control unit 4, element And 5. reversible counter 6, clock generator 7 , a key 8, the output of which is the output of the device, an inverter 9.

The first output of the control unit 4 is connected to the recording input of the reverse counter b, and the second output is to the input of the key 8, the third output of the control unit 4 is connected to the interface line, and the first input of the control unit 4 is connected to the first output of the interface unit 3, the second output of which connected to the recording input of the address generator 1 and to the second input of the control unit 4, the third input of which is connected to the output of the element And 5. The first output of the storage device 2 is connected to the input of the element And 5 and the information input of the reversible counter 6, subtract the upstream input of which is connected to the output of the clock 7. The second output of the storage device 2 is connected to the fourth input of the control unit 4, and the output of the reverse counter 6 is connected to the fifth input of the control unit via inverter 9, to the summing input of the address generator, the sixth input of the block control 4 is connected to a computer interface line.

In FIG. 2 shows a control unit 4, which contains an AND-NOT element 10, a D-trigger 11, an inverter 12. a diode 13. a capacitor 14, an AND-NOT element 15. An I. 16 element, an AND-NOT 17 element.

On Fig, 4 shows a key that contains a resistor 18. resistor 19. transistor 20.

In FIG. 5 shows timelines of the operation of the device, where a is the output of the D-trigger; b - inverse input of the D-flip-flop 11, c - signal Vyv.N; d - output 1 of control unit 4; d - clock sync pulses of the clock generator 7; e - and the outputs of the reversible counter 6; l-o - outputs of address generator 1.

Consider the operation of the proposed device. In one state in which the device is driven by the RESET signal H, the D-flip-flop 11 is set to one state, the zero from its inverse output locks the NAND element 10 of the control unit 4, and therefore, the output of the N-HE 15 element is set to low the level of the signal that holds the reversing counter 6 in the recording mode. This prohibits the counting of pulses and there are no zero pulses at the output of the reverse counter, since the first input of the AND-17 element has a high level, then, upon the arrival of the BB H signal from the first input of the control unit 4, the computer reads low

5 level (i.e., unit) device ready signal. In order to reproduce the desired speech unit, it is necessary to write a computer through the interface unit 3 to the address generator 1 code, which

0 sets the starting address of the speech unit recorded in the memory 2. The code is written to the address generator 1 by the signal SEL from the second output of the interface unit 3. through it

5, the D-flip-flop 11 is reset (see Figs. 3, 4. 5) and a high signal level is established at the third input of the AND-NOT 10 element. Since the D-trigger 11 has a finite response time, a high level at the output of the AND-NOT element is removed (and at the output of the AND-NOT element 15 is activated) by removing the EXIT signal, which will record the low-order bits of the number from the output memory device 2 into a reverse counter 6 and will enable the count.

By the moment of arrival of the trailing edge of the SIGNAL signal, the data has already been set at the outputs of the read-only memory 2.

0 The high-order bit of the number from the second output of the storage device 2 through the block 4 controls the state of the key 8 (the key 8 supplies the output of the device with a constant high voltage or zero).

5 After the high-level reversible counter 6 is installed at the recording input V, it starts working in the subtraction mode, counting the half-wavelength of the sound signal. A zeroing pulse that produces a zero level signal from the output

the reverse counter 6 (it signals that the subtraction is completed), is fed through the inverter NOT 9 to the summing input of the address generator 1 and to the fifth input of the control unit 4. The leading edge of the zeroing pulse will change the address of the memory unit 2 and after a time delay on the elements 13, 14, 15, which is necessary for reliable reading of data at the new address, enters the new time code into the reverse counter 6. Entering the time code results in the resetting of the zeroing signal. Therefore, the nulling pulse is obtained much shorter than the half-cycle of the clock frequency. and the next positive edge of the clock frequency causes the unit to be subtracted from the counter 6 and there is no loss of pulse (see Fig. 5). As soon as there will be a zero code in the reverse counter b. the next nulling pulse will occur and the entire speech cycle is repeated until then. until the first output of the memory device 2 does not display a code N having units in all bits, which is recognized by the circuit AND 5. This code marks the end of the output of the speech unit. The signal from the output of element And 5 enters the control unit 4, which by this signal gives a low level at its output 1 and this prohibits the operation of the reverse counter 6. At the same time, block 4 sets a constant high level at the second output, stopping the sound output and prepares the element AND-NOT 17 for generating, on the third output of the control unit 4, a ready signal in the computer.

When preparing information for recording in memory 2, it must be ensured that there is no accidental coincidence of the pulse or pause duration with code N, which is a sign of the end of a speech unit. Long recording time slots should be split into several time slots of no more than N-1 in length.

By the signal of readiness, the computer can send a new code to the address generator 1 through the interface unit 3 and the operation of the device will be repeated. The computer reads the ready signal. issuing through the interface unit 3 the BB signal to the first input of the control unit 4. The control computer needs to know only the sequence of starting addresses of the speech units stored in memory 2. To reproduce speech in the 5 kHz range, the clock frequency 7 should be on the order of 20 kHz. Moreover, for encoding the pulse length, 4-5 bit codes stored

in memory 2. It should be noted that the duration of the first pulse can be increased by the length of the output signal of the device, but this does not affect the quality of speech.

On the basis of the proposed device, various voice output systems can be built, characterized by a computer program and the contents of the storage device 2.

0, complete phrases, single words, phonemes, or phoneme pairs can be stored in memory 2.

In the first case, the pauses between the words will be encoded in the speech unit similar to the words - the pause will be a sequence of memory cells with a zero high-order value.

In the second case, the computer program builds phrases, sequentially transmitting the address of the necessary words. The moment of setting the address of the next word is determined by the availability of a ready signal at the 3rd output of the control unit 4. A pause can be encoded at the beginning or at the end of each word.

5 In this case, the computer is not involved in the counting of pauses, since this function is fully implemented by the device. This allows you to expand the total message volume by reusing one voice unit.

0 (words) in a few sentences. To reduce the required memory space, pauses of different durations can be encoded in block 2 as separate speech units. When building phrases from computers should

5 to be sequentially displayed in the device addresses of the required words and pauses between them. The structure of the phrase in this case can be set in the computer memory by a table (Fig. 6), the first element of which contains the length of the table:

0 tsy. and subsequent elements are the values of the codes output to the device. The table encodes a four-word phrase, and the pauses between the words are the same and are set by the T1 code, and after the last word is displayed

5 (output to code A4) pause with code T2. separating this phrase from the following. In this case, the computer also does not count the value of time intervals, but sets the value of the pause

0 by output of the corresponding code P.

If pauses are not encoded in unit 2 of the device or there are no intervals of the required duration in the available set of pauses, the countdown of time intervals may be

5 is possible on a computer. The phrase coding table may have the same structure as that shown in FIG. 6, but Ti elements will not mean a code (pause address in block 2) to be output to the device. and the value of the time intervals that

computers must be read between the operations of outputting the Aj codes to the device.

The time intervals are usually counted by a computer operating system using a timing device - a timer and system programs, i.e. from an application programmer, the value of timing algorithms is not required. .

In the third case (when the complete set of dyrons is stored in the memory), messages of unlimited volume can be generated. In addition, you can play arbitrary text using a keyboard input.

There are various peripheral control algorithms. Four possible exchange methods are indicated: synchronous, asynchronous (in standby mode), interruption, and using direct memory access.

When working with the device, synchronous exchange can be used if the speech unit is a complete phrase and it is known that the previous output is completed. .

If the output of a phrase can be interpreted before completion of the previous output, or the phrase is composed of several speech units, as shown in FIG. 6, it is necessary to apply the asynchronous output algorithm shown in FIG. 7.

By reading the readiness signal of the device, a value of logical zero is output from the output of block 3 into the computer. 4, This signal is a sign of completion of the output of a speech unit, i.e. sign of readiness for the next conclusion.

If the device is not ready, the reading is repeated, and if ready, the next speech unit is output.

The computer interface unit 3 can also provide interrupt operation to the device. It is also possible to modify the interface unit, in which it not only transfers the address to memory 2. but also writes data from the computer to it. The resulting further bonds do not alter the essence of the invention. Interrupt communications can be implemented by using the signal from the 3rd output of a 4v block. quality of the signal fulfilling the interrupt requirement.

The implementation of the interface unit 3 depends on the type of interface used in the computer with which the device should operate. One of the possible implementations of the interface unit for working with the trunk interface of the MPI on OST

11.305.903-80 in standby mode is implemented by a single chip K 588 B T 1.

In this case, the interface highway contains sixteen buses AD1 ... AD16 for transmitting the address and data exchange between computers and peripheral devices, i.e. on the AD buses, a code is alternately supplied. ADDRESS and code DATA. In addition, with 0 access to a peripheral device (i.e., at an address greater than 160.000s), simultaneously with the address of the computer device, a VU signal is generated. The interface control unit 5 also receives interface control signals from the computer 3: the SIA signal, indicating that the computer has set the subscriber's address on the AD buses. CONCLUSION indicating that the computer set up data on the AD1 buses to be entered at the previously set address and the signal ENTER, at which the peripheral device should set the data for input into the computer.

A processor working with the MPI interface (for example, microprocessors K 5 1801VM1, K1801VM2) captures the inputs. data before the end of the ENTER signal it issues. Therefore, the data signal from the interface line must be delayed. With respect to the removal of 0 - the signal input. This delay is usually not carried out in peripheral devices, but in the processor unit. The input signal generated in the trunk is delayed with respect to the input signal at terminal 5 of the microprocessor.

After receiving data from the computer via the OUTPUT signal or transmitting data to the computer via the ENTER signal, the interface unit 3 transmits to the computer the SIP signal, allowing the computer 0 to start a new cycle / t of data exchange. Active levels of all signals are low. It should be noted that the address transmitted on the MPI trunk in the interface unit 3. is a code identifying this peripheral device 5. The voice message address is recorded in the address generator 1 through the interface unit 3 by the DATA interface code.

A device for synthesizing speech signals can be implemented on the following types of microcircuits:

blocks 1. 6-K155IE7. Block 2 - K573RF6A. block 5- K555LI6. 5block 9-K155 LN1. block 10- K155LA4. block 11 - K155TM2. block 12 - K155LN1. block 13 - diode KD 522A. block 15- K155 LAZ.

block 16 - K155 LI1. block 17- K155 LA8. block 20 - KT315G.

So, the essence of the invention is as follows. In the proposed device, for each half-wave of the speech signal, only one number is stored in the memory, encoding its duration. The high-order bit of this number indicates the level of signal output to the key (1 - high, 0 - low). This allows you to increase the total amount of stored speech without increasing the memory capacity. The signal output to the key, in this case, takes only two values - a high level during the positive half-wave and low during the negative. Thus, the coding of each half-wave requires one small-bit number. It was experimentally verified that the presentation of the speech signal (a fragment of which is shown in Fig. 3. curve A) in the form shown in Fig. 3, curve B does not affect speech intelligibility. In FIG. 3, all signal values are greater than a certain level of H, replaced by a constant high level, and less - H - by a constant low level, i.e. the speech signal is replaced by a sequence of rectangular pulses. Moreover, if such a signal is supplied to the loudspeaker, then not only speech intelligibility is maintained, but (due to the pulse duration) the different loudness of speech is reproduced. It has also been experimentally established that four bit codes are sufficient to encode the duration of the pulses and the distances between them.

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Claims (1)

In addition, the device is very simple in technical implementation, as it is assembled on discrete elements. The claims A device for synthesizing speech signals, comprising a memory unit, an address generator, the outputs of which are connected to the address inputs of the memory unit, and a pulse generator, which entails that, in order to increase the amount of synthesized speech information, elements AND and NOT are inserted into it, a key, a reversible counter and a control unit, the first input and output of which are the input of the initial installation and the device ready output, the second and third inputs are the control inputs of the device and the second output is connected to the input of the key, the output of which is the information output of the device, the information inputs of which are respectively the information inputs of the address generator, the control input of which o is connected to the second input of the control unit, and the information input is connected to the output of the element NOT. the input of which is connected to the fourth input of the control unit, and the output of the reversible counter, the information inputs of which are connected to the outputs of the memory unit and the inputs of element I. The output of which is connected to the fifth input of the control unit, the third output of which is connected to the control input of the reverse counter, whose counter input is connected to the output pulse generator, one of the outputs of the memory unit is connected to the sixth input of the control unit. . Riga 5 FIG. 4 BUf : Rive. 6. With M & Chalo j Read toe / no stun device You & $ 6 kOZ / device / &