JPH0486032A - Sound code - Google Patents

Abstract

PURPOSE:To reduce average energy consumption by outputting a silence code when a silent state is detected, and stopping the operation of a part which is not related to the operations of a silence detecting means and a silence code output means. CONSTITUTION:When the value of a counter reaches a set value, the level of accumulated power is decided. In the case of silence, a selector 7 is set through a control register 4 to the side of a silence register 6 as a silence code output means. Further, after a FIFO memory 5 is reset, a low-speed clock mode is set to a clock generation part 2 as a bottom frequency for a part composed of the program of a silence detector, etc., which is operated in the case of silence, to finish the processing within a sound input rate. Therefore, an encoding processing is stopped in a silence block, and a silence detection processing is executed by the low-speed clock mode. Thus, energy consumption can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an audio codec for compressing and encoding audio signals, and in particular to audio codecs used in devices that require low power consumption such as portable digital telephones. Regarding codecs.

[Prior Art] Conventionally, this type of audio codec compresses and encodes input audio by constantly operating an encoder during a call.

On the other hand, in recent years, there has been a demand for lower power consumption in devices that use this type of voice codec, including portable digital telephones.

[Problems to be Solved by the Invention] However, in the conventional audio codec, power consumption is determined by its operating clock frequency, so in order to reduce power consumption, the operating clock frequency must be reduced.

In this case, there is a problem in that it causes inconvenience to the receiving station.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a voice codec that can reduce average power consumption without causing any inconvenience to a receiving station.

[Means for Solving the Problems] The audio codec according to the present invention includes an encoding means for encoding an audio input signal to obtain encoded data in which the amount of information thereof is compressed, and an encoding unit obtained by the encoding means. A normal code output means for storing and outputting data; and measuring the cumulative power of the audio input signal over a certain period of time and comparing the cumulative power with a predetermined threshold to determine whether there is no sound or a sound state. a silence detection means for detecting whether there is a sound; a silence code output means for outputting only silence codes; and when the silence detection means detects a voice state, encoded data from the normal code output means is selected to detect silence. Output selection means for selecting a silence code from the silence code output means when a state is detected; and output selection means for selecting a silence code from the silence code output means when a silence state is detected; It is characterized by comprising a control means for stopping the operation of the parts that are not present.

[Effects] According to the present invention, the silent period included in the call time, for example, the time from when the call switch is turned on until the voice is uttered, the silent time between spoken words, the silent time included in one word. , and the silent time from the end of the call until the call switch is released by the silence detection means, and when the silence detection means detects a silence state, outputs a silence code from the silence code output means, Since the operations of parts not related to the operations of the silence detection means and the silence code output means are stopped, power consumption can be significantly reduced.

Moreover, by reducing the frequency of the operating clock of the silence code output means and the silence detection means during silence, it is possible to further reduce the average power consumption.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an audio codec according to a first embodiment of the present invention. Note that the audio codec according to this embodiment is one in which an encoder and a silence detection section are realized by a program.

In FIG. 1, input data is internally taken in via an input data bus 11 and an input register 3. In FIG. The input register 3 is connected to the arithmetic unit 1 via the internal data bus 12.
, control register 4 and FIFO memory 5.

The calculation unit 1 functions as an encoder and silence detection means together with a predetermined program. The silence detection means includes a counter for counting the number of input samples, a power calculation section, a power accumulation register, and an accumulation power determination section, which are realized by software. Also,
The arithmetic unit 1 operates based on the arithmetic unit clock supplied from the clock generation unit 2.

The clock generation unit 2 generates a calculation unit clock based on an external main clock, generates a hardware reset signal based on an external reset signal, and further generates a clock switching signal generated by a control register 4. Performs high-speed/low-speed switching of the arithmetic unit clock corresponding to the

The control register 4 is a register whose contents can be checked via the arithmetic unit 1, and its operation is performed in synchronization with the selection signal A1, the read signal, and the write signal. Clock switching specification, FI
The output designation of the FIFO reset signal to the FO memory 5 and the designation of the output selection signal to the selector 7 can be set.

The FIFO (first-in, first-out) memory 5 is a normal code output means that holds and outputs a plurality of code data from the calculation unit 1. Writing is performed when the calculation unit 1 confirms the empty state of the FIFO memory 5 using a FIFO full signal. After that, it is performed in synchronization with the selection signal C and the write signal, and the subsequent
When the data in the FIFO memory 5 becomes full, the processing is performed according to the output ready signal and the FIFO full signal. Further, this FIFO memory 5 is reset by a FIFO reset signal from an OR gate 8 that outputs the logical product of a hardware reset signal output from the clock generator 2 and a software reset signal output from the control register 4. It becomes.

The output of this FIFO memory 5 is input to one input end of the selector 7 via an internal data bus 14. Further, this audio codec is equipped with a silence register 6 as a silence code output means for outputting a silence code, and the output of this silence register 6 is inputted to the other input end of the selector 7 via an internal data bus 13. has been done.

The selector 7 selects either the output of the silence register 6 or the output of the FIFO memory 5 according to an output selection signal specified by the control register 4. The selected data is output to the output data bus 15 in synchronization with the output data read signal.

FIG. 2 is a flowchart showing the operation of the audio codec configured as described above, and FIG. 3 is an operation timing diagram of the audio codec.

When the external reset signal to the clock generation section 2 is released, the clock generation section 2 generates a high-speed clock as an operation clock.

The arithmetic unit 1 starts normal operation, and first, the control register 4
outputs a FIFO reset signal through
SL).

Next, the number of samples for accumulating the power of input audio data is set, a counter for counting the number of input samples is initialized, and then processing is started (S2).

Every time data is read from input register 3 (S3)
, increment the counter (S4), and accumulate the square value of the input data as the power of the input data (S4).
S6). If the counter is equal to or less than the set value (S8), subsequent to power accumulation, encoding processing is performed (Ss), and encoded data is written into the FIFO memory 5 (Sθ).

When the counter reaches the set value, determine the cumulative power level. ), in the case of silence, set the selector 7 to the silence register 6 side, which is a silence code output means, via the control register 4. 8.3) After resetting the FIFO memory 5 (S, , ), clock generation is performed. For part 2, the part consisting of a program such as a silence detector that should operate when there is no sound specifies a low-speed clock mode that is the lowest frequency that can complete processing within the human voice rate (8.5), and encodes it. No processing or output of encoded data to FIFO is performed.

From then on, every time data is read, the counter is incremented in S3. S4), Accumulate the power of the input data, for example, the square value of the input data, repeat the same operation, and when the counter reaches the set value, judge the cumulative power level.S□2), If there is a sound In order to specify the high-speed clock mode for the clock generation unit 2 via the control register 4 (S+e), the selector is set to the FI which is the postfix output means.
Set to FO Memo IJ 5 side.

By performing such processing, the encoding process is stopped during the silent section, and the silence detection process is performed in low-speed clock mode, resulting in a significant reduction in power consumption, as shown in Figure 3. I can do it.

FIG. 4 is a block diagram showing a second embodiment in which the encoding means and silence detection means of the present invention are constructed by hardware. In FIG. 4, the same parts as those in FIG. 1 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

The silence detection section 32 and the encoder 33 operate according to a silence detection section clock and an encoder clock, respectively, which are generated by the control section 31 based on an external main clock.

In addition to clock generation, the control unit 31 also generates a read clock based on an output data read signal, an input clock and an output clock, a silence detector reset signal based on an external reset signal, an encoder reset signal, and an encoder reset signal based on an external reset signal. FI
It generates an FO reset signal, outputs an output selection signal based on the silence detection signal, switches the silence detector clock between high and low speeds, and generates an encoder reset signal and a FIFO reset signal.

The silence detection unit 32 determines the cumulative power level of data input in synchronization with the input clock via the input register 3 in the same manner as in the first embodiment, and in the case of silence, detects silence. Output a signal.

Based on the silence detection signal, the control unit 31 sets the selector 7 to the silence register 6, which is a silence code output means, and
Reset FO memory 5. After that, the control unit 31
The encoder 33 is stopped by the encoder reset signal, and the silence detector 32 switches to the clock having the lowest frequency at which the processing can be completed within the audio input rate.

On the other hand, if silence is not detected, the control section 31 sets the selector 7 to the FIFO memory 5, which is a normal code output means. Thereafter, the control section 31 restarts the operation of the encoder 33 and restores the silence detection section clock, which has been slowed down.

The FIFO memory 5 is a first-in, first-out memory that holds a plurality of encoded data from the encoder 33, and its writing is performed in synchronization with the output clock of the control section 31. Then, when the data in the FIFO memory 5 becomes full,
Output ready signal is output.

The selector 7 selects the output of either the silence register θ, which is a silence code output means, or the FIFO memory 5, which is a normal code output means, in response to an output selection signal output from the control section 31.

The encoded data is output to the output data bus 15 via the selector 7 in synchronization with the output data read signal.

According to this circuit, in a silent section, the encoding process is stopped, the silence detecting section 32 and the silence register 6, which is a silence code output means, are operated at the minimum clock to output silence code data, and vice versa. When there is a sound, an audio codec with reduced average power consumption can be realized by performing encoding processing using the normal clock and outputting encoded data.

Note that in this method, the encoded data of the first power accumulation block of the detected sound part and the first power accumulation block of the detected silent part are lost, but generally the time of the power accumulation block is about 10 to 20 m5. There is almost no practical problem for the receiving station.

[Effects of the Invention] As described above, according to the present invention, the silence period included in the call time is detected by the silence detection means, and when the silence detection means detects a silence state, a silence code is detected. Since the silence code is outputted from the output means and the operation of parts not related to the operation of the silence detection means and the silence code output means is stopped, the average power consumption can be significantly reduced. play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the audio codec according to the first embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the audio codec, FIG. 3 is a timing diagram showing the operation of the audio codec, and FIG. 4 FIG. 2 is a block diagram of an audio codec according to a second embodiment of the present invention. 1; Arithmetic unit, 2; Clock generation unit, 3; Input register,
4; Control register, 5; FIFO memory, 6; Silence register, 7; Selector, 8; OR gate, 11; Input data path, 12 to 14: Internal data bus, 15; Output data bus, 31; Control unit, 32 ; Silence detection unit, 33; Encoder

Claims (2)

[Claims] (1) An encoding means for encoding an audio input signal to obtain encoded data whose information amount is compressed; a normal code output means for storing and outputting the encoded data obtained by the encoding means; Silence detection means measures cumulative power of an input signal over a certain period of time and compares this cumulative power with a predetermined threshold value to detect whether it is a silent state or a sound state; A silence code output means to output, and when a voice state is detected by the silence detection means, encoded data from the normal code output means are selected, and when a silence state is detected, encoded data from the silence code output means is selected. The apparatus further comprises an output selection means for selecting a silence code, and a control means for stopping the operation of a portion unrelated to the operation of the silence code output means and the silence detection means when a silence state is detected by the silence detection means. Featured audio codec. (2) The audio system according to claim 1, wherein the control means reduces the frequency of the operating clock of the portion that operates during the silent period when the silent state is detected by the silent detection means. codec.