SU1633402A1 - Microprogrammed control device - Google Patents

Abstract

The invention relates to automation and computing technology and can be used to control a specialized device operating on a time scale, or as an ACV process controller, providing control on signals from sensors in normal and emergency modes. The purpose of the invention is to expand the field of application by implementing the possibility of analyzing the complex of logical conditions and improving the speed of the device by providing the possibility of joint storage and implementation in one device of both subprograms with relative priority and subprograms with absolute priority corresponding to processing. emergency situations. The firmware contains three blocks of firmware memory, a counter, a multiplexer, OR, AND elements, a clock generator, a set of logical conditions, an absolute priority trigger, two switches, a constant generator one, a single vibrator. 2 Il. with $ ate

Description

The invention relates to automation and computer technology and can be used to control a specialized device, real-time sweeping, or as an ACS controller for technological processes, providing control by signals from sensors in normal and emergency modes.

The purpose of the invention is the expansion of the field of application due to the realization of the possibility of managing complex logical conditions and increasing the speed of the device.

Figure 1 shows the Lunctional diagram of the device; Lig.2 is the time diagram of the device function.

The device (Lig.1) contains the first-third 1-3 microprogram memory blocks, a generator of 4 clock pulses, a register 5 of a set of logical conditions, a counter 6, a multiplexer 7, a trigger 8 of absolute priority, a single vibrator 9, the first 10 and the second 11 switches, elements OR 12-14, element 15, constant generator unit 16, group 1 / single inputs

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logical conditions, a group of 18 inputs 1 complex logical conditions.

In addition, memory block 2 has outputs of field 19.1 micro-operations of field 19.2 of address, field of 19.3 logical conditions and indication 19.4 of the conditional transition, and block 3 of memory — outputs of field 20.1 of address and indication of 20.2 absolute priority.

The memory unit 1 serves for storing and issuing information about the addresses of the main microprograms, as well as about the addresses of the subroutines ensuring the operation of the firmware control device in emergency mode.

The memory unit 2 is intended for storing and issuing firmware that ensures the operation of the firmware control device in the main program mode and in the interrupt routine mode.

Memory unit 3 is designed to store and issue addresses of interrupt routines with relative priority. Reading information from memory block 3 is allowed only if there is a single signal at input V.

The generator 4 clock pulses serves to synchronize the operation of the functional elements included in the device.

Register 5 of a set of logical conditions is intended for receiving, storing, and issuing values of a set of logical conditions arriving at inputs 18 of a microprogram control unit. The signals at its outputs determine the portion of the microcommand address stored in the third memory block 3.

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Counter 6 serves to forward at the corresponding time points or under the respective conditions of the first and second memory blocks 1 and 2, respectively.

The multiplexer 7 serves for switching to the first input of the second element OR 14 of one of the inputs of the logical conditions of the device OR 17 of the output of the constant generator unit 16.

Multiplexer 7 implements the following logic function.

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where D and A; - signals for information and address (control to g (nx) multiplexer inputs,

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Trigger 8 absolute priority, one-shot 9, the first switch 10, JQ the second switch 11, the third element

OR 12, the first element OR 13, the second. element OR 14, element 15 and are designed to control the operating modes of the device.

15 The constant generator unit 16 is used to organize the operation of the device in the unconditional transition mode. The principle of operation of the firmware control device is as follows.

There are two micromodes of operation. 1. The operation of the firmware control device for the execution of uninterrupted firmware. 25 2. The operation of the firmware control for the implementation of interrupted firmware.

Each type of work has its own modes.

3Q Consider the modes for the first macro mode:

1.1. Natural addressing mode, when counter 6 is redirected by impulse signals arriving at the C (-H) input of the counter

6 from the generator 4 clock pulses.

1.2. The unconditional transition mode, when the counter 6 is redirected, is received when a single signal is received at the count / record input of the counter 6 from the output of the second element OR 14.

1 „3. The conditional transition mode according to the zero logical condition, when dc is redirected by the counter 6 is carried out by the arrival at its input of the count / write signal of the zero level, by the sync signal from the second generator output 4 clock pulses.

1.4. The conditional transition mode by a single logical condition, when counter 6 is redirected upon the arrival of a single level at the input of an account / record.

For the second macro mode of operation there are the following modes:

2. To the main microprogram interrupt mode according to the usual set of logical conditions (with relative

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priority) when the device is functioning normally (no emergency conditions are created).

2.2. The mode of interrupting the main firmware in an emergency condition of logical conditions (with absolute priority) when an emergency situation occurs.

The priority of the interrupt modes is determined by the level of the signal appearing at the outputs 19.4 and 20.2 of the second 2 and third 3 memory blocks, respectively.

Let us consider in more detail each of the types and modes of operation of the device.

Mode 1.1, natural addressing is performed in this mode. R Initial time counter 6 and trigger 8 of absolute priority are in the zero state. With this, from the outputs 19.3 the logical conditions of the second block 2 of the microprogram memory, the control inputs of the multiplexer 7 receive a zero code, according to which a logic zero signal appears at its output. At the same time, at the output 19.4 of the second block 2 of the microprogram memory, and consequently, at the output of the AND 15 element and at the second input of the third element OR 12 there is a logical zero signal.

The first clock pulse from the first generator output 4 clock pulses writes into register 5 of the complex of the logical conditions of a set of logical conditions received at the inputs 18 of the device.

The signals from the outputs of register 5 of the complex of logical conditions are fed to the first address inputs of the third block 3 of the microprogram memory. At the same time, at its outputs 20.1, a first micro-command appears, determining the address of the first micro-command of the interrupt microprogram, and a signal at output 20.2, determining the interrupt mode.

Suppose that the first clock pulse from the first generator output 4 clock pulses into register 5 of the complex of logical conditions was

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This signal is fed to the input of the single-oscillator 9. The zero-level signal from the output of one of the selector is fed to the first input of the third element OR 12, which ensures the zero level at the output of this element.

At this time, at the outputs of the address of the first block 1 of the firmware memory there is a code defining the address of the first microcommand of the device firmware. This code goes to the first information input of the first switch 10 of the device, which is allowed to pass through the zero level coming from the output of the third element OR 12 to the first inverse control input of the first switch 10. From the outputs of the first switch 10, the address code of the first microcommand goes to the information inputs of the counter 6

The first sync pulse from the second output of the 4 sync pulse generator increases the contents of counter 6 by one, thereby determining the address of the first micro-command of the device firmware.

The address code of the first microcommand from the outputs of counter 6 is fed to the address inputs of the first 1 and second 2 memory blocks of the microprograms, respectively. At the same time, at the outputs of the first block 1 of the microprogram memory, the address code of the second microcommand appears, and at the outputs of the second block 2 of the microprogram memory - the first microcommand of the device microprogram. . The signal at output 19.4 of the second block 2 of firmware memory is still zero. From the outputs of field 19.3 of the logical conditions of the second block 2 of the microprogram memory, the address outputs of multiplexer 7 still receive a zero code.

The zero level signal from the output 19.4 of the second block 2 of the microprogram memory is fed to the second input of the element 15, thus leaving it in the zero state. From outputs 19.2 the address field of the second block 2 of the microprogram memory to the second, address inputs of the third block 3 of the microprogram memory, the address code is received,

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written such a set of logical rules partially defining the address of the second

vii, in which no interruptions should occur. Then, at output 20.2 of the third block 3 of firmware memory, there is a signal of zero

micro-instructions informing about the address of the second interrupt micro-command. The second sync pulse from the first generator output 4 sync pulses

microcommand informing about the address of the second microcommand interrupt. The second sync pulse from the first generator output 4 sync pulses

writes to the register 5 of a set of logical conditions received at the inputs 18 of the device. The signals of the complex of logical conditions from the outputs of register 5 are sent to the first address inputs of the third block 3 of the microprogram memory and carry out its redirection. At the same time, at the outputs of the third block 3 of the microprogram memory, there appears a code defining the address of the third interrupt micro-instruction.

Again, suppose that the set of logical conditions that came to the inputs 18 of the device does not require interruptions, then the output 20.2 of the third block 3 of the microprogram memory will retain the zero level signal. The zero level signal through the one-shot 9 passes to the first input of the third element OR 12 and passes through it, since the third element OR 12 is prepared for the zero-level signal to pass a zero signal from the output of the AND 15 element.

The zero level signal from the output of the third element OR 12 allows the passage of the address code of the second microcommand of the device operation from the first block 1 of the firmware memory through the first inverse control input of the first switch 10 to the first input of the second element OR 14 and prevents the passage of signals from the third block 3 microprogram memory for the second information input of the first switch 10.

The address code of the second microcommand from the outputs of the first switch 10 is fed to the information inputs of counter 6.

The second sync pulse from the second output of the sync pulse generator 4 increases the contents of counter 6 by one, thereby determining the address code of the next micro-command of the device operation.

Further operation of the device in this mode is carried out according to the law of operation.

Mode 1.2. This mode performs an unconditional transition. In this case, at the output 19.3 of the logic conditions of the second block 2 of the microprogram memory, a code appears that determines the number of the highest of the information inputs 17 of the multiplexer 7. A constant generator of 17 is connected to this input. Therefore, at the output of the multiplexer

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the typelexer 7 by Wits logical unit, which goes to the first input of the second element OR 14, while the output of the second element OR 14 also goes to a single level, which goes to the input of the counting record of the counter 6. Therefore, the counter 6 will write the code the addresses of the next microcommand determined by the code present at this moment in time at the information inputs of the counter 6.

Further operation of the device in this mode is carried out according to the law of operation.

Mode 1.3 (1.4. In these modes, a conditional transition is performed. In this case, a conditional transition is possible both by a logical condition having a zero level and by a logical condition having a unit level.

If the code from the output of field 19.3 of the logical conditions of the second memory block 2, arriving at the address inputs of multiplexer 7, selects a logical condition that has a single level, then the signal of a single level from the output of multiplexer 7 enters through the second element OR 14 to the count / record input of counter 6 At the same time, it is clear that the process of functioning of the device is similar to the process of functioning in the unconditional transition mode.

If the code from the output of field 19.3 of the logical conditions of the second block 2 of the microprogram memory selects a logical condition having a zero level, then it is assumed that the second input of the second element OR 14 has a zero level, the operation of the device is similar to the operation of the device in the already considered above mode 1, when natural addressing occurs.

Mode 2.1. In this mode, an interrupt is performed according to the usual set of logical conditions, i.e. when the device is functioning normally.

If a set of logical conditions at which an interrupt is enabled is input to the device inputs 18, then this set of logical conditions is added to the register L by the next sync pulse coming from the first generator output 4 sync pulses.

The complex of logic conditions from the outputs of register 5 is fed to the first address inputs of the third block 3 of the memory of microprograms and redirects it.

In this case, the output 19.4 of the second block 2 of the firmware memory contains a signal of a logical unit. The complex of logical conditions that allow an interruption cannot be zero. Therefore, arriving at the inputs of the first element OR 13, the signals of the complex of logical conditions translate it into a single state. Single signals from the output of the first element OR 13 and the output 19.4 of the second block 2 of the memory of microprograms arrive at the inputs of the element AND 15 and translate it into a single state. A single signal from the output of the AND 15 element goes through the third element OR 12 to the second control input of the first switch 10, thereby allowing code passing through it defining the address of the interrupt microcommand according to the usual set of logical conditions coming from the outputs of the third memory block 3 ti firmware.

The address code of the first microcommand of interruption is supplied to the information inputs of the counter 6 according to the usual complex of logical conditions.

A single signal from the output of the third element OR 13 is fed to the first control input of the first switch 10. Thus prohibiting the passage through it of the code defining the address of the microcommand of the main firmware from the first block 1 of the firmware memory.

A single signal from the output of the third element OR 13 enters the second input of the second element OR 14, passes through it and enters the count / record input of counter 6. In this case, counter 6 records information about the address code of the first interrupt micro-command, which t outputs of counter 6 will go to the address inputs of the first and second blocks 1 and / memory, respectively.

After the device enters a new state, two cases are possible.

In the first case, the resumption of the operation of the device after an interruption is carried out from the place of the program belonging to such its part, where the interruption is also allowed. Then at

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The presence of the required set of logical conditions at the inputs 18 of the device makes the transition to a new program location. If the new program location also belongs to its section where the interrupt is enabled, the transition process continues until the device changes to the state corresponding to the section of the program where the interruption is prohibited.

In the second case, the device resumes operation from the program site belonging to such a part of it, where the interruption is prohibited or the interruption conditions are absent. In this case, from the specified place of the program, operation of the device continues normally.

Mode 2.2. In this mode, the firmware is interrupted according to an emergency complex of logical conditions. In this case, the addresses of the emergency firmware are recorded in the first block 1 of the microprogram memory.

In this mode, the device operates as follows. An emergency complex of logical conditions enters the inputs 18 of the device. On the next sync pulse arriving at the C input of the register 5 of the complex of logical conditions from the first generator output of 4 clock pulses, the complex of logical conditions is recorded in register 5. From the output of the register 5, the signals of the logical condition complex go to the first address inputs of the third block 3 of the microprogram memory 3, this forwarding it for the device to process the emergency routine. At the same time, the output of 20.2 of the third block 3 of the firmware memory will contain a signal of a logical unit. This means that the execution of this micro-command has absolute priority with respect to all other types of micro-commands. A single signal from the output 20.2 of the third block 3 of the microprogram memory goes through the single-clock 9 to the first input of the third element IDB-I 12 and translates it into a single state. The unit level from the output of the third element OR 12 allows the second control input of the first switch 10 to pass signals through the second information input of the first switch 10. Therefore, the output code of the first switch 10 will contain the address code of the first

emergency device microcommand. This code arrives at the information inputs of the counter 6.

A single signal from the output of the third element OR 12 is also fed to the second input of the second element OR 14 and translates it into a single state | the The level of the logical unit is fed to the input of the account / record of the counter 6. Thus, the address code of the first emergency micro-command is written to counter 6.

A single signal from the output of the one-vibration 9 also goes to the first information input of the second switch 11. In this case, the parameters of the one-shot 9 are selected by the fact that a single impulse from its output is, as it were, waiting for the arrival of the next sync pulse from the second output of the generator 4 sync pulses. For the duration of the next sync pulse from the second output of the 4 sync pulse generator, the second switch 11 is switched to a single state.

On the falling edge of this sync pulse, the trigger 8 of absolute priority is converted to one. At the same time, at the inverse output of trigger 8 of absolute priority there will be a signal of logical zero, which is fed to the input of block 3 of the microprogram memory. This unit level blocks the issuance of micro-instructions from the third memory block 3. In this case, the output 20.2 of the third memory block 3 will have a logical zero signal. The logical zero signal from the output of the trigger 8 of absolute priority will also go to the third input of the element 15 and bring it to the zero state. The logical zero signal from the output of the AND 15 element will go through the third element OR 12 to the first control input of the first switch 10 and allow the signals to pass through its first information input.

At the end of the emergency interrupt routine, the higher end of output 19.1 of the micro-operations of the second block 2 of the microprogram memory appears at the end of the interrupt routine. This signal arrives at the second information input of the second switch 11. Upon the arrival at the second control input of the second switch of the next sync pulse with

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The first output of the sync pulse generator 4 translates the absolute priority trigger 8 to the zero state, which ensures that the device can return to the main firmware mode.

Further operation of the device occurs according to the law of operation.

Claims (1)

Invention Formula A firmware control device containing three microprogram memory units, a counter, a multiplexer, the first and second OR elements, an AND element, the counter input connected to the address input of the first microprogram memory unit and the address input of the second microprogram memory unit the device is connected to the information inputs of the multiplexer, the outputs of the logical conditions of the second memory block of the microprograms are connected to the group of address inputs of the multiplexer, the output of which is connected the first input of the second element OR, the output of the first element OR is connected to the first input of the element AND, the output of the second element OR is connected to the counting input of the counter, the outputs of the address field of the second memory block of the microprograms are connected to the first group of address inputs of the third block of the microprogram memory, the output of the conditional transition of the second memory unit of the microprogram is connected to the second input of the element I, the outputs of the microoperations field of the second memory unit of the microprograms are the outputs of the device, characterized in that using the scope of analyzing the complex of logical conditions and speeding up, it additionally contains a clock generator, a register of a complex of logic conditions, an absolute priority trigger, first and second switches, a one-shot, a third OR element, and the output field of the address of the first microprogram memory block connected to the first information input of the first switch; the output field of the address of the third firmware memory block is connected to the second information input of the first go switch, output The sign of absolute priority of interrupting the third memory block of the microprograms is connected to the input of the one-oscillator, the output of which is connected to the first input of the third OR element and the first information input of the second switch, the output of element II is connected to the second input of the third OR element, the output of which is connected to the control unit input of the first switch, the second input of the second element OR, the group of information inputs of the register of the complex of logical conditions is the group of inputs of the complex of the logical conditions of the device, group na register outputs complex logic conditions connected with the second group of address inputs of the third memory block firmware and with a group of first OR input group the outputs of the first switch are connected to a group of information inputs of the counter; the output of the end of the absolute priority subroutine is the microoperations field of the second firmware memory block — connected to the second information input of the second switch, the output of which is connected to the trigger input of absolute priority, the output of which is connected to the resolution input of the third memory block microprograms and the third input of the element I, the first output of the sync pulse generator is connected to the synchronization input of the register of a complex of logical conditions and with the second control input of the second switch, the second output of the clock generator is connected to the synchronization input of the counter and with the first control input of the second switch. If.} condoia ycjioSifH Rig.2PCL teln. priority interrupts with a & s0 / gngtnb / m priority (emergency)