JP2867585B2 - Event detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an event detection circuit of a microcomputer development device, and more particularly, to a write event detection circuit that compares an initial value read in advance with a write value.

[Conventional technology]

In recent years, with the diversification of needs and the enhancement of functions, increasing the efficiency of application program development has become a major issue. Therefore, the microcomputer development device is required to have a more strict event detection function for arbitrary data at any address.

As shown in FIG. 9, the write event detection circuit of the conventional microcomputer development device inputs only the address bus signal 32, the data bus signal 33, and the write status signal 34 according to a write instruction to the selector 10 and detects the event. .

[Problems to be Solved by the Invention] The event detection circuit of the conventional microcomputer development device targets an address bus, a data bus, and a write status of an emulation chip as an event detection target. For this reason, there is a drawback in that it is not possible to detect that the value of the write address has changed from arbitrary data to arbitrary data due to a write instruction for the arbitrary address.

For example, in order to detect a case where an arbitrary bit of an arbitrary address changes from “0” to “1”, even if the initial value of the detection bit is “1”, an instruction to write “1” to the relevant bit Executing will cause event detection.

[Means for solving the problem]

An event detection circuit according to the present invention is a copy circuit that holds an initial value of a predetermined write address and an initial value to compare the write value when a processor to be emulated executes a write instruction for a specific address. A circuit for generating a read signal for the copy circuit; a circuit for writing a write value to a corresponding address of the copy circuit when executing a write command for the predetermined address to the copy circuit; And a circuit for comparing the output of the latch with the write value output on the data bus, and a circuit for selectively outputting the output of the comparison circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of a first embodiment of the present invention.

The copy circuit that holds the initial value corresponding to the patent range in the configuration of the event detection circuit corresponds to the copy RAM 5, and the circuit that generates the read signal for the copy circuit is an inverter.
The emulation chip write signal 34 is directly input to the signal of the circuit for writing the write value to the corresponding address of the copy circuit when executing the write instruction in response to the instruction 28.

The latch that holds the initial value output from the copy circuit corresponds to the read data latch 16, and the circuit that compares the output of the latch with the write value output on the data bus corresponds to the AND gates 24 and 25. Correspond to the set event enable signal 52, the clear event enable signal 53, the AND gates 24 and 25, and the latch 8.

FIG. 2 is a timing chart of a bus cycle by a write instruction of the processor for explaining the operation of the block of FIG.

The instruction cycle is composed of three cycles of T1, T2 and T3. The write address bus signal 32 is output to the address bus A15-0 from the T1 to T3 cycles, and the data bus D7-0.
Becomes high impedance in the T1 and T2 cycles, and write data is output in the T3 cycle. Write status signal
34 becomes active in the T3 cycle.

FIG. 3 is a timing chart of signals of respective parts for explaining an event detection operation by execution of a write instruction in the block of FIG.

First, detection event data is written from the supervisor processor 2 to the 25-bit event detection memory 3 via the latch 8, and a set event enable signal 59 or a clear event enable signal 60 is activated as a bit condition to be detected.

When the emulation chip 1 executes a write instruction to the internal hardware of the emulation chip during the user mode, the copy RAM output enable signal 41 becomes active in cycle T2, and the initial data is output from the copy RAM 5 to the emulation chip data bus 33, and the read operation is performed. The data is latched by the data latch 16.

In the T3 cycle, the write data according to the write instruction is output and latched by the write latch 16, and at the same time, the write data is also written to the copy RAM 5.

The clear event detection signal 49 is activated in the T3 cycle when the read data latch output signal 45 and the write data latch inverted output signal 48 are activated, that is, when the initial data is “1” and the write data is “0”. Becomes The set event detection signal 50 becomes active in the T3 cycle when the initial data is “0” and the write data is “1” when the read data latch inversion output signal 46 and the write data latch output signal 47 become active. Become.

That is, when the write instruction is executed, the initial value of the event detection address is latched in advance, the write value by the write instruction is compared with the latched data, the write event detection signal is activated, and the address value of the arbitrary address changes. Can be detected.

 FIG. 4 is a block diagram of a second embodiment of the present invention.

The circuit for comparing the output of the latch of the event detection circuit with the write value output on the data bus and the circuit for selectively outputting the output of the comparison circuit correspond to the event detection memory 4 having a 33-bit input. The other corresponding circuits in the claims are the same as the event detection circuit in FIG.

The difference in operation from the first embodiment is that the initial value and the write value of the event detection address by the write command are previously written from the supervisor processor 2a to the event detection memory 4.

In this embodiment, the write data latch and read data latch output signals 45 and 47, and the ride data latch output signal 47 in the read / write latch block 12 of the first embodiment.
The read / write latch block 12 is simplified because the gate circuits 24 to 26 for inputting the data are unnecessary.

 FIG. 5 is a block diagram showing a third embodiment of the present invention.

The copy circuit for holding the initial value in the claims corresponds to the copy RAM 5, and the emulation chip write signal 34 corresponds to the signal of the circuit for generating the read signal for the copy circuit in this embodiment.

The circuit that writes the write value to the corresponding address of the copy circuit when executing the write instruction for the predetermined address for the copy circuit corresponds to the data latch 14 and the write strobe latch 15 and holds the initial value output from the copy RAM 5. The latch that corresponds to the read data latch 16, the circuit that compares the output of the latch with the write value output on the data bus corresponds to the AND gates 24 and 25, and the circuit that selectively outputs the output of the comparison circuit is Set event enable signal
59, the clear event enable signal 60, the AND gates 24 and 25, and the latch 8.

Next, FIG. 6 shows a bus cycle in accordance with a write instruction of the processor to which the present embodiment is applied. The instruction cycle is composed of two clock cycles. A write address is output to the emulation chip address bus 32 during a write cycle.
Becomes high impedance in the first clock cycle of the write cycle, and write data is output in the second clock cycle. The emulation chip write signal 34 becomes active in the second clock cycle.

Hereinafter, the event detection operation by the execution of the write instruction in the block of FIG. 5 will be described with reference to the timing chart of FIG.

First, data for event detection is written from the supervisor processor 2 to the event detection memory 3 via the latch 8, and a set event enable signal 59 or a clear event enable signal 60 is set as a bit condition to be detected.
Is active.

When the emulation chip 1 executes a write instruction to the hardware inside the emulation chip during the user mode, the emulation chip write signal 34 is output from the emulation chip 1 to the emulation chip data bus 33 in the second clock cycle of the write cycle in which the emulation chip write signal 34 becomes active. The written data is latched by the data latch 14 at the timing when the operation timing signal 37 becomes “0”, that is, at the rise of the emulation chip write timing signal 43.

Similarly, at the second clock cycle of the write cycle, the initial data is output from the copy RAM 5 to the event detection circuit data bus 39, and the operation timing signal 37 becomes "0", that is, at the rise of the emulation chip write timing signal 43. The data is latched by the read data latch 16. Here, as the address for the copy RAM 5 (event detection circuit address bus 39), an address obtained by latching the emulation chip address bus 32 at the rising edge of the operation timing signal 37 is supplied.

On the other hand, at the clock following the write cycle, the event detection circuit write signal 66 becomes active, the data latch 14 outputs the write data by the immediately preceding write instruction to the event detection circuit data bus 40, and the operation timing signal 37 becomes “0”. Is latched by the write data latch 17 at the timing of "1", that is, at the rising timing of the write timing signal 44 of the event detection circuit.

Similarly, at the timing when the event detection circuit write signal 66 becomes active at the next clock of the write cycle,
Write data is written to the copy RAM 5. The clear event detection signal 49 is output when the read data latch output 45 and the write data latch inversion output signal 48 become active, that is, when the initial data is “1” and the write data is “0”, It becomes active when the clock operation timing signal 37 becomes “0”.

The set event detection signal 50 is output when the read data latch inversion output signal 46 and the write data latch output signal 47 become active, that is, when the initial data is “0” and the write data is “1”, It becomes active when the clock operation timing signal 37 becomes “0”.

 FIG. 8 shows a block diagram of a fourth embodiment of the present invention.

The circuit for comparing the output of the latch with the write value output on the data bus and the circuit for selectively outputting the output of the comparison circuit in the claims correspond to the event detection memory 4. The other corresponding circuit of the claims is the third circuit.
This is the same as the embodiment.

The difference from the third embodiment in the operation is that the supervisor processor 2a writes the initial value and the write value of the event detection address by the write command to the event detection memory 4 in advance.

In this embodiment, the read / write latch block 12 in the third embodiment is simplified.

〔Example〕

 Next, a fifth embodiment of the present invention will be described.

First, FIG. 12 shows a bus cycle according to a write instruction of a processor to which the present embodiment is applied. The instruction cycle is composed of two clock cycles. The write address is output to the emulation chip address bus 280 during the write cycle, and the emulation chip data bus
The reference numeral 290 indicates that the impedance becomes high in the first clock cycle of the write cycle, and the write data is output in the second clock cycle. The emulation chip write signal 300 becomes active in the second clock cycle.

FIG. 10 shows a block diagram of a fifth embodiment of the present invention.
The copy circuit corresponds to the copy RAM 500, the circuit that generates a read signal for the copy circuit corresponds to the OR gate 160,
In the present embodiment, the circuit for writing the write value to the corresponding address of the copy circuit when executing the write command for the specific address to the copy circuit has no special circuit in this embodiment, and directly connects to the emulation chip data bus 290. The latch that holds the initial value output from the copy RAM corresponds to the read data latch 130, and the circuit that compares the output of the latch with the write value output on the data bus is AND
The circuit corresponding to the gates 180 and 190 and selectively outputting the output of the comparison circuit corresponds to the set event enable circuit 51, the clear enable signal 520, the AND gates 180 and 190, and the latch 800.

Hereinafter, the event detection operation by the execution of the write instruction in the present embodiment will be described with reference to the time chart of FIG.

First, the supervisor mode status signal 200 is "1"
During the supervisor mode, the event detection memory is transmitted from the supervisor processor 200 via the selector 110.
Event detection data is written in 300, and a set event enable signal 510 or a clear event enable signal 52 is activated as a bit condition to be detected.

When the emulation chip 100 executes a write instruction to the hardware inside the emulation chip during the user mode in which the supervisor mode status signal 320 becomes “0”, the operation timing signal 310 becomes “0” in the first clock cycle of the write cycle. At the timing, that is, at the timing when the event detection circuit read timing inversion signal 400 becomes “1”, the initial data is output from the copy RAM 500 to the emulation chip data bus 290, and the event detection circuit read timing inversion signal 40
The data is latched by the read data latch 130 at the fall of 0.

On the other hand, in the second clock cycle of the write cycle,
Write data according to a write instruction is output from the emulation chip 100 to the emulation chip data bus 290. Here, when the operation timing signal 310 becomes “0”, that is, the event detection circuit write timing inversion signal 410 becomes “1”, the emulation chip data bus 290,
Emulation chip inverted data bus 470, set event enable signal 510, clear event enable signal
Depending on the state of 520, the clear event detection signal 480 or the set event detection signal 490 becomes “1”.

At the same time, write data is written to the copy RAM 500 at the timing when the event detection circuit write timing signal 370 becomes active.

The clear event detection signal 480 is output from the read data latch output 450 and the emulation chip inversion data bus 470.
Becomes active, that is, the initial data is “1”
When the write data is "0", the operation becomes active when the operation timing signal 30 in the second clock cycle of the write cycle becomes "0".

The set event detection signal 490 is output from the read data latch inverted output 460 and the emulation chip data bus 290.
Is active, that is, the initial data is “0”
When the write data is “1”, the operation timing signal 300 in the second clock cycle of the write cycle is “0”.
It becomes active at the timing.

FIG. 11 shows a block diagram of a sixth embodiment of the present invention.
The circuit for comparing the latch output with the write value output on the data bus and the circuit for selectively outputting the output of the comparison circuit correspond to the event detection memory 400. The other corresponding circuits are the same as in the fifth embodiment.

The difference from the fifth embodiment in the operation is that the initial value and the write value of the event detection address by the write command are previously written in the event detection memory 4 from the supervisor processor 2.

In the present embodiment, the gate circuit which receives the write latch, the read latch output bus, and the write latch output bus in the fifth embodiment as input is not required.

〔The invention's effect〕

As described above, in the present invention, the event detection circuit latches the initial value of the event detection address in advance when executing the write instruction, compares the write value by the write instruction with the latch data, and Is active, it is possible to detect that the value of the write address has changed from arbitrary data to arbitrary data by a write instruction for the arbitrary address.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIGS. 2 and 3 are timing diagrams of signals of respective parts for explaining the operation of the block of FIG. 1, and FIG. FIG. 5 is a block diagram of a third embodiment of the present invention, FIGS. 6 and 7 are timing diagrams of signals of respective parts for explaining the operation of the block of FIG. 5, FIG. 8 is a block diagram of a fourth embodiment of the present invention, FIG. 9 is a block diagram of an example of a conventional event detection circuit, FIG. 10 is a block diagram of a fifth embodiment of the present invention, and FIG. FIG. 12 is a block diagram of the sixth embodiment, FIG. 12 is a write instruction time chart of the target processor of FIGS. 10 and 11, and FIG. 13 is a write instruction time chart of the fifth and sixth embodiments. is there.

Claims (1)

(57) [Claims] A copy circuit for storing an initial value of a predetermined write address and an initial value for comparing the write value when a processor to be emulated executes a write instruction for a specific address; A circuit for generating a read signal for the copy circuit, a circuit for writing a write value to a corresponding address of the copy circuit when executing a write command for the predetermined address for the copy circuit, and an initial value output from the copy circuit And a circuit for comparing an output of the latch with a write value output on a data bus, and a circuit for selectively outputting an output of the comparison circuit.