SU1711170A2 - Device for controlling information transfer of computer and group peripheral devices - Google Patents

Abstract

The invention relates to computing and radionavigation, can be used in receiver-indicators of satellite navigation systems and is additional to the invention according to the author's certificate Ms 1640700. The purpose of the invention is to expand the functionality of the device by providing the ability to exchange information without taking into account the priority of external devices. The goal is achieved by introducing a group of exchange control blocks into the device containing the priority selection block, the switch, the exchange register and the address decoder, each of which contains an AND-NOT element, a write register, two triggers, a comparison circuit, an exchange decoder, the element NOT a data switch. 1 il.

Description

The invention relates to computing technique and radio navigation, can be used in receivers of satellite navigation systems, and is additional to the invention in accordance with the authors. St. No. 1640700.

The purpose of the invention is to expand the functionality of the device by providing information exchange without taking into account the priority of external devices.

The drawing shows a functional diagram of a device for controlling the exchange of information between a computer and a group of peripheral devices, which contains a group of communication control blocks between a computer and a group of external devices (one exchange control block is shown).

The drawing shows the address decoder 1, the computer 2, the exchange register 3, the switch 4, the priority selection block 5, the peripheral registers 6, the peripheral

device 7, parallel to bus 8 of the number code (computer command output group), control signal circuit 9 (gating computer output), interrupt circuit 10 (computer interrupt output), information reading circuit 11 (computer reading output), information bus 12 parallel exchange (a group of information inputs of a computer), parallel buses 13 and 14 of control (groups of inputs and outputs of the address decoder), information recording circuit 15 (first write output of a computer), bus 16 of parallel exchange of information between devices 7 and switch 4, bus 17 of parallel information sharing (first group of computer information outputs), group of information buses 18 and 19, information recording circuit 20 (second computer recording output), information bus 21 of parallel information exchange, query circuit 22 (query input of block 5), query circuit group 23 (group of inputs request block 5), chain 24

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operation resolution (output resolution of unit 5), group 25 of operation resolution circuits (group of output permission of operation block 5), information bus 26 of parallel information exchange (second group of computer information outputs); In addition, the device contains a group of exchange control blocks 27 each of which contains the element I / 1-HE 28, the record register 29, the first trigger 30, the comparison circuit 31, the exchange decoder 32, and has a control circuit group 33 for connecting the output group of the decoder 32 to the device inputs 7 and the data switch 34. Block 27 also contains a second trigger 35 and has information buses 36 and 37 for connecting the outputs of the register 3 to the information inputs of the register 29 and the outputs of the switch 34 with a group of 12 computer inputs. A control circuit 38 connects the output of circuit 31 to a computer ready input. Circuits 39 and 40 connect the output of the computer operation permission and the output of the sign of the computer address to the inputs of the NAND element 28. The information recording circuit 41 connects the third recording output of the computer to the input of the register entry 29. The address bus 42 (group of address outputs of the computer) is connected to the first group of information inputs of the circuit 31. Block 27 also includes an NOT element 43, the input and output of which are connected respectively to the output of the circuit 31 and the installation input of the trigger 35. The installation input, the reset input and the output of the trigger 30 are connected respectively to the output of the NAND element 28, first at the output of the decoder 32 and the control input of the circuit 31. The information outputs of the register 29 are connected to the second group of information inputs of the circuit 31 and the groups of information inputs of the decoder 32 and the switch 34, the control input of which is connected to the output of the circuit 31. The reset input and the output of the trigger 35 are connected respectively, with the second output and the control input of the decoder 32.

The device works as follows.

Each block 27 is assigned its own address code, which is permanently formed in the device and supplied via bus 42 to the inputs of circuit 31. The address code is assigned to block 27 at the device design stage and can be changed if necessary. In order to select the control unit 27 for the group of peripheral devices with which information is exchanged, the computer on bus 17 sets the code of the address and recording signal transmitted over circuit 15, writes it to the exchange register 3. From the output of the exchange register 3, the address code for the buses 21 and 36 with the help of the control signal supplied through the circuit 41 is rewritten into the register 29 of the control unit 27, With the output

register 29, the address code is fed to a group of inputs of the circuit 31. The computer sends the work enable signal (upper level) to the first inputs of the AND-28 elements of all blocks 27 and the circuit 40 to the second inputs

0 elements AND-28 are the code comparison resolution signal. At the output of the AND-28 element, a low level signal is generated, which is fed to the setup input of the trigger 30 and sets it to the state when

5 of which, at the output, a top level signal is generated allowing the comparison of codes. In the presence at the control input of the circuit 31 of the enable signal from the output of the trigger 30, codes are compared

0 addresses arriving at the information inputs of the circuit 31. If the address codes are equal, then the output of the circuit 31 generates a signal of the upper level, which is fed to the control input of the switch 34 to enable broadcasting via the switch 34 to the input of the computer via the code response bus 37 addresses; to the input element HE 43 to form at the output of the lower level of the signal to set the trigger 35 on a single input to

0 a position in which a low level signal is generated at its output allowing the operation of the decoder 32 (this signal from the output of the trigger 35 is fed to the control input of the decoder 32); on chain 38 in

5 computer as an information signal that block 27 has performed an operation on comparing address codes and issued to the input of a computer on the address response bus 37.

The computer, having received a signal on the circuit 38, performs an analysis of the address response to clarify the correctness of the choice of block 27 by a group of peripheral devices with which information is exchanged. After completing the analysis, the response of the computer goes

5 to the following operations: removes from the circuit 40 the address comparison resolution signal; sets on the bus 17 command code; according to the recording signal received via the circuit 15. writes the command code to the exchange register 3; according to the control signal received via the circuit 41, it rewrites the command code from the exchange register 3 to the registers 29 of the blocks 27.

The instruction code from register output 29 goes to input to decoder 32, where it is decrypted as a low level signal at the first output. The signal from the first output of the decoder 32 is fed to the reset input of the trigger 30 to reset it.

The operation of the peripheral devices 7 is controlled by a sequence of commands received from the computer, which are determined by the decoder 32, and from its output by the lower level control signals along the circuits 33 are fed to the inputs of the actuating elements of the peripheral devices. The initiator for the exchange of information with any peripheral device of the group (without taking into account their priority) is a computer. The ready-to-receive signal, or an interrupt signal for transmitting information only from the peripheral device to which the operation permission signal was received from the central computer processor, is transmitted to the input of the priority selection unit 5. Further operation of the device for managing the exchange of information is similar to the operation of the known device.

If the central processor of the computer has issued a control signal to allow simultaneous operation of all peripheral devices of the group, then the exchange between the processor and the peripheral devices is based on their priority, according to the algorithm described in the well-known invention. After the exchange of information with a group of peripheral devices is completed, the central processor of the computer writes to the register 29 another command, which is decoded by the decoder.32, and at its corresponding output a lower level signal is generated, which is fed to the second trigger input 35. At the trigger output 35, a high-level signal is set which is fed to the control input of the decoder 32 to disable the decoding of instruction codes. After this operation, the operation of the central processor of the computer with this block 27 is terminated.

Claims (1)

The invention is a device for controlling the exchange of information between a computer and a group of peripheral devices according to the author. St. No. 1640700, characterized in that, with the aim of expanding the functionality by ensuring the exchange of information without taking into account the priority of external devices, a group of exchange control blocks is entered into it, each of which contains an element. AND –NE, a write register, two triggers, a comparison circuit, an exchange decoder, an NOT element and a data switch, group of outputs which forms a group of device outputs for connecting to a group of information inputs of a computer, a group of outputs of an exchange decoder forms a group of device outputs for connecting to inputs of the peripheral mode of a group, a group of information inputs of a recording register is connected to a group of information outputs of an exchange register, the output of the comparison circuit is the output of the device for connecting to the readiness of the computer, the first and second inputs of the element AND-NOT are the inputs of the device for connecting respectively to the output of enabling the computer to work and the output the sign of the address of the computer, the entry of the recording of the register of records is the input of the device for connection to the third output of the recording of information of the computer, the first group of information inputs of the comparison circuit is a group of device inputs for connecting to a computer address output group, a setup input, a reset input and a first trigger output are connected respectively to the output of the NAND element, the first output of the exchange decoder and the control input of the comparison circuit; the information output register group is connected to the information input groups exchange decoder and data switch and second the group of information inputs of the comparison circuit, the reset input and the setup input and the output of the second trigger are connected respectively to the second output of the exchange decoder, the output of the NOT element and the control input of the exchange decoder, and the output of the comparison circuit is connected to the control input of the NOT element.