SU674025A1 - Microprocessor computing system - Google Patents

Description

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The invention relates to the field of computer maintenance and can be used in one of the various applications.

Microprocessing computations with tight control are known (1 | and 2, containing an arithmetic-logical unit, .register® block, instruction decryption unit, information exchange units, a source register and a sync signal distribution node. However, the increase in the size of the Grade information processed and such microprocessor-based computing systems leads to a significant reduction in their speed, in changing its command system is impossible.

Also known is a microprocessor-based computing system with a microprogram {i1sh 1M vp control, containing the same type of device for performing flakes in the same type of microprogram microprocessor device) for laziness, each device of the same type for performing operations containing an arithmetic-logical unit, a shifter.

. result register, status register; register of microinstructions, decoder of microoperations, information exchange units, connected to bi-directional information machines, and a block to a general purpose register, the output of an arithmetic-logical block through a buffer register is connected to the shift input, the register input of microinstruction is connected to the control bus, and the output - to the entrance of the microsurgery unit; each firmware control device of the same type contains serially connected block of programmable addresses and block of microcommands, group prog1 | i1m1 ruoShh YLy 1ento & NOT, the feedback register whose paraphase output is connected. to the first group of inputs of the block of programmable addresses, and the information input through the first group of programmable elements of NOT connecting with the first output of the microcommand memory block, the second; the output of which through serially connected second group of programmable elements H13 and read killers is connected to the output of the device. The main disadvantages of this microprocessor computing system are a significant number of additional circuits in the final microprocessor. 1 numerical system, necessary for generating such clock signals, for organizing the logic of conjugation and synchronization with other PC and computer units; decrease in the speed of the previous expansion of the randomness of the aggregate; The devices of the type of device are outputted to the parallel processor unit by the dfet of the sequential passage of the transfer signals; the lack of functional flexibility of one-type microprogram control device to expand the microcommand size and increase the volume of microcircuits. The aim of the invention is to improve the performance, flexibility, restructuring and expansion of the functional capabilities of the system. This is achieved by the fact that each unit of operation of the proposed system has an extension node, psaws of resolution, autonomous exchange control units, and a work cycle shaping unit, the launch input is connected to the control input, bji input and outputs, respectively, connected to the inputs and device slots and one-sixth inputs and outputs of other devices for performing operations, the first control input is connected to the corresponding output of the arithmetic-lgioic block, two outputs of which are expanded through the node and a bit; they are also connected to the corresponding inputs of the device and to the corresponding outputs of other operation devices, the autonomous exchange control units are connected to the corresponding inputs and outputs of the device and to the corresponding inputs and outputs of other devices that control the inputs system outputs and outputs, the output of each node of the autonomous exchange control is connected to the control input of the corresponding information exchange unit, the control inputs of the connection with the corresponding mikroopera decoder outputs (and outputs tions forming unit which Started cycle, the second control input E Ko cho ShvSh oy e d botvbTeotvuyuschym yield eshifragora microoperations obmsha block outputs information inputs BpoCom obschetche destination registers and result registers / ayhod sdaygatel first and a first input the state register is connected to the first information bus of the device, the inputs of the first and second information exchange units, the output of the result register, the first output of the general purpose register unit, the first input of the arithmetic the logic unit and the first output of the status register are connected to the second information bus of the device, the input of the third information exchange unit is connected to the second output of the status register, the second input of the device is connected to the second output of the slider connected to two-way communication with the node which is connected with the control inputs and outputs with the corresponding inputs and outputs of the device, s; 1; the codes of the decoder of the microoperations and the working cycle shaping unit, the output of the MSrc command register and in the mountain od general purpose register block soedynen the second input arithmetic and logichesn. control unit inputs of the microinstructions register are connected to the corresponding outputs of the operating mode block; the control inputs of the stand-by register, the bit expansion unit, the general-purpose register block in the result register are connected to the corresponding outputs of the micro-operations decoder and the block forming a working cycle, the output of which is connected to the control input of the buffer register, the control input of the arithmetic-logical unit associated with the corresponding output of the micro-operation decoder, and in each device for firmware control of commutators, the registers, informational inputs of which are connected to the sorting - by the looping inputs of the device, and the parafaan outputs are connected to the second group of inputs of the programmed address, the job setting unit of the cycle, the control input is connected to the Control input of the device, nodes autonomous control of receiving information, the first output of each of which is connected with the control input of the corresponding register and with the corresponding input of the cycle setting unit, the output which are respectively connected with the control inputs of the read amplifiers, the feedback unit and the programmable address register, third and fourth outputs of the memory block of microinstructions through the switch soo1vetstvenno connected with the control inputs of the read amplifiers and regist-. feedback, with pens, 1 inputs of autonomous control units receiving information, the second and third inputs and outputs of each of which are connected respectively to the inputs and outputs of the device and with the corresponding inputs and outputs of other devices of the microprogram control, the second input and output of each the autonomous information reception control node is connected to the corresponding information transmission control buses, and the third input is connected to the control input of the system ,. The fourth output of the memory block of micro-commands is connected to the corresponding input of the work cycle task block. Fig. 1 is a block diagram of a device for performing operations of the described system; in fig. 2 - time diagram of the microcommand execution cycle; in fig. 3 is an example of a device connection. performing operations; in fig. 4 - block scheme of the firmware control device; in fig. 5 - temporal diarram of the micro-command sampling club in the micrographic control unit; in fig. 6 is an example of connecting firmware control devices; in fig. 7 an example of building a microprocessor-based numeral system. The device for performing operations (see 4 "d. 1) contains the micro-command register 1, the micro-operation decoder 2, the general registers block 3, the arithmetical-occoding OK 4, the buffer register 5 for temporary storage of the result of the arithmetic or logical operation shifter 6, extension node 7 bit register, 8 state register, result register 9, duty cycle forcing unit 1, information exchange blocks 11-13, for apg 14–16 autonomous exchange control, internal Hbie information pieces 17 for 18 readings, internal information bus 19 records and ynfs mation in an internal bus 20 records controlled conditions. The input of micro-command register 1 is connected to the control bus (input 21), through which the register receives control information (micro-command bits) for temporary storage during its execution in the device, and the registration output 1 is connected to the input of the decoder 2 microoperations and outputs which are connected to the control inputs of the remaining nodes and tuning these nodes to execute certain types of micro-operations. The read information bus 17 combines ne ffibie outputs of block 3 of general purpose registers, outputs of result register and status register 8, and inputs of blocks 11 and 12 exchange information connected to external bidirectional information buses 22 and 23, respectively. The information bus 18 of the schigshan combines the outputs of a certain part of the bits of the register 1 microinstructions and the second outputs of the block 3 of the registers common to “-. value. Inputs of block 4 are connected by tires 17 and 18, along which two operands are fed into the block. Block 4 contains an asynchronous transfer node between parallel bits, having two inputs connected to pins 24 and 25, d two outputs that are connected to pins 26 and 27 via node 7. The transfer code is sent to two bits, on two latencies, the generated transfer code is issued from the higher bit of block 4. Incoming code. transfer has the following meanings: O1 - transfer is equal to O; 10 - the transfer is equal to 11 - waiting for the transfer. The execution time of the arithmetic operation in block 4, containing the asynchronous transfer node, depends on the operand codes and varies from the maximum value, equal to the sum of the transfer formation times in all bits of the asynchronous transfer node, to the minimum, equal to the transfer formation time to one. asynchronous transfer unit. The use of an asynchronous transfer node allows not only to increase & the performance of an arithmetic operation, but also to fix the end of it (for example, transfer in all digits of the device) in each device independently of the others, in parallel: x with it. The output of the asynchronous transfer node, the fusible end of the operation, is connected to one of the inputs of block 10. The result of the operation performed in block 4, including the transfer bit, is fed to the information input of the buffer register 5 for temporary storage, the output of which is connected to the input of the shifter 6. The shifter 6 has completed shifts1 left and right for one bit and wed (Ut with pins 24 and 25, and through node 7 - with pins 26 and 27, according to which shear bits are received and issued during the: shift operations, sdvvgatel 6 There are, moreover, a number of controllable states, such as Sign, Overflow, Transfer-Loan, Result Zero, Shift Bit, Parity of Result, etc. The output of Shift 6, associated with the issuance of control states, is connected to bus 20, and the output associated with the issuance of the operation result, to bus 19. Register 8 has two recording directions, the first of which is EE occupation of 1 & Pyusyu controlled state, and the second recording information on the bus 19. By uikne 19 there is or recording the result of the input from the shifter 6, or the recording of information received and is through blocks 11-13 in the data receiver information on the bus receivers 19 L c1 register 9 are the result of .lyuboy; block 3 and register 8. Information is transmitted through blocks 11 and 12 from information sources connected to bus 17, i.e. from registers 9 and 8 and from any register of block 3. The output of information tm to the external bidirectional formation bus 28 occurs through the exchange block 13 from the state register 8, Uz1 & | 14-16 autonomous control of the oeivie M uravay yu asy ah {ySHY mryomom and asynchronous sh.shcha information through the appropriate, connected with the nimn-blocks 11-13 exchange. Each of the nodes 14-16 autonomous) control exchange; 1 (1b is associated with dual external down-right terminals and a module, respectively 29 and 30, 31, and 32, 33 and 34. According to 29w, 31, 33 and 33, an inforkl & t is received during reception indicating the presence of informatin on the corresponding bi-directional information tires 22,23 and 28. According to conclusions 30, 32 and 34, the receptionist’s acceptance policy is received and a sign is received during the issuance indicating the end of the reception of the updated information and, thus, the corresponding information exchange block from the external highway. Conclusions 30, 32 and / 33 are connected to the inputs of the unit 10. Each of the autonomous exchange control node has the same input and dongle connected to the internal unit “m of a driver and amp; s. Two ports of the module are connected with the outputs of the decoder 2 microoptions || Decoding availability Signs of reception or issuance through the appropriate exchange unit in the designated microcommand. The second two inputs are connected to the outputs of block 10, LH-briggs are the source of signals

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-. 5.., Ite .-. R-.i.,. Receiving or receiving information through this exchange node. The outputs of nodes 14-16 of the autonomous exchange control are connected to two control inputs of the coexistent exchange block 11-13 and open or output gates at the time of receiving or issuing information, e, which is connected to the corresponding 1-way data busses 22 , 23 and 28. The duty cycle shaping unit 10 is connected to three external terminals 3537 of the device. Conclusion 35 aapu.osa obn. With a signal source that intimates new sequence of sync signals. You j 36 and 37 synchronize each other. In this case, the microcommand is executed in several single-parallel ones. Typical devices of high performance operations. 37 also synchronizes the sampling of microcommands from the same type of firmware control devices. The sequence of sync signals, processed by block 10, consists of a sync signal for the arrival of a micro-command in register 1 microcomponent, a sync signal for the information program through one of the blocks 11–13. the exchange of bus 19, the read clock sync of operands on bus 17 and 18 in block 4 in the no. of the operation in it, syncally recording the result of the operation and controlMebix into information receivers of 20 and 19. With the sign of receiving information in the microinstruction and sequence code sync signal about trigger signal receiving information. The output of block 10, associated with the microman reception clock signal; dy (output 38), / is connected to the input. SanchroNizatsiya register 1 micro-commands. The output of block 10, associated with the read synchronization signal (output 39), is connected to the 4th operand of the result register 9, the 8 state register, the general purpose register 3 block, the 1: MSfocomid register, the synchronization input at-. Ema in rgm 5 and to the node 7 of the expansion of the discharge. The outputs of unit 10, which is connected to the information receiving sync signal (output 40) via external highways and the synchronic signals of the recording of the operation result (output 41), are connected to the sncro inputs. For information on receiving information from register 9, register 8, registers in block 3, as well as with node 7, the expansion of the size and nodes 14-16 stand-alone, control exchange. The output of block 10, associated with the mask feature (clock 42 / sync. Receiving anformadi and recording the result of the operation, is connected to the masking registers 9 and 8, the registers in block 3 and to the control input of the node 7 expanding, rendering the distribution path. Output 42 of block 10 functions when the following conditions are met: the previous microcommand cycle is completed, the initiating signal at pin 35 did not occur, but there were changes in the potentials at pins 36 and 37 associated with the operation of the GO blocks of other devices connected in parallel with it performed Operations. At the same time, in block 10 of the processor module, the coRP {N did not receive a signal at the 35-start output, 1 select all sync signals 11 and the corresponding potential changes® on pins 36 and 37, but a mask is applied to the sync signal for receiving information from the external directional signal information buses 22, 23, 28 .and to the result recording clock signal. Node 7 is designed to extend the bit of the device for performing operations. One of the inputs of the node 7 is connected to, and the water supply 43, which {x 1st is the external pointer to the higher order in the process block, is in the state of several devices of the same type for performing operations. A higher logical module at pin 43 is set to a certain logical level: (ень or)) from the raised link to. When performing arithmetic operations: walkie-talkies to Conclusions 26 and 27 of the crepmiero device w, the corresponding transfer code is determined, determined by the type of operation performed by the device. When performing logical operations, for example, the logical burner for the higher bits, node 7 in the older device, on the output, outputs 26 (in the slowdown, shift 6 of the youngest device 1® in the processor unit) logical O. O. One of Wela 7 inputs (hyudinen with output of block 10, When a mask appears at this output, H1eauavi "from logical level to output: 43 node 7 in this device functions as in a senior device" prote "of the trash block. This allows you to execute 1metical and shear operations in - About groups of devices of the same type are completed in the operations of the processor block. In FIG. 2, a time gram is given, which explains the chit & MHs: rooks in the device of the execution of operations on 4sg. 1. The beginning of the cycle is connected with

/ G by coincidence of two necessary conditions: the end of the recording sync signal in the previous cycle and the presence of a trigger signal 44 from the signal source associated with pin 35. The coincidence of these conditions causes a negative 4th pin at pin 36 and then a successive change in the potentials at pin 36 and 37, connected with the generation of the necessary sequence of the sync signals of block 10. The first 4-flint 46 micro-command clock sync signal occurs immediately after the end of the recording sync signal in the previous cycle, 3 (the outer 47 sync signal and a micro-command occurs after fixing the time counted from "feJOHTa 45 in block 10, the front 48 sikhroshama reception of information occurs directly after the front 47 when the service ends or no output information in the previous 1M cycle, Transmission 48 opens the corresponding message. and at the site of its automatic control for receiving information and 1fizyaka, identifying the availability of information on the down-transmission information buses. From the reception of a negative 49 sign, a fixed time is counted in the internal block 10 to the occurrence of a positive front 50 at pin 36, Frdsdat 50 back (51 synchromesh reception of information, negative 52 signs ordering at the end of reception of the information, negative negative, 53, Conclusion 37 and the front panel of the sanhsigal of reading 54. If there is no reception of information from the outside in the code of the microcontrol that has been prompted by the microcommand, there is no synchro signal for receiving informational space in the code 10, and the unit has Potential potentials on Pins 36 and 37 occur immediately after the micro-command receive sync signal when the termination condition is fulfilled OR there is no information output in the previous cycle, ... ... Frong 52 you are 1 self-signed in the external source 55 positive, 55 and closing the information output gates. The front 55 forms in the device a positive 56 response sign in the device, signifying the end of the exchange on reception. A positive 57 signal at pin 37 synchronizes the completion of the arithmetical, logical sludge transfer operation. For hygienic and forwarding operations, the completion of operations is associated with a fixed time base, which is deducted from the front of the 53, and for arithmetic operations associated with asynchronous transport, the completion time counted from the front 53 depends on the number code that depends on the code transfer, the end time counted from the front 53 depends on the number code that depends on the code transfer. an arithmetic unit of a co-operative unit 4, and is generated by an AS-chip transfer unit in this unit. Front 57 snaps the front edge of the 58 read clock, the front (ont 59 syncray recordings and the negative front 60 signaling at pin 36. Strokeful 4f 61 signals at the output of the BoiShMkae output of 6 after some time, as a result of the result of the process. , and causes a falling front 62 of the write signal, the front 4th 46 of the next: I received the reception of the next Mike) OK (3 commands. At the same time, the information output through one of the blocks 11-13 of the exchange 61 opens the output of the H1b valve corresponding The second measurement unit forms the negative front 63 of the feature, i identifies the information received. This information output is combined with the reception of the next control unit in the operation unit and continues until the negative response 64 from the external receiver of the information appears on the iia one of the findings of the control unit, and 34, sveta aaa "s with a corresponding node of the exchange control. The negative front forms a positive front 65 recognizes". 1 ka, identifying issued nnformShik, and closed exit in) entyli in rotting unit exchange. Front 65 Reinforces the “j oHT 66 in the external information receiver, which determines the end of the exchange for issuing information. FIG. Figure 3 shows an example of the construction of a hfporessor block of four yci devices 67–70, the execution of operations. One; common pins. 36 and 37 of all devices for performing operations are combined. Conclusion 2 Shesh tg with -Shvsh Zhtusus, iKOTopoe is the oldest, in the Yabzhen-ibn. Different from the position of like-pin in tfugi devices, i.e. obedo, for example with a ground tire. Pins 24 and 25 of each device are combined with pins 26 and 27 of the neighboring device, forming a ring connection of all four devices. Similar conclusions 29-34 of all devices are combined. The outputs of 28 of all devices are located on the bottom and form a common state highway. The same name pins 35 are combined in devices / ax 67 and 68, 69 and 70, forming two groups in the processor unit. It allows you to send the triggering signals of separate initiation over half words in a separate group (the word size is equal to the size of the processor unit). Pins 36 and 37 perform the function Wired I. This allows the combined facilities to synchronize the end of the reception inrm, the end of the recording and the beginning of the output of the information. The firmware control device (see Fig. 4) contains input registers 71 and 72, informational inputs of the transponders with outputs 7 3 and 74 devices, nodes 75 and 76 of autonomous control of asynchronous reception of information in them, sequentially connected block 77 gfogram. micro-command memory block 78, a group of programmable elements NOT 79, read output amplifiers 80, reverse register 81: link tf, a work cycle assignment block 82. Blocks 77 and 78 consist of a series of horizontal lines (rows) and a series of vertical busbars (columns), in which there are valve elements (a diode, a transistor) that crosswire the software between them and programmMbte. To the inputs (lines) of the block 77 there are paraphase outputs of the registers 71, 72 and 81. The outputs of the block 77 (column) are connected to the inputs (lines) of the block - - 4. 78, the outputs (columns) of which, in turn, are combined from the input of the 1st group of programmable elements NOT 79. The group of programmable elements NOT 79 either translates the logic level to the corresponding output of the matrix 78 or inverts this logic level. The output, output amplifiers 80 readouts are a set of powerful output amplifiable Cascades having separate information inputs connected through a group of programmable elements HE 79 with a certain part of the block 78, and common gate and masking inputs. The gate input is connected via output 8 3 devices with one of the outputs of block 82 of the task cycle operation. The outputs of the read amplifiers 80 are combined with the terminals 84 of the device and

13 allows the logical function of Wired And, the second part of the outputs of block 78 to be performed through a group of 79 elements of the interface with information inputs of the register 81 of the communication link. The third part of the outputs of block 78 are four service bits 85-88 of the long-range code, two of which (85 and 86) are signs that determine the need to receive information, respectively, in regisgra 71 and 72 before fetching the code of the following microcommand, and the next two bits 87 and 88 are signs of black. The output of bit 87 is combined with the masking input of the amplifiers 80 sci-shanni. .-. ; ; .--..::-::- The register 81 of the feedback, except for the synchronization input receive, in common with one of the output of the block 82, has an input that masks the reception of information. him This input is connected to the output with a zhezbnog discharge 88. Each of the nodes 75 and 76 of the autonomous control of receiving information into the register is combined with a fourth output of 89–92 and 93–96 of the control unit. Conclusions 89 and 93 are connected to the sources of external communications installed on pins 73 and 74 from the outside. Signs of the need to receive information into the registers controlled by them. Conclusions 90 and 94 are connected to the sources of external sources,. identified {to shshs availability of information on the 73 and 74 shdovdah. Conclusions 91 and 95 are connected, to the internal sources 0, nodes 75 and 76, forming ogvvvye with “at the end of the reception of information. At pins 92 and 96 are set by nodes 75 and 76, read the usability, decisive reception with {1Gnals® by pins 90 and 94. Pins 9 and 96 when combined with the same pins of other devices. firmware control itor logic function Conducting And and are designed to simultaneously receive signals from pins 90 and S4 and, a) 6m1. ”identifies information that they identify in several ways in parallel to the connected devices ..: Each of the nodes 75 and 76 receive information signal sync Which arrives at the synchronization input for receiving the register used by this node into one input of block 82. In addition, the input of node 75 is combined with the output of the service code 86 micro-command code that is a sign of the need to receive information in p Registry 71. Analogue14

/ 5Г jHo input node 76 is combined with the output of service bit 85, which is a sign of the need to receive information in register 72. The duty cycle setting unit 82 is connected via pin 97 to an external source signal of the firmware control device. One of the outputs of block 82 is combined with the cracking input 98 of block 77; in with the input of an additional (dummy) element in this block. The output of this element through the inverter is combined with the strobe (INPUT 99 and the input of an additional (fict JTHBHOro) element of block 78. The output of this second element is connected to input 82,.,; -. X- ;;;, ..-: /; Additional elements are not they perform logical functions and are intended for models and: in nepiexoms ix processes, they pass through the blocks in. One | 1ga of the inputs of the 8: 2 block through the output 10 of the device is connected to the external signal that allows the information to be received from the device. This will eventually (cascadeally) connect mic | X devices of software 5GB of control to increase the depth of the MHKponofnnPoStsMM of the function of the macroprogram control unit.::. . :. -. On phage 5, a time diag {{5}, p6o: yy1ts yzhl sample code of micromashs in the microprocessor control device is presumed. Cycle No. hborkn includes the stage of receiving information in the input registers; The 1st regenergical blocks 77 and 78, the stage of the first, second, and final stage of the stage: you are: The dachk formed by the CBD micro-command. The regeneration of blocks is necessary for the dynamic storage of information in the NTC (for example, in: matrices; implemented in CMOS technology, “stores information circuits; with during the time of the ILI; and on internal parasitic capacitances). The reception and recovery stage begins with the arrival of the signal front edge 101 on the link 97. The front 101 forms in block 82 a negative front 102 of a snifth output at output 83, a front SW of a receive sync signal to register 71 at node 75, a leading edge 1O4 of a receive clock signal in register 72 6 node 76 and a leading front 105 of a sync signal fed to the gate input of block 77. The front 103 establishes at node 75 a log level that permits the right of 1O6 upon a sign coming in on pin 90, and in1, 6740 15., formations that are fed to the inputs of the register 71. Similarly, 4rong 104 in the middle 7b decides the reception of the negative front 107 of the sign entering at about 94. The enable output logic levels on leads 92 and 95 s are set when the terminating condition pred1duscheg6 exchange for receiving a respective registers. After a certain time, counted in the autonomous reception node 75 from the input of the front 106, the falling edge 108 of the receive sync signal in the register 71 and the negative front 109 of the response signal arriving at the output 91 are formed. Front 1O9 causes a positive 4-line 110 of the signal at pin 90, which in turn, at node 75, has a positive front 111 wave signal. Similarly, at node 76 20, the rear 112 sync beacon signals in register 72 and the negative are formed; at the output of 95, which causes a positive front 114 on output 94, which in turn forms a positive front 115 on output 95. The front 105 regenerates the block 77 in time determined by the time delay for the regeneration of the additional element block 77, ° which forms the front 116. The 1-front 116. performs the regeneration of the block 78 through, time determined by the time delay for the regeneration of the additional element of the block 78, which creates the front 117-sign. the end of the regeneration blocks. Prisov-. When the conditions for terminating the reception of information in registers are reduced and the registra- tion ends in blocks in block 82, 118 are formed, indicating the presence of a decisive logical level in the drive, 100. reading information from the block 77 in the programmable address. Through BpeNM, determined by the junction time in the additional element of block 77, the front 119 arises, causing the information in the block 78 to be read. Che {time, 6 time determined by the timeout and the dB element 78, occurs ((120, which is a sign of devices to the Microdirectory. When this coincidence coincides with the lower level of the logical one, the front edge 121 of the output signal at the output terminal 88 is generated. In an output (the output signal occurs, the microcode of the issuing code occurs through the output amplifiers 8 0 read to pins 84, 4SS-i - .r-: rV - wV .-. - 25 16 write part of the output code to the register. Feedback in the absence of a mask sign in bit 88, set the signs of the need to receive information in nodes 75 and 76. If there is a T-shirt feature in bit 87 to outputs 84, a code 1, 1, ..., 1 is output. When a negative front 101 arrives at pin 97, a new sampling cycle of the next micro-command begins, to increase the In order to output the microcode code, it is necessary to unite the pins 73, 74, 83, 89 97 and 100 of several devices. In this case, the output bit capacitance is doubled, twice, etc. depending on the parallel connected devices in the unit. Combining conclusions 83, vypol yushih logical function Wired. and, ps you can synchronize the timing of the output of the output code from all devices, regardless of the time transition characteristics in each of them. In order to increase the volume of micro-programs, it is possible to propose an incompatible way to build blocks of microprogram control. In one method of construction, it is necessary to connect several of the T-microprocessor control parallels in parallel, combining the same output 73.74, 83, 89-95, 97, 1OO and 84. At the same time, there are two methods for distributing microtrippole MM for multiple input codes. In one method, this set is divided into separate subsets, which micrographs are packed separately by device, i.e. only one device responds to the arrival of a defined input code, while in other devices, mask masks are generated in bits 87 and e8. In the method, several devices that together form a microinstruction code for the incoming code respond to the arrival of an input code n kidih logic function Wired And when issuing. .It is advisable to use both of these methods in the distribution of mr: k {l Program. The maximum depth of the micro subprogram in one firmware control device is limited by the size of the feedback register. In FIG. 6 of the chapter is an example of a parallel-sequential construction of a firmware control firmware at three facilities 122-124. Conclusions 73 and 8992 of the device 122j are combined with the input highway through which the command information enters the block with a sign that identifies its presence in time. The combined pins 74, 93, 94, and 96 of the devices 122-124 are combined with the input highway, through which information is received in the block for internal conditional nepie moves. The combined pins 84 of the device 123 and 124 are connected to the output mic- “RO-command trunk. At pin 97, connect both devices 123 and 124, an external signal is received (for example: from the processor unit), which triggers the micro-command sampling cycle. A logical ursyb is applied to WRTL 100 in devices 123 and 124, enabling the use of information. Conclusions 84 in devices 123 and 124 are combined to synchronize the simultaneous issuance of a micro-command code. One of the pins 84, pins 97 and 10O of the device 122 are connected respectively to the pins 9O-92 of the device 12 3 and 124. The remaining pins 84 from the building-i 122 pgb are connected to the pins 73 of the devices 123. to 124. Command code 1 , arriving at pins 73 of device 122, unfolds into a series of codes that occur at pins 84 of that device. Each of these codes enters the devices and-124 unfolds into the sequence of microscopes on the combined pins 84 of these devices. FIG. Figure 7 shows an example of building a microprocessor-based computing system consisting of one processor unit 125 and unit 126 of microprocessor control. The processor unit on the micro-comaid trunk (shvodm 21 if 35) is integrated with the microprocessor control unit (output) and 84), yyr-: Ch0M combined output 37 of the HHTerpan processor components in the processing unit connected to the output 97 of the ingeral devices mikroshchiyu with a gram of the replication. The state line (pins 28, 33, and 34) of the processor unit is combined with the input state line (pins 74, 94, and 95) of the microprogrammed control unit. The other two highways of the processor unit are the subalux address and information mainlines of the memory blocks and &IOKOB; UVV. AT; The ONE command line (pins 73, 90 and 91) of the microprogram control unit is combined with the information line (pins 23, 31 and 32).

 the information line enters the microprogram control unit with command information, decodes in this block into a sequence of microcommands, and the number of information processed in the processing unit is received and issued. A sample of a microcommand in a microprogram mapping unit combines in time with the execution of the previous I microcommand in a processor unit. Code ., ; Pre {1Bani is fed to the inputs of the microprogram control unit and is accepted simultaneously with the command information. The introduction of work cycle shaping units and autonomous exchange control nodes allows for the construction of functions; lithium systems, the hardware costs are 10%. These costs are associated with the construction of synchronization units and the exchange organization. Since the execution time of arithmetic operations in a device for performing operations depends on the operand codes, as well as only on its own delays, the average operation time for a processor unit of 16–32 bits is reduced by 15-25%, respectively, compared to microprocess-: SO {smart computer systems. The flexible organization of control and synchronization in the firmware management system allows you to build parallel ones; sequential and parallel sequential blocks of firmware control with various methods increased the volume of firmware, depth. microprograms, microcommand orders, which is special (5on6 is important for comModication systems. OOrmULAI operations contains an arithmetic unit, a shifter, a result register, register conditions, a microinstructions register, microoperations, information exchange units connected to the Bidirectional information to us, and the general register register, the output of the arithmetic – oceanic block through the buffer register is connected to the input of the shifter, the register of microinstructions is connected to the control bus, and the output of the interface dashi4 |) microprocessor / each of the same type of microprogram contains many consecutively connected bdcs programmable addresses and microinstructions memory block, a group of programmable elements NOT, feedback register, the paraphase outputs of which are connected to the first group of inputs of the programmable address block c, and the information input through the first group of softwares (the 1Mirovannye elements are NOT connected to the first output of the microinstructions memory block, the second output of the second through the last connected to the second group of the NOT and uyli11 “Lit consider connected to the output of the device, ff and part, which is connected to the output device, ff and part1 u & with that. a y u & with that from yelyu.-povyshygyy proiShedy ol.nootK, adjustment flexibility and expansion capability, feKajkfloe device 1aypolno11i operations system vvodeng node expansion ryzr of clarity, Us- l1 autonomous uprav1leni: exchange and block forming cycle, the input of which is connected to -Start the control input of the device, the inputs and outputs are connected respectively to the inputs and outputs of the device and to the same inputs and outputs of other devices of operation, the first control input is connected to the responsible Exit arithmetic and logic unit, two output through the discharge unit expansion of clarity and two inputs connected to the respective device and moves to the corresponding outputs of other devices performing operations auxiliary unpasneHtia exchange nodes connected to so6tE ETG stvuyushimi; the inputs and output of the device and the boarder are the highest inputs and outputs in the DrugOrs. The device is equipped with control inputs and system wiring, the output of each node is autonomous nbb exchange control connected to the control unit eboTBercifBjTOniero information exchange unit, controlling and connected to the corresponding outputs of the output and block of the unit { “1I: the work of the working Cycle, the second control of which Voedans with the corresponding output of the Diagrams M11k | l and the first input of the state register connects to the first information bus of the device, the inputs

The first and second information exchange blocks, the output of the result register, the first output of the general purpose register block, the first input of the arithmetic logic unit and the first perHctpa state output are connected to the second information bus of the device, the third information exchange unit input is connected to the second output of the status register The second input of which is connected to the second output of the shifter, which is connected by two-way links to the bit expansion node, which is connected by the control inputs and outputs to the corresponding inputs and the device outputs, the outputs of the micro-operation decoder and the operating cycle shaping unit, the output of the micro-command register and the second output of the general register block: the values are connected to the second input of the arithmetic-logical unit, the control inputs, the micro-command register register with the corresponding output of the operating cycle shaping unit, the control inputs of the STATUS register, the size expansion node, the general purpose register block and the result register are connected to the corresponding microscopic flow paths || The working cycle shaping unit and unit, whose input is connected to the control input of the buffer register, controls the input of the arithmetic-logic unit to the corresponding output of the microscopic decoder, and the switch, the registers, information inputs of which are connected to the corresponding microscopic control unit output with the corresponding inputs of the device, and the paraphase Waste is connected to the second group of inputs of the block of programmable addresses, the work cycle setting block, at the control input to which is connected to the input the control input of the device, the autonomous control units for receiving information, the first output of each of which is connected to the control input. The home of the tseigbet tseigbager b with the corresponding input of the work cycle setting block, the outputs of which are connected respectively to the control inputs of the read amplifiers, the feedback register and the block of programmable addresses, the third and fourth outputs of the microcommand memory block through the switch are connected respectively to the control inputs of the amplifiers readout and register of the feedback connection, with the first inputs of the nodes of the auto-HOMlJoro control information reception, the second and third inputs and outputs of each

21 of which are connected to the inputs and outputs of the device and with the corresponding inputs and outputs of other microprocessor devices 1: x) of the control, the second input and output of each node of the autonomous information reception control are connected to the corresponding transmission control buses, and the third input is connected to the control input of the system, the fourth output of the memory block micro 674025

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commands is connected to the corresponding input of the work cycle task block. Sources of information taken into account Yry expertise 1. Electronics, trans. from English, ed. Mir, M “18, 1974. 2. US Patent No. 3878514, cl. 340-172.5, 08.04.75. 3. Electronics, trans. from English., ed. 0: World, № 12, 1973, p. 44-54.

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